Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/irq.c

   1 /*
   2  * linux/arch/arm/mach-omap2/irq.c
   3  *
   4  * Interrupt handler for OMAP2 boards.
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License. See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/exception.h>
  20 #include <asm/mach/irq.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24
  25 #include <mach/hardware.h>
  26
  27 #include "iomap.h"
  28
  29 /* selected INTC register offsets */
  30
  31 #define INTC_REVISION           0x0000
  32 #define INTC_SYSCONFIG          0x0010
  33 #define INTC_SYSSTATUS          0x0014
  34 #define INTC_SIR                0x0040
  35 #define INTC_CONTROL            0x0048
  36 #define INTC_PROTECTION         0x004C
  37 #define INTC_IDLE               0x0050
  38 #define INTC_THRESHOLD          0x0068
  39 #define INTC_MIR0               0x0084
  40 #define INTC_MIR_CLEAR0         0x0088
  41 #define INTC_MIR_SET0           0x008c
  42 #define INTC_PENDING_IRQ0       0x0098
  43 /* Number of IRQ state bits in each MIR register */
  44 #define IRQ_BITS_PER_REG        32
  45
  46 #define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
  47 #define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
  48 #define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
  49 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
  50
  51 /*
  52  * OMAP2 has a number of different interrupt controllers, each interrupt
  53  * controller is identified as its own "bank". Register definitions are
  54  * fairly consistent for each bank, but not all registers are implemented
  55  * for each bank.. when in doubt, consult the TRM.
  56  */
  57 static struct omap_irq_bank {
  58         void __iomem *base_reg;
  59         unsigned int nr_irqs;
  60 } __attribute__ ((aligned(4))) irq_banks[] = {
  61         {
  62                 /* MPU INTC */
  63                 .nr_irqs        = 96,
  64         },
  65 };
  66
  67 static struct irq_domain *domain;
  68
  69 /* Structure to save interrupt controller context */
  70 struct omap3_intc_regs {
  71         u32 sysconfig;
  72         u32 protection;
  73         u32 idle;
  74         u32 threshold;
  75         u32 ilr[INTCPS_NR_IRQS];
  76         u32 mir[INTCPS_NR_MIR_REGS];
  77 };
  78
  79 /* INTC bank register get/set */
  80
  81 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
  82 {
  83         __raw_writel(val, bank->base_reg + reg);
  84 }
  85
  86 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
  87 {
  88         return __raw_readl(bank->base_reg + reg);
  89 }
  90
  91 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
  92 static void omap_ack_irq(struct irq_data *d)
  93 {
  94         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
  95 }
  96
  97 static void omap_mask_ack_irq(struct irq_data *d)
  98 {
  99         irq_gc_mask_disable_reg(d);
 100         omap_ack_irq(d);
 101 }
 102
 103 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 104 {
 105         unsigned long tmp;
 106
 107         tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
 108         printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
 109                          "(revision %ld.%ld) with %d interrupts\n",
 110                          bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
 111
 112         tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
 113         tmp |= 1 << 1;  /* soft reset */
 114         intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
 115
 116         while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
 117                 /* Wait for reset to complete */;
 118
 119         /* Enable autoidle */
 120         intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
 121 }
 122
 123 int omap_irq_pending(void)
 124 {
 125         int i;
 126
 127         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 128                 struct omap_irq_bank *bank = irq_banks + i;
 129                 int irq;
 130
 131                 for (irq = 0; irq < bank->nr_irqs; irq += 32)
 132                         if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
 133                                                ((irq >> 5) << 5)))
 134                                 return 1;
 135         }
 136         return 0;
 137 }
 138
 139 static __init void
 140 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 141 {
 142         struct irq_chip_generic *gc;
 143         struct irq_chip_type *ct;
 144
 145         gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
 146                                         handle_level_irq);
 147         ct = gc->chip_types;
 148         ct->chip.irq_ack = omap_mask_ack_irq;
 149         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 150         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 151
 152         ct->regs.ack = INTC_CONTROL;
 153         ct->regs.enable = INTC_MIR_CLEAR0;
 154         ct->regs.disable = INTC_MIR_SET0;
 155         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
 156                                 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 157 }
 158
 159 static void __init omap_init_irq(u32 base, int nr_irqs,
 160                                  struct device_node *node)
 161 {
 162         void __iomem *omap_irq_base;
 163         unsigned long nr_of_irqs = 0;
 164         unsigned int nr_banks = 0;
 165         int i, j, irq_base;
 166
 167         omap_irq_base = ioremap(base, SZ_4K);
 168         if (WARN_ON(!omap_irq_base))
 169                 return;
 170
 171         irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
 172         if (irq_base < 0) {
 173                 pr_warn("Couldn't allocate IRQ numbers\n");
 174                 irq_base = 0;
 175         }
 176
 177         domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
 178                                        &irq_domain_simple_ops, NULL);
 179
 180         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 181                 struct omap_irq_bank *bank = irq_banks + i;
 182
 183                 bank->nr_irqs = nr_irqs;
 184
 185                 /* Static mapping, never released */
 186                 bank->base_reg = ioremap(base, SZ_4K);
 187                 if (!bank->base_reg) {
 188                         pr_err("Could not ioremap irq bank%i\n", i);
 189                         continue;
 190                 }
 191
 192                 omap_irq_bank_init_one(bank);
 193
 194                 for (j = 0; j < bank->nr_irqs; j += 32)
 195                         omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
 196
 197                 nr_of_irqs += bank->nr_irqs;
 198                 nr_banks++;
 199         }
 200
 201         pr_info("Total of %ld interrupts on %d active controller%s\n",
 202                 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 203 }
 204
 205 void __init omap2_init_irq(void)
 206 {
 207         omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
 208 }
 209
 210 void __init omap3_init_irq(void)
 211 {
 212         omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
 213 }
 214
 215 void __init ti81xx_init_irq(void)
 216 {
 217         omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
 218 }
 219
 220 static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
 221 {
 222         u32 irqnr;
 223
 224         do {
 225                 irqnr = readl_relaxed(base_addr + 0x98);
 226                 if (irqnr)
 227                         goto out;
 228
 229                 irqnr = readl_relaxed(base_addr + 0xb8);
 230                 if (irqnr)
 231                         goto out;
 232
 233                 irqnr = readl_relaxed(base_addr + 0xd8);
 234 #ifdef CONFIG_SOC_OMAPTI816X
 235                 if (irqnr)
 236                         goto out;
 237                 irqnr = readl_relaxed(base_addr + 0xf8);
 238 #endif
 239
 240 out:
 241                 if (!irqnr)
 242                         break;
 243
 244                 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
 245                 irqnr &= ACTIVEIRQ_MASK;
 246
 247                 if (irqnr) {
 248                         irqnr = irq_find_mapping(domain, irqnr);
 249                         handle_IRQ(irqnr, regs);
 250                 }
 251         } while (irqnr);
 252 }
 253
 254 asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
 255 {
 256         void __iomem *base_addr = OMAP2_IRQ_BASE;
 257         omap_intc_handle_irq(base_addr, regs);
 258 }
 259
 260 int __init omap_intc_of_init(struct device_node *node,
 261                              struct device_node *parent)
 262 {
 263         struct resource res;
 264         u32 nr_irqs = 96;
 265
 266         if (WARN_ON(!node))
 267                 return -ENODEV;
 268
 269         if (of_address_to_resource(node, 0, &res)) {
 270                 WARN(1, "unable to get intc registers\n");
 271                 return -EINVAL;
 272         }
 273
 274         if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
 275                 pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
 276
 277         omap_init_irq(res.start, nr_irqs, of_node_get(node));
 278
 279         return 0;
 280 }
 281
 282 #ifdef CONFIG_ARCH_OMAP3
 283 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 284
 285 void omap_intc_save_context(void)
 286 {
 287         int ind = 0, i = 0;
 288         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
 289                 struct omap_irq_bank *bank = irq_banks + ind;
 290                 intc_context[ind].sysconfig =
 291                         intc_bank_read_reg(bank, INTC_SYSCONFIG);
 292                 intc_context[ind].protection =
 293                         intc_bank_read_reg(bank, INTC_PROTECTION);
 294                 intc_context[ind].idle =
 295                         intc_bank_read_reg(bank, INTC_IDLE);
 296                 intc_context[ind].threshold =
 297                         intc_bank_read_reg(bank, INTC_THRESHOLD);
 298                 for (i = 0; i < INTCPS_NR_IRQS; i++)
 299                         intc_context[ind].ilr[i] =
 300                                 intc_bank_read_reg(bank, (0x100 + 0x4*i));
 301                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 302                         intc_context[ind].mir[i] =
 303                                 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
 304                                 (0x20 * i));
 305         }
 306 }
 307
 308 void omap_intc_restore_context(void)
 309 {
 310         int ind = 0, i = 0;
 311
 312         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
 313                 struct omap_irq_bank *bank = irq_banks + ind;
 314                 intc_bank_write_reg(intc_context[ind].sysconfig,
 315                                         bank, INTC_SYSCONFIG);
 316                 intc_bank_write_reg(intc_context[ind].sysconfig,
 317                                         bank, INTC_SYSCONFIG);
 318                 intc_bank_write_reg(intc_context[ind].protection,
 319                                         bank, INTC_PROTECTION);
 320                 intc_bank_write_reg(intc_context[ind].idle,
 321                                         bank, INTC_IDLE);
 322                 intc_bank_write_reg(intc_context[ind].threshold,
 323                                         bank, INTC_THRESHOLD);
 324                 for (i = 0; i < INTCPS_NR_IRQS; i++)
 325                         intc_bank_write_reg(intc_context[ind].ilr[i],
 326                                 bank, (0x100 + 0x4*i));
 327                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 328                         intc_bank_write_reg(intc_context[ind].mir[i],
 329                                  &irq_banks[0], INTC_MIR0 + (0x20 * i));
 330         }
 331         /* MIRs are saved and restore with other PRCM registers */
 332 }
 333
 334 void omap3_intc_suspend(void)
 335 {
 336         /* A pending interrupt would prevent OMAP from entering suspend */
 337         omap_ack_irq(0);
 338 }
 339
 340 void omap3_intc_prepare_idle(void)
 341 {
 342         /*
 343          * Disable autoidle as it can stall interrupt controller,
 344          * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
 345          */
 346         intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
 347 }
 348
 349 void omap3_intc_resume_idle(void)
 350 {
 351         /* Re-enable autoidle */
 352         intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
 353 }
 354
 355 asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
 356 {
 357         void __iomem *base_addr = OMAP3_IRQ_BASE;
 358         omap_intc_handle_irq(base_addr, regs);
 359 }
 360 #endif /* CONFIG_ARCH_OMAP3 */