Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/irq.c

   1 /*
   2  * linux/arch/arm/mach-omap2/irq.c
   3  *
   4  * Interrupt handler for OMAP2 boards.
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License. See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/exception.h>
  20 #include <asm/mach/irq.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24
  25 #include <mach/hardware.h>
  26
  27 #include "iomap.h"
  28 #include "common.h"
  29
  30 /* selected INTC register offsets */
  31
  32 #define INTC_REVISION           0x0000
  33 #define INTC_SYSCONFIG          0x0010
  34 #define INTC_SYSSTATUS          0x0014
  35 #define INTC_SIR                0x0040
  36 #define INTC_CONTROL            0x0048
  37 #define INTC_PROTECTION         0x004C
  38 #define INTC_IDLE               0x0050
  39 #define INTC_THRESHOLD          0x0068
  40 #define INTC_MIR0               0x0084
  41 #define INTC_MIR_CLEAR0         0x0088
  42 #define INTC_MIR_SET0           0x008c
  43 #define INTC_PENDING_IRQ0       0x0098
  44 /* Number of IRQ state bits in each MIR register */
  45 #define IRQ_BITS_PER_REG        32
  46
  47 #define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
  48 #define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
  49 #define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
  50 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
  51
  52 /*
  53  * OMAP2 has a number of different interrupt controllers, each interrupt
  54  * controller is identified as its own "bank". Register definitions are
  55  * fairly consistent for each bank, but not all registers are implemented
  56  * for each bank.. when in doubt, consult the TRM.
  57  */
  58 static struct omap_irq_bank {
  59         void __iomem *base_reg;
  60         unsigned int nr_irqs;
  61 } __attribute__ ((aligned(4))) irq_banks[] = {
  62         {
  63                 /* MPU INTC */
  64                 .nr_irqs        = 96,
  65         },
  66 };
  67
  68 static struct irq_domain *domain;
  69
  70 /* Structure to save interrupt controller context */
  71 struct omap3_intc_regs {
  72         u32 sysconfig;
  73         u32 protection;
  74         u32 idle;
  75         u32 threshold;
  76         u32 ilr[INTCPS_NR_IRQS];
  77         u32 mir[INTCPS_NR_MIR_REGS];
  78 };
  79
  80 /* INTC bank register get/set */
  81
  82 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
  83 {
  84         __raw_writel(val, bank->base_reg + reg);
  85 }
  86
  87 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
  88 {
  89         return __raw_readl(bank->base_reg + reg);
  90 }
  91
  92 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
  93 static void omap_ack_irq(struct irq_data *d)
  94 {
  95         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
  96 }
  97
  98 static void omap_mask_ack_irq(struct irq_data *d)
  99 {
 100         irq_gc_mask_disable_reg(d);
 101         omap_ack_irq(d);
 102 }
 103
 104 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 105 {
 106         unsigned long tmp;
 107
 108         tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
 109         printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
 110                          "(revision %ld.%ld) with %d interrupts\n",
 111                          bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
 112
 113         tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
 114         tmp |= 1 << 1;  /* soft reset */
 115         intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
 116
 117         while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
 118                 /* Wait for reset to complete */;
 119
 120         /* Enable autoidle */
 121         intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
 122 }
 123
 124 int omap_irq_pending(void)
 125 {
 126         int i;
 127
 128         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 129                 struct omap_irq_bank *bank = irq_banks + i;
 130                 int irq;
 131
 132                 for (irq = 0; irq < bank->nr_irqs; irq += 32)
 133                         if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
 134                                                ((irq >> 5) << 5)))
 135                                 return 1;
 136         }
 137         return 0;
 138 }
 139
 140 static __init void
 141 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 142 {
 143         struct irq_chip_generic *gc;
 144         struct irq_chip_type *ct;
 145
 146         gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
 147                                         handle_level_irq);
 148         ct = gc->chip_types;
 149         ct->chip.irq_ack = omap_mask_ack_irq;
 150         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 151         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 152         ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
 153
 154         ct->regs.enable = INTC_MIR_CLEAR0;
 155         ct->regs.disable = INTC_MIR_SET0;
 156         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
 157                                 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 158 }
 159
 160 static void __init omap_init_irq(u32 base, int nr_irqs,
 161                                  struct device_node *node)
 162 {
 163         void __iomem *omap_irq_base;
 164         unsigned long nr_of_irqs = 0;
 165         unsigned int nr_banks = 0;
 166         int i, j, irq_base;
 167
 168         omap_irq_base = ioremap(base, SZ_4K);
 169         if (WARN_ON(!omap_irq_base))
 170                 return;
 171
 172         irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
 173         if (irq_base < 0) {
 174                 pr_warn("Couldn't allocate IRQ numbers\n");
 175                 irq_base = 0;
 176         }
 177
 178         domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
 179                                        &irq_domain_simple_ops, NULL);
 180
 181         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 182                 struct omap_irq_bank *bank = irq_banks + i;
 183
 184                 bank->nr_irqs = nr_irqs;
 185
 186                 /* Static mapping, never released */
 187                 bank->base_reg = ioremap(base, SZ_4K);
 188                 if (!bank->base_reg) {
 189                         pr_err("Could not ioremap irq bank%i\n", i);
 190                         continue;
 191                 }
 192
 193                 omap_irq_bank_init_one(bank);
 194
 195                 for (j = 0; j < bank->nr_irqs; j += 32)
 196                         omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
 197
 198                 nr_of_irqs += bank->nr_irqs;
 199                 nr_banks++;
 200         }
 201
 202         pr_info("Total of %ld interrupts on %d active controller%s\n",
 203                 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 204 }
 205
 206 void __init omap2_init_irq(void)
 207 {
 208         omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
 209 }
 210
 211 void __init omap3_init_irq(void)
 212 {
 213         omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
 214 }
 215
 216 void __init ti81xx_init_irq(void)
 217 {
 218         omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
 219 }
 220
 221 static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
 222 {
 223         u32 irqnr;
 224
 225         do {
 226                 irqnr = readl_relaxed(base_addr + 0x98);
 227                 if (irqnr)
 228                         goto out;
 229
 230                 irqnr = readl_relaxed(base_addr + 0xb8);
 231                 if (irqnr)
 232                         goto out;
 233
 234                 irqnr = readl_relaxed(base_addr + 0xd8);
 235 #ifdef CONFIG_SOC_TI81XX
 236                 if (irqnr)
 237                         goto out;
 238                 irqnr = readl_relaxed(base_addr + 0xf8);
 239 #endif
 240
 241 out:
 242                 if (!irqnr)
 243                         break;
 244
 245                 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
 246                 irqnr &= ACTIVEIRQ_MASK;
 247
 248                 if (irqnr) {
 249                         irqnr = irq_find_mapping(domain, irqnr);
 250                         handle_IRQ(irqnr, regs);
 251                 }
 252         } while (irqnr);
 253 }
 254
 255 asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
 256 {
 257         void __iomem *base_addr = OMAP2_IRQ_BASE;
 258         omap_intc_handle_irq(base_addr, regs);
 259 }
 260
 261 int __init omap_intc_of_init(struct device_node *node,
 262                              struct device_node *parent)
 263 {
 264         struct resource res;
 265         u32 nr_irqs = 96;
 266
 267         if (WARN_ON(!node))
 268                 return -ENODEV;
 269
 270         if (of_address_to_resource(node, 0, &res)) {
 271                 WARN(1, "unable to get intc registers\n");
 272                 return -EINVAL;
 273         }
 274
 275         if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
 276                 pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
 277
 278         omap_init_irq(res.start, nr_irqs, of_node_get(node));
 279
 280         return 0;
 281 }
 282
 283 #ifdef CONFIG_ARCH_OMAP3
 284 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 285
 286 void omap_intc_save_context(void)
 287 {
 288         int ind = 0, i = 0;
 289         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
 290                 struct omap_irq_bank *bank = irq_banks + ind;
 291                 intc_context[ind].sysconfig =
 292                         intc_bank_read_reg(bank, INTC_SYSCONFIG);
 293                 intc_context[ind].protection =
 294                         intc_bank_read_reg(bank, INTC_PROTECTION);
 295                 intc_context[ind].idle =
 296                         intc_bank_read_reg(bank, INTC_IDLE);
 297                 intc_context[ind].threshold =
 298                         intc_bank_read_reg(bank, INTC_THRESHOLD);
 299                 for (i = 0; i < INTCPS_NR_IRQS; i++)
 300                         intc_context[ind].ilr[i] =
 301                                 intc_bank_read_reg(bank, (0x100 + 0x4*i));
 302                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 303                         intc_context[ind].mir[i] =
 304                                 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
 305                                 (0x20 * i));
 306         }
 307 }
 308
 309 void omap_intc_restore_context(void)
 310 {
 311         int ind = 0, i = 0;
 312
 313         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
 314                 struct omap_irq_bank *bank = irq_banks + ind;
 315                 intc_bank_write_reg(intc_context[ind].sysconfig,
 316                                         bank, INTC_SYSCONFIG);
 317                 intc_bank_write_reg(intc_context[ind].sysconfig,
 318                                         bank, INTC_SYSCONFIG);
 319                 intc_bank_write_reg(intc_context[ind].protection,
 320                                         bank, INTC_PROTECTION);
 321                 intc_bank_write_reg(intc_context[ind].idle,
 322                                         bank, INTC_IDLE);
 323                 intc_bank_write_reg(intc_context[ind].threshold,
 324                                         bank, INTC_THRESHOLD);
 325                 for (i = 0; i < INTCPS_NR_IRQS; i++)
 326                         intc_bank_write_reg(intc_context[ind].ilr[i],
 327                                 bank, (0x100 + 0x4*i));
 328                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 329                         intc_bank_write_reg(intc_context[ind].mir[i],
 330                                  &irq_banks[0], INTC_MIR0 + (0x20 * i));
 331         }
 332         /* MIRs are saved and restore with other PRCM registers */
 333 }
 334
 335 void omap3_intc_suspend(void)
 336 {
 337         /* A pending interrupt would prevent OMAP from entering suspend */
 338         omap_ack_irq(NULL);
 339 }
 340
 341 void omap3_intc_prepare_idle(void)
 342 {
 343         /*
 344          * Disable autoidle as it can stall interrupt controller,
 345          * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
 346          */
 347         intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
 348 }
 349
 350 void omap3_intc_resume_idle(void)
 351 {
 352         /* Re-enable autoidle */
 353         intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
 354 }
 355
 356 asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
 357 {
 358         void __iomem *base_addr = OMAP3_IRQ_BASE;
 359         omap_intc_handle_irq(base_addr, regs);
 360 }
 361 #endif /* CONFIG_ARCH_OMAP3 */