Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/irq.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/ioport.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/io.h>
  25 #include <linux/module.h>
  26 #include <linux/interrupt.h>
  27
  28 #include <asm/mach-types.h>
  29 #include <plat/gpmc.h>
  30
  31 #include <plat/sdrc.h>
  32
  33 /* GPMC register offsets */
  34 #define GPMC_REVISION           0x00
  35 #define GPMC_SYSCONFIG          0x10
  36 #define GPMC_SYSSTATUS          0x14
  37 #define GPMC_IRQSTATUS          0x18
  38 #define GPMC_IRQENABLE          0x1c
  39 #define GPMC_TIMEOUT_CONTROL    0x40
  40 #define GPMC_ERR_ADDRESS        0x44
  41 #define GPMC_ERR_TYPE           0x48
  42 #define GPMC_CONFIG             0x50
  43 #define GPMC_STATUS             0x54
  44 #define GPMC_PREFETCH_CONFIG1   0x1e0
  45 #define GPMC_PREFETCH_CONFIG2   0x1e4
  46 #define GPMC_PREFETCH_CONTROL   0x1ec
  47 #define GPMC_PREFETCH_STATUS    0x1f0
  48 #define GPMC_ECC_CONFIG         0x1f4
  49 #define GPMC_ECC_CONTROL        0x1f8
  50 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  51 #define GPMC_ECC1_RESULT        0x200
  52
  53 /* GPMC ECC control settings */
  54 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  55 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  56 #define GPMC_ECC_CTRL_ECCREG1           0x001
  57 #define GPMC_ECC_CTRL_ECCREG2           0x002
  58 #define GPMC_ECC_CTRL_ECCREG3           0x003
  59 #define GPMC_ECC_CTRL_ECCREG4           0x004
  60 #define GPMC_ECC_CTRL_ECCREG5           0x005
  61 #define GPMC_ECC_CTRL_ECCREG6           0x006
  62 #define GPMC_ECC_CTRL_ECCREG7           0x007
  63 #define GPMC_ECC_CTRL_ECCREG8           0x008
  64 #define GPMC_ECC_CTRL_ECCREG9           0x009
  65
  66 #define GPMC_CS0_OFFSET         0x60
  67 #define GPMC_CS_SIZE            0x30
  68
  69 #define GPMC_MEM_START          0x00000000
  70 #define GPMC_MEM_END            0x3FFFFFFF
  71 #define BOOT_ROM_SPACE          0x100000        /* 1MB */
  72
  73 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
  74 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
  75
  76 #define CS_NUM_SHIFT            24
  77 #define ENABLE_PREFETCH         (0x1 << 7)
  78 #define DMA_MPU_MODE            2
  79
  80 /* Structure to save gpmc cs context */
  81 struct gpmc_cs_config {
  82         u32 config1;
  83         u32 config2;
  84         u32 config3;
  85         u32 config4;
  86         u32 config5;
  87         u32 config6;
  88         u32 config7;
  89         int is_valid;
  90 };
  91
  92 /*
  93  * Structure to save/restore gpmc context
  94  * to support core off on OMAP3
  95  */
  96 struct omap3_gpmc_regs {
  97         u32 sysconfig;
  98         u32 irqenable;
  99         u32 timeout_ctrl;
 100         u32 config;
 101         u32 prefetch_config1;
 102         u32 prefetch_config2;
 103         u32 prefetch_control;
 104         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 105 };
 106
 107 static struct resource  gpmc_mem_root;
 108 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 109 static DEFINE_SPINLOCK(gpmc_mem_lock);
 110 static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
 111 static int gpmc_ecc_used = -EINVAL;     /* cs using ecc engine */
 112
 113 static void __iomem *gpmc_base;
 114
 115 static struct clk *gpmc_l3_clk;
 116
 117 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 118
 119 static void gpmc_write_reg(int idx, u32 val)
 120 {
 121         __raw_writel(val, gpmc_base + idx);
 122 }
 123
 124 static u32 gpmc_read_reg(int idx)
 125 {
 126         return __raw_readl(gpmc_base + idx);
 127 }
 128
 129 static void gpmc_cs_write_byte(int cs, int idx, u8 val)
 130 {
 131         void __iomem *reg_addr;
 132
 133         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 134         __raw_writeb(val, reg_addr);
 135 }
 136
 137 static u8 gpmc_cs_read_byte(int cs, int idx)
 138 {
 139         void __iomem *reg_addr;
 140
 141         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 142         return __raw_readb(reg_addr);
 143 }
 144
 145 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 146 {
 147         void __iomem *reg_addr;
 148
 149         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 150         __raw_writel(val, reg_addr);
 151 }
 152
 153 u32 gpmc_cs_read_reg(int cs, int idx)
 154 {
 155         void __iomem *reg_addr;
 156
 157         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 158         return __raw_readl(reg_addr);
 159 }
 160
 161 /* TODO: Add support for gpmc_fck to clock framework and use it */
 162 unsigned long gpmc_get_fclk_period(void)
 163 {
 164         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 165
 166         if (rate == 0) {
 167                 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
 168                 return 0;
 169         }
 170
 171         rate /= 1000;
 172         rate = 1000000000 / rate;       /* In picoseconds */
 173
 174         return rate;
 175 }
 176
 177 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 178 {
 179         unsigned long tick_ps;
 180
 181         /* Calculate in picosecs to yield more exact results */
 182         tick_ps = gpmc_get_fclk_period();
 183
 184         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 185 }
 186
 187 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 188 {
 189         unsigned long tick_ps;
 190
 191         /* Calculate in picosecs to yield more exact results */
 192         tick_ps = gpmc_get_fclk_period();
 193
 194         return (time_ps + tick_ps - 1) / tick_ps;
 195 }
 196
 197 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 198 {
 199         return ticks * gpmc_get_fclk_period() / 1000;
 200 }
 201
 202 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
 203 {
 204         unsigned long ticks = gpmc_ns_to_ticks(time_ns);
 205
 206         return ticks * gpmc_get_fclk_period() / 1000;
 207 }
 208
 209 #ifdef DEBUG
 210 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 211                                int time, const char *name)
 212 #else
 213 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 214                                int time)
 215 #endif
 216 {
 217         u32 l;
 218         int ticks, mask, nr_bits;
 219
 220         if (time == 0)
 221                 ticks = 0;
 222         else
 223                 ticks = gpmc_ns_to_ticks(time);
 224         nr_bits = end_bit - st_bit + 1;
 225         if (ticks >= 1 << nr_bits) {
 226 #ifdef DEBUG
 227                 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
 228                                 cs, name, time, ticks, 1 << nr_bits);
 229 #endif
 230                 return -1;
 231         }
 232
 233         mask = (1 << nr_bits) - 1;
 234         l = gpmc_cs_read_reg(cs, reg);
 235 #ifdef DEBUG
 236         printk(KERN_INFO
 237                 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 238                cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
 239                         (l >> st_bit) & mask, time);
 240 #endif
 241         l &= ~(mask << st_bit);
 242         l |= ticks << st_bit;
 243         gpmc_cs_write_reg(cs, reg, l);
 244
 245         return 0;
 246 }
 247
 248 #ifdef DEBUG
 249 #define GPMC_SET_ONE(reg, st, end, field) \
 250         if (set_gpmc_timing_reg(cs, (reg), (st), (end),         \
 251                         t->field, #field) < 0)                  \
 252                 return -1
 253 #else
 254 #define GPMC_SET_ONE(reg, st, end, field) \
 255         if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
 256                 return -1
 257 #endif
 258
 259 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
 260 {
 261         int div;
 262         u32 l;
 263
 264         l = sync_clk + (gpmc_get_fclk_period() - 1);
 265         div = l / gpmc_get_fclk_period();
 266         if (div > 4)
 267                 return -1;
 268         if (div <= 0)
 269                 div = 1;
 270
 271         return div;
 272 }
 273
 274 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 275 {
 276         int div;
 277         u32 l;
 278
 279         div = gpmc_cs_calc_divider(cs, t->sync_clk);
 280         if (div < 0)
 281                 return -1;
 282
 283         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 284         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 285         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 286
 287         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 288         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 289         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 290
 291         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 292         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 293         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 294         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 295
 296         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 297         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 298         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 299
 300         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 301
 302         if (cpu_is_omap34xx()) {
 303                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 304                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 305         }
 306
 307         /* caller is expected to have initialized CONFIG1 to cover
 308          * at least sync vs async
 309          */
 310         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 311         if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
 312 #ifdef DEBUG
 313                 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
 314                                 cs, (div * gpmc_get_fclk_period()) / 1000, div);
 315 #endif
 316                 l &= ~0x03;
 317                 l |= (div - 1);
 318                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 319         }
 320
 321         return 0;
 322 }
 323
 324 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
 325 {
 326         u32 l;
 327         u32 mask;
 328
 329         mask = (1 << GPMC_SECTION_SHIFT) - size;
 330         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 331         l &= ~0x3f;
 332         l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
 333         l &= ~(0x0f << 8);
 334         l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
 335         l |= GPMC_CONFIG7_CSVALID;
 336         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 337 }
 338
 339 static void gpmc_cs_disable_mem(int cs)
 340 {
 341         u32 l;
 342
 343         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 344         l &= ~GPMC_CONFIG7_CSVALID;
 345         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 346 }
 347
 348 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 349 {
 350         u32 l;
 351         u32 mask;
 352
 353         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 354         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 355         mask = (l >> 8) & 0x0f;
 356         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 357 }
 358
 359 static int gpmc_cs_mem_enabled(int cs)
 360 {
 361         u32 l;
 362
 363         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 364         return l & GPMC_CONFIG7_CSVALID;
 365 }
 366
 367 int gpmc_cs_set_reserved(int cs, int reserved)
 368 {
 369         if (cs > GPMC_CS_NUM)
 370                 return -ENODEV;
 371
 372         gpmc_cs_map &= ~(1 << cs);
 373         gpmc_cs_map |= (reserved ? 1 : 0) << cs;
 374
 375         return 0;
 376 }
 377
 378 int gpmc_cs_reserved(int cs)
 379 {
 380         if (cs > GPMC_CS_NUM)
 381                 return -ENODEV;
 382
 383         return gpmc_cs_map & (1 << cs);
 384 }
 385
 386 static unsigned long gpmc_mem_align(unsigned long size)
 387 {
 388         int order;
 389
 390         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 391         order = GPMC_CHUNK_SHIFT - 1;
 392         do {
 393                 size >>= 1;
 394                 order++;
 395         } while (size);
 396         size = 1 << order;
 397         return size;
 398 }
 399
 400 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 401 {
 402         struct resource *res = &gpmc_cs_mem[cs];
 403         int r;
 404
 405         size = gpmc_mem_align(size);
 406         spin_lock(&gpmc_mem_lock);
 407         res->start = base;
 408         res->end = base + size - 1;
 409         r = request_resource(&gpmc_mem_root, res);
 410         spin_unlock(&gpmc_mem_lock);
 411
 412         return r;
 413 }
 414
 415 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 416 {
 417         struct resource *res = &gpmc_cs_mem[cs];
 418         int r = -1;
 419
 420         if (cs > GPMC_CS_NUM)
 421                 return -ENODEV;
 422
 423         size = gpmc_mem_align(size);
 424         if (size > (1 << GPMC_SECTION_SHIFT))
 425                 return -ENOMEM;
 426
 427         spin_lock(&gpmc_mem_lock);
 428         if (gpmc_cs_reserved(cs)) {
 429                 r = -EBUSY;
 430                 goto out;
 431         }
 432         if (gpmc_cs_mem_enabled(cs))
 433                 r = adjust_resource(res, res->start & ~(size - 1), size);
 434         if (r < 0)
 435                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 436                                       size, NULL, NULL);
 437         if (r < 0)
 438                 goto out;
 439
 440         gpmc_cs_enable_mem(cs, res->start, resource_size(res));
 441         *base = res->start;
 442         gpmc_cs_set_reserved(cs, 1);
 443 out:
 444         spin_unlock(&gpmc_mem_lock);
 445         return r;
 446 }
 447 EXPORT_SYMBOL(gpmc_cs_request);
 448
 449 void gpmc_cs_free(int cs)
 450 {
 451         spin_lock(&gpmc_mem_lock);
 452         if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
 453                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
 454                 BUG();
 455                 spin_unlock(&gpmc_mem_lock);
 456                 return;
 457         }
 458         gpmc_cs_disable_mem(cs);
 459         release_resource(&gpmc_cs_mem[cs]);
 460         gpmc_cs_set_reserved(cs, 0);
 461         spin_unlock(&gpmc_mem_lock);
 462 }
 463 EXPORT_SYMBOL(gpmc_cs_free);
 464
 465 /**
 466  * gpmc_read_status - read access request to get the different gpmc status
 467  * @cmd: command type
 468  * @return status
 469  */
 470 int gpmc_read_status(int cmd)
 471 {
 472         int     status = -EINVAL;
 473         u32     regval = 0;
 474
 475         switch (cmd) {
 476         case GPMC_GET_IRQ_STATUS:
 477                 status = gpmc_read_reg(GPMC_IRQSTATUS);
 478                 break;
 479
 480         case GPMC_PREFETCH_FIFO_CNT:
 481                 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
 482                 status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
 483                 break;
 484
 485         case GPMC_PREFETCH_COUNT:
 486                 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
 487                 status = GPMC_PREFETCH_STATUS_COUNT(regval);
 488                 break;
 489
 490         case GPMC_STATUS_BUFFER:
 491                 regval = gpmc_read_reg(GPMC_STATUS);
 492                 /* 1 : buffer is available to write */
 493                 status = regval & GPMC_STATUS_BUFF_EMPTY;
 494                 break;
 495
 496         default:
 497                 printk(KERN_ERR "gpmc_read_status: Not supported\n");
 498         }
 499         return status;
 500 }
 501 EXPORT_SYMBOL(gpmc_read_status);
 502
 503 /**
 504  * gpmc_cs_configure - write request to configure gpmc
 505  * @cs: chip select number
 506  * @cmd: command type
 507  * @wval: value to write
 508  * @return status of the operation
 509  */
 510 int gpmc_cs_configure(int cs, int cmd, int wval)
 511 {
 512         int err = 0;
 513         u32 regval = 0;
 514
 515         switch (cmd) {
 516         case GPMC_ENABLE_IRQ:
 517                 gpmc_write_reg(GPMC_IRQENABLE, wval);
 518                 break;
 519
 520         case GPMC_SET_IRQ_STATUS:
 521                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
 522                 break;
 523
 524         case GPMC_CONFIG_WP:
 525                 regval = gpmc_read_reg(GPMC_CONFIG);
 526                 if (wval)
 527                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
 528                 else
 529                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
 530                 gpmc_write_reg(GPMC_CONFIG, regval);
 531                 break;
 532
 533         case GPMC_CONFIG_RDY_BSY:
 534                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 535                 if (wval)
 536                         regval |= WR_RD_PIN_MONITORING;
 537                 else
 538                         regval &= ~WR_RD_PIN_MONITORING;
 539                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 540                 break;
 541
 542         case GPMC_CONFIG_DEV_SIZE:
 543                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 544
 545                 /* clear 2 target bits */
 546                 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
 547
 548                 /* set the proper value */
 549                 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
 550
 551                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 552                 break;
 553
 554         case GPMC_CONFIG_DEV_TYPE:
 555                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 556                 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
 557                 if (wval == GPMC_DEVICETYPE_NOR)
 558                         regval |= GPMC_CONFIG1_MUXADDDATA;
 559                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 560                 break;
 561
 562         default:
 563                 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
 564                 err = -EINVAL;
 565         }
 566
 567         return err;
 568 }
 569 EXPORT_SYMBOL(gpmc_cs_configure);
 570
 571 /**
 572  * gpmc_nand_read - nand specific read access request
 573  * @cs: chip select number
 574  * @cmd: command type
 575  */
 576 int gpmc_nand_read(int cs, int cmd)
 577 {
 578         int rval = -EINVAL;
 579
 580         switch (cmd) {
 581         case GPMC_NAND_DATA:
 582                 rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
 583                 break;
 584
 585         default:
 586                 printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
 587         }
 588         return rval;
 589 }
 590 EXPORT_SYMBOL(gpmc_nand_read);
 591
 592 /**
 593  * gpmc_nand_write - nand specific write request
 594  * @cs: chip select number
 595  * @cmd: command type
 596  * @wval: value to write
 597  */
 598 int gpmc_nand_write(int cs, int cmd, int wval)
 599 {
 600         int err = 0;
 601
 602         switch (cmd) {
 603         case GPMC_NAND_COMMAND:
 604                 gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
 605                 break;
 606
 607         case GPMC_NAND_ADDRESS:
 608                 gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
 609                 break;
 610
 611         case GPMC_NAND_DATA:
 612                 gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
 613
 614         default:
 615                 printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
 616                 err = -EINVAL;
 617         }
 618         return err;
 619 }
 620 EXPORT_SYMBOL(gpmc_nand_write);
 621
 622
 623
 624 /**
 625  * gpmc_prefetch_enable - configures and starts prefetch transfer
 626  * @cs: cs (chip select) number
 627  * @fifo_th: fifo threshold to be used for read/ write
 628  * @dma_mode: dma mode enable (1) or disable (0)
 629  * @u32_count: number of bytes to be transferred
 630  * @is_write: prefetch read(0) or write post(1) mode
 631  */
 632 int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
 633                                 unsigned int u32_count, int is_write)
 634 {
 635
 636         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
 637                 pr_err("gpmc: fifo threshold is not supported\n");
 638                 return -1;
 639         } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
 640                 /* Set the amount of bytes to be prefetched */
 641                 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
 642
 643                 /* Set dma/mpu mode, the prefetch read / post write and
 644                  * enable the engine. Set which cs is has requested for.
 645                  */
 646                 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
 647                                         PREFETCH_FIFOTHRESHOLD(fifo_th) |
 648                                         ENABLE_PREFETCH |
 649                                         (dma_mode << DMA_MPU_MODE) |
 650                                         (0x1 & is_write)));
 651
 652                 /*  Start the prefetch engine */
 653                 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
 654         } else {
 655                 return -EBUSY;
 656         }
 657
 658         return 0;
 659 }
 660 EXPORT_SYMBOL(gpmc_prefetch_enable);
 661
 662 /**
 663  * gpmc_prefetch_reset - disables and stops the prefetch engine
 664  */
 665 int gpmc_prefetch_reset(int cs)
 666 {
 667         u32 config1;
 668
 669         /* check if the same module/cs is trying to reset */
 670         config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
 671         if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
 672                 return -EINVAL;
 673
 674         /* Stop the PFPW engine */
 675         gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
 676
 677         /* Reset/disable the PFPW engine */
 678         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
 679
 680         return 0;
 681 }
 682 EXPORT_SYMBOL(gpmc_prefetch_reset);
 683
 684 static void __init gpmc_mem_init(void)
 685 {
 686         int cs;
 687         unsigned long boot_rom_space = 0;
 688
 689         /* never allocate the first page, to facilitate bug detection;
 690          * even if we didn't boot from ROM.
 691          */
 692         boot_rom_space = BOOT_ROM_SPACE;
 693         /* In apollon the CS0 is mapped as 0x0000 0000 */
 694         if (machine_is_omap_apollon())
 695                 boot_rom_space = 0;
 696         gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
 697         gpmc_mem_root.end = GPMC_MEM_END;
 698
 699         /* Reserve all regions that has been set up by bootloader */
 700         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 701                 u32 base, size;
 702
 703                 if (!gpmc_cs_mem_enabled(cs))
 704                         continue;
 705                 gpmc_cs_get_memconf(cs, &base, &size);
 706                 if (gpmc_cs_insert_mem(cs, base, size) < 0)
 707                         BUG();
 708         }
 709 }
 710
 711 static int __init gpmc_init(void)
 712 {
 713         u32 l, irq;
 714         int cs, ret = -EINVAL;
 715         int gpmc_irq;
 716         char *ck = NULL;
 717
 718         if (cpu_is_omap24xx()) {
 719                 ck = "core_l3_ck";
 720                 if (cpu_is_omap2420())
 721                         l = OMAP2420_GPMC_BASE;
 722                 else
 723                         l = OMAP34XX_GPMC_BASE;
 724                 gpmc_irq = INT_34XX_GPMC_IRQ;
 725         } else if (cpu_is_omap34xx()) {
 726                 ck = "gpmc_fck";
 727                 l = OMAP34XX_GPMC_BASE;
 728                 gpmc_irq = INT_34XX_GPMC_IRQ;
 729         } else if (cpu_is_omap44xx()) {
 730                 ck = "gpmc_ck";
 731                 l = OMAP44XX_GPMC_BASE;
 732                 gpmc_irq = OMAP44XX_IRQ_GPMC;
 733         }
 734
 735         if (WARN_ON(!ck))
 736                 return ret;
 737
 738         gpmc_l3_clk = clk_get(NULL, ck);
 739         if (IS_ERR(gpmc_l3_clk)) {
 740                 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
 741                 BUG();
 742         }
 743
 744         gpmc_base = ioremap(l, SZ_4K);
 745         if (!gpmc_base) {
 746                 clk_put(gpmc_l3_clk);
 747                 printk(KERN_ERR "Could not get GPMC register memory\n");
 748                 BUG();
 749         }
 750
 751         clk_enable(gpmc_l3_clk);
 752
 753         l = gpmc_read_reg(GPMC_REVISION);
 754         printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 755         /* Set smart idle mode and automatic L3 clock gating */
 756         l = gpmc_read_reg(GPMC_SYSCONFIG);
 757         l &= 0x03 << 3;
 758         l |= (0x02 << 3) | (1 << 0);
 759         gpmc_write_reg(GPMC_SYSCONFIG, l);
 760         gpmc_mem_init();
 761
 762         /* initalize the irq_chained */
 763         irq = OMAP_GPMC_IRQ_BASE;
 764         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 765                 irq_set_chip_and_handler(irq, &dummy_irq_chip,
 766                                                 handle_simple_irq);
 767                 set_irq_flags(irq, IRQF_VALID);
 768                 irq++;
 769         }
 770
 771         ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
 772         if (ret)
 773                 pr_err("gpmc: irq-%d could not claim: err %d\n",
 774                                                 gpmc_irq, ret);
 775         return ret;
 776 }
 777 postcore_initcall(gpmc_init);
 778
 779 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 780 {
 781         u8 cs;
 782
 783         /* check cs to invoke the irq */
 784         cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
 785         if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
 786                 generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
 787
 788         return IRQ_HANDLED;
 789 }
 790
 791 #ifdef CONFIG_ARCH_OMAP3
 792 static struct omap3_gpmc_regs gpmc_context;
 793
 794 void omap3_gpmc_save_context(void)
 795 {
 796         int i;
 797
 798         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
 799         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
 800         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
 801         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
 802         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
 803         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
 804         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
 805         for (i = 0; i < GPMC_CS_NUM; i++) {
 806                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
 807                 if (gpmc_context.cs_context[i].is_valid) {
 808                         gpmc_context.cs_context[i].config1 =
 809                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
 810                         gpmc_context.cs_context[i].config2 =
 811                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
 812                         gpmc_context.cs_context[i].config3 =
 813                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
 814                         gpmc_context.cs_context[i].config4 =
 815                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
 816                         gpmc_context.cs_context[i].config5 =
 817                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
 818                         gpmc_context.cs_context[i].config6 =
 819                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
 820                         gpmc_context.cs_context[i].config7 =
 821                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
 822                 }
 823         }
 824 }
 825
 826 void omap3_gpmc_restore_context(void)
 827 {
 828         int i;
 829
 830         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
 831         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
 832         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
 833         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
 834         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
 835         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
 836         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
 837         for (i = 0; i < GPMC_CS_NUM; i++) {
 838                 if (gpmc_context.cs_context[i].is_valid) {
 839                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
 840                                 gpmc_context.cs_context[i].config1);
 841                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
 842                                 gpmc_context.cs_context[i].config2);
 843                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
 844                                 gpmc_context.cs_context[i].config3);
 845                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
 846                                 gpmc_context.cs_context[i].config4);
 847                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
 848                                 gpmc_context.cs_context[i].config5);
 849                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
 850                                 gpmc_context.cs_context[i].config6);
 851                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
 852                                 gpmc_context.cs_context[i].config7);
 853                 }
 854         }
 855 }
 856 #endif /* CONFIG_ARCH_OMAP3 */
 857
 858 /**
 859  * gpmc_enable_hwecc - enable hardware ecc functionality
 860  * @cs: chip select number
 861  * @mode: read/write mode
 862  * @dev_width: device bus width(1 for x16, 0 for x8)
 863  * @ecc_size: bytes for which ECC will be generated
 864  */
 865 int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
 866 {
 867         unsigned int val;
 868
 869         /* check if ecc module is in used */
 870         if (gpmc_ecc_used != -EINVAL)
 871                 return -EINVAL;
 872
 873         gpmc_ecc_used = cs;
 874
 875         /* clear ecc and enable bits */
 876         gpmc_write_reg(GPMC_ECC_CONTROL,
 877                         GPMC_ECC_CTRL_ECCCLEAR |
 878                         GPMC_ECC_CTRL_ECCREG1);
 879
 880         /* program ecc and result sizes */
 881         val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
 882         gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
 883
 884         switch (mode) {
 885         case GPMC_ECC_READ:
 886         case GPMC_ECC_WRITE:
 887                 gpmc_write_reg(GPMC_ECC_CONTROL,
 888                                 GPMC_ECC_CTRL_ECCCLEAR |
 889                                 GPMC_ECC_CTRL_ECCREG1);
 890                 break;
 891         case GPMC_ECC_READSYN:
 892                 gpmc_write_reg(GPMC_ECC_CONTROL,
 893                                 GPMC_ECC_CTRL_ECCCLEAR |
 894                                 GPMC_ECC_CTRL_ECCDISABLE);
 895                 break;
 896         default:
 897                 printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
 898                 break;
 899         }
 900
 901         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 902         val = (dev_width << 7) | (cs << 1) | (0x1);
 903         gpmc_write_reg(GPMC_ECC_CONFIG, val);
 904         return 0;
 905 }
 906 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
 907
 908 /**
 909  * gpmc_calculate_ecc - generate non-inverted ecc bytes
 910  * @cs: chip select number
 911  * @dat: data pointer over which ecc is computed
 912  * @ecc_code: ecc code buffer
 913  *
 914  * Using non-inverted ECC is considered ugly since writing a blank
 915  * page (padding) will clear the ECC bytes. This is not a problem as long
 916  * no one is trying to write data on the seemingly unused page. Reading
 917  * an erased page will produce an ECC mismatch between generated and read
 918  * ECC bytes that has to be dealt with separately.
 919  */
 920 int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
 921 {
 922         unsigned int val = 0x0;
 923
 924         if (gpmc_ecc_used != cs)
 925                 return -EINVAL;
 926
 927         /* read ecc result */
 928         val = gpmc_read_reg(GPMC_ECC1_RESULT);
 929         *ecc_code++ = val;          /* P128e, ..., P1e */
 930         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
 931         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 932         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 933
 934         gpmc_ecc_used = -EINVAL;
 935         return 0;
 936 }
 937 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);