2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <video/omapdss.h>
28 #include "omap_hwmod.h"
29 #include "omap_device.h"
40 #define DISPC_CONTROL 0x0040
41 #define DISPC_CONTROL2 0x0238
42 #define DISPC_CONTROL3 0x0848
43 #define DISPC_IRQSTATUS 0x0018
45 #define DSS_SYSCONFIG 0x10
46 #define DSS_SYSSTATUS 0x14
47 #define DSS_CONTROL 0x40
48 #define DSS_SDI_CONTROL 0x44
49 #define DSS_PLL_CONTROL 0x48
51 #define LCD_EN_MASK (0x1 << 0)
52 #define DIGIT_EN_MASK (0x1 << 1)
54 #define FRAMEDONE_IRQ_SHIFT 0
55 #define EVSYNC_EVEN_IRQ_SHIFT 2
56 #define EVSYNC_ODD_IRQ_SHIFT 3
57 #define FRAMEDONE2_IRQ_SHIFT 22
58 #define FRAMEDONE3_IRQ_SHIFT 30
59 #define FRAMEDONETV_IRQ_SHIFT 24
62 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
63 * reset before deciding that something has gone wrong
65 #define FRAMEDONE_IRQ_TIMEOUT 100
67 static struct platform_device omap_display_device = {
71 .platform_data = NULL,
75 struct omap_dss_hwmod_data {
81 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
82 { "dss_core", "omapdss_dss", -1 },
83 { "dss_dispc", "omapdss_dispc", -1 },
84 { "dss_rfbi", "omapdss_rfbi", -1 },
85 { "dss_venc", "omapdss_venc", -1 },
88 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
89 { "dss_core", "omapdss_dss", -1 },
90 { "dss_dispc", "omapdss_dispc", -1 },
91 { "dss_rfbi", "omapdss_rfbi", -1 },
92 { "dss_venc", "omapdss_venc", -1 },
93 { "dss_dsi1", "omapdss_dsi", 0 },
96 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
97 { "dss_core", "omapdss_dss", -1 },
98 { "dss_dispc", "omapdss_dispc", -1 },
99 { "dss_rfbi", "omapdss_rfbi", -1 },
100 { "dss_dsi1", "omapdss_dsi", 0 },
101 { "dss_dsi2", "omapdss_dsi", 1 },
102 { "dss_hdmi", "omapdss_hdmi", -1 },
105 static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
110 omap_mux_init_signal("hdmi_cec",
111 OMAP_PIN_INPUT_PULLUP);
112 omap_mux_init_signal("hdmi_ddc_scl",
113 OMAP_PIN_INPUT_PULLUP);
114 omap_mux_init_signal("hdmi_ddc_sda",
115 OMAP_PIN_INPUT_PULLUP);
118 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
119 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
120 * internal pull up resistor.
122 if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
123 control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
124 reg = omap4_ctrl_pad_readl(control_i2c_1);
125 reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
126 OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
127 omap4_ctrl_pad_writel(reg, control_i2c_1);
131 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
133 u32 enable_mask, enable_shift;
134 u32 pipd_mask, pipd_shift;
138 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
139 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
140 pipd_mask = OMAP4_DSI1_PIPD_MASK;
141 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
142 } else if (dsi_id == 1) {
143 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
144 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
145 pipd_mask = OMAP4_DSI2_PIPD_MASK;
146 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
151 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
156 reg |= (lanes << enable_shift) & enable_mask;
157 reg |= (lanes << pipd_shift) & pipd_mask;
159 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
164 int __init omap_hdmi_init(enum omap_hdmi_flags flags)
166 if (cpu_is_omap44xx())
167 omap4_hdmi_mux_pads(flags);
172 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
174 if (cpu_is_omap44xx())
175 return omap4_dsi_mux_pads(dsi_id, lane_mask);
180 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
182 if (cpu_is_omap44xx())
183 omap4_dsi_mux_pads(dsi_id, 0);
186 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
188 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
191 static struct platform_device *create_dss_pdev(const char *pdev_name,
192 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
193 struct platform_device *parent)
195 struct platform_device *pdev;
196 struct omap_device *od;
197 struct omap_hwmod *ohs[1];
198 struct omap_hwmod *oh;
201 oh = omap_hwmod_lookup(oh_name);
203 pr_err("Could not look up %s\n", oh_name);
208 pdev = platform_device_alloc(pdev_name, pdev_id);
210 pr_err("Could not create pdev for %s\n", pdev_name);
216 pdev->dev.parent = &parent->dev;
219 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
221 dev_set_name(&pdev->dev, "%s", pdev->name);
224 od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
226 pr_err("Could not alloc omap_device for %s\n", pdev_name);
231 r = platform_device_add_data(pdev, pdata, pdata_len);
233 pr_err("Could not set pdata for %s\n", pdev_name);
237 r = omap_device_register(pdev);
239 pr_err("Could not register omap_device for %s\n", pdev_name);
249 static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
250 int pdev_id, void *pdata, int pdata_len,
251 struct platform_device *parent)
253 struct platform_device *pdev;
256 pdev = platform_device_alloc(pdev_name, pdev_id);
258 pr_err("Could not create pdev for %s\n", pdev_name);
264 pdev->dev.parent = &parent->dev;
267 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
269 dev_set_name(&pdev->dev, "%s", pdev->name);
271 r = platform_device_add_data(pdev, pdata, pdata_len);
273 pr_err("Could not set pdata for %s\n", pdev_name);
277 r = platform_device_add(pdev);
279 pr_err("Could not register platform_device for %s\n", pdev_name);
289 static enum omapdss_version __init omap_display_get_version(void)
291 if (cpu_is_omap24xx())
292 return OMAPDSS_VER_OMAP24xx;
293 else if (cpu_is_omap3630())
294 return OMAPDSS_VER_OMAP3630;
295 else if (cpu_is_omap34xx()) {
296 if (soc_is_am35xx()) {
297 return OMAPDSS_VER_AM35xx;
299 if (omap_rev() < OMAP3430_REV_ES3_0)
300 return OMAPDSS_VER_OMAP34xx_ES1;
302 return OMAPDSS_VER_OMAP34xx_ES3;
304 } else if (omap_rev() == OMAP4430_REV_ES1_0)
305 return OMAPDSS_VER_OMAP4430_ES1;
306 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
307 omap_rev() == OMAP4430_REV_ES2_1 ||
308 omap_rev() == OMAP4430_REV_ES2_2)
309 return OMAPDSS_VER_OMAP4430_ES2;
310 else if (cpu_is_omap44xx())
311 return OMAPDSS_VER_OMAP4;
312 else if (soc_is_omap54xx())
313 return OMAPDSS_VER_OMAP5;
315 return OMAPDSS_VER_UNKNOWN;
318 int __init omap_display_init(struct omap_dss_board_info *board_data)
321 struct platform_device *pdev;
323 const struct omap_dss_hwmod_data *curr_dss_hwmod;
324 struct platform_device *dss_pdev;
325 enum omapdss_version ver;
327 /* create omapdss device */
329 ver = omap_display_get_version();
331 if (ver == OMAPDSS_VER_UNKNOWN) {
332 pr_err("DSS not supported on this SoC\n");
336 board_data->version = ver;
337 board_data->dsi_enable_pads = omap_dsi_enable_pads;
338 board_data->dsi_disable_pads = omap_dsi_disable_pads;
339 board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
340 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
342 omap_display_device.dev.platform_data = board_data;
344 r = platform_device_register(&omap_display_device);
346 pr_err("Unable to register omapdss device\n");
350 /* create devices for dss hwmods */
352 if (cpu_is_omap24xx()) {
353 curr_dss_hwmod = omap2_dss_hwmod_data;
354 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
355 } else if (cpu_is_omap34xx()) {
356 curr_dss_hwmod = omap3_dss_hwmod_data;
357 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
359 curr_dss_hwmod = omap4_dss_hwmod_data;
360 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
364 * First create the pdev for dss_core, which is used as a parent device
365 * by the other dss pdevs. Note: dss_core has to be the first item in
368 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
369 curr_dss_hwmod[0].id,
370 curr_dss_hwmod[0].oh_name,
371 board_data, sizeof(*board_data),
374 if (IS_ERR(dss_pdev)) {
375 pr_err("Could not build omap_device for %s\n",
376 curr_dss_hwmod[0].oh_name);
378 return PTR_ERR(dss_pdev);
381 for (i = 1; i < oh_count; i++) {
382 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
383 curr_dss_hwmod[i].id,
384 curr_dss_hwmod[i].oh_name,
385 board_data, sizeof(*board_data),
389 pr_err("Could not build omap_device for %s\n",
390 curr_dss_hwmod[i].oh_name);
392 return PTR_ERR(pdev);
396 /* Create devices for DPI and SDI */
398 pdev = create_simple_dss_pdev("omapdss_dpi", -1,
399 board_data, sizeof(*board_data), dss_pdev);
401 pr_err("Could not build platform_device for omapdss_dpi\n");
402 return PTR_ERR(pdev);
405 if (cpu_is_omap34xx()) {
406 pdev = create_simple_dss_pdev("omapdss_sdi", -1,
407 board_data, sizeof(*board_data), dss_pdev);
409 pr_err("Could not build platform_device for omapdss_sdi\n");
410 return PTR_ERR(pdev);
417 static void dispc_disable_outputs(void)
420 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
422 struct omap_dss_dispc_dev_attr *da;
423 struct omap_hwmod *oh;
425 oh = omap_hwmod_lookup("dss_dispc");
427 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
432 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
436 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
438 /* store value of LCDENABLE and DIGITENABLE bits */
439 v = omap_hwmod_read(oh, DISPC_CONTROL);
440 lcd_en = v & LCD_EN_MASK;
441 digit_en = v & DIGIT_EN_MASK;
443 /* store value of LCDENABLE for LCD2 */
444 if (da->manager_count > 2) {
445 v = omap_hwmod_read(oh, DISPC_CONTROL2);
446 lcd2_en = v & LCD_EN_MASK;
449 /* store value of LCDENABLE for LCD3 */
450 if (da->manager_count > 3) {
451 v = omap_hwmod_read(oh, DISPC_CONTROL3);
452 lcd3_en = v & LCD_EN_MASK;
455 if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
456 return; /* no managers currently enabled */
459 * If any manager was enabled, we need to disable it before
460 * DSS clocks are disabled or DISPC module is reset
463 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
466 if (da->has_framedonetv_irq) {
467 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
469 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
470 1 << EVSYNC_ODD_IRQ_SHIFT;
475 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
477 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
480 * clear any previous FRAMEDONE, FRAMEDONETV,
481 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
483 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
485 /* disable LCD and TV managers */
486 v = omap_hwmod_read(oh, DISPC_CONTROL);
487 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
488 omap_hwmod_write(v, oh, DISPC_CONTROL);
490 /* disable LCD2 manager */
491 if (da->manager_count > 2) {
492 v = omap_hwmod_read(oh, DISPC_CONTROL2);
494 omap_hwmod_write(v, oh, DISPC_CONTROL2);
497 /* disable LCD3 manager */
498 if (da->manager_count > 3) {
499 v = omap_hwmod_read(oh, DISPC_CONTROL3);
501 omap_hwmod_write(v, oh, DISPC_CONTROL3);
505 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
508 if (i > FRAMEDONE_IRQ_TIMEOUT) {
509 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
516 int omap_dss_reset(struct omap_hwmod *oh)
518 struct omap_hwmod_opt_clk *oc;
522 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
523 pr_err("dss_core: hwmod data doesn't contain reset data\n");
527 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
529 clk_prepare_enable(oc->_clk);
531 dispc_disable_outputs();
533 /* clear SDI registers */
534 if (cpu_is_omap3430()) {
535 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
536 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
540 * clear DSS_CONTROL register to switch DSS clock sources to
543 omap_hwmod_write(0x0, oh, DSS_CONTROL);
545 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
546 & SYSS_RESETDONE_MASK),
547 MAX_MODULE_SOFTRESET_WAIT, c);
549 if (c == MAX_MODULE_SOFTRESET_WAIT)
550 pr_warning("dss_core: waiting for reset to finish failed\n");
552 pr_debug("dss_core: softreset done\n");
554 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
556 clk_disable_unprepare(oc->_clk);
558 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;