2 * clkt_clksel.c - OMAP2/3/4 clksel clock functions
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 * clksel clocks are clocks that do not have a fixed parent, or that
17 * can divide their parent's rate, or possibly both at the same time, based
18 * on the contents of a hardware register bitfield.
20 * All of the various mux and divider settings can be encoded into
21 * struct clksel* data structures, and then these can be autogenerated
22 * from some hardware database for each new chip generation. This
23 * should avoid the need to write, review, and validate a lot of new
24 * clock code for each new chip, since it can be exported from the SoC
25 * design flow. This is now done on OMAP4.
27 * The fusion of mux and divider clocks is a software creation. In
28 * hardware reality, the multiplexer (parent selection) and the
29 * divider exist separately. XXX At some point these clksel clocks
30 * should be split into "divider" clocks and "mux" clocks to better
33 * (The name "clksel" comes from the name of the corresponding
34 * register field in the OMAP2/3 family of SoCs.)
36 * XXX Currently these clocks are only used in the OMAP2/3/4 code, but
37 * many of the OMAP1 clocks should be convertible to use this
42 #include <linux/kernel.h>
43 #include <linux/errno.h>
44 #include <linux/clk.h>
46 #include <linux/bug.h>
48 #include <plat/clock.h>
52 /* Private functions */
55 * _get_clksel_by_parent() - return clksel struct for a given clk & parent
56 * @clk: OMAP struct clk ptr to inspect
57 * @src_clk: OMAP struct clk ptr of the parent clk to search for
59 * Scan the struct clksel array associated with the clock to find
60 * the element associated with the supplied parent clock address.
61 * Returns a pointer to the struct clksel on success or NULL on error.
63 static const struct clksel *_get_clksel_by_parent(struct clk *clk,
66 const struct clksel *clks;
68 for (clks = clk->clksel; clks->parent; clks++)
69 if (clks->parent == src_clk)
70 break; /* Found the requested parent */
73 /* This indicates a data problem */
74 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
75 __clk_get_name(clk), __clk_get_name(src_clk));
83 * _get_div_and_fieldval() - find the new clksel divisor and field value to use
84 * @src_clk: planned new parent struct clk *
85 * @clk: struct clk * that is being reparented
86 * @field_val: pointer to a u32 to contain the register data for the divisor
88 * Given an intended new parent struct clk * @src_clk, and the struct
89 * clk * @clk to the clock that is being reparented, find the
90 * appropriate rate divisor for the new clock (returned as the return
91 * value), and the corresponding register bitfield data to program to
92 * reach that divisor (returned in the u32 pointed to by @field_val).
93 * Returns 0 on error, or returns the newly-selected divisor upon
94 * success (in this latter case, the corresponding register bitfield
95 * value is passed back in the variable pointed to by @field_val)
97 static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
100 const struct clksel *clks;
101 const struct clksel_rate *clkr, *max_clkr = NULL;
104 clks = _get_clksel_by_parent(clk, src_clk);
109 * Find the highest divisor (e.g., the one resulting in the
110 * lowest rate) to use as the default. This should avoid
111 * clock rates that are too high for the device. XXX A better
112 * solution here would be to try to determine if there is a
113 * divisor matching the original clock rate before the parent
114 * switch, and if it cannot be found, to fall back to the
117 for (clkr = clks->rates; clkr->div; clkr++) {
118 if (!(clkr->flags & cpu_mask))
121 if (clkr->div > max_div) {
128 /* This indicates an error in the clksel data */
129 WARN(1, "clock: %s: could not find divisor for parent %s\n",
131 __clk_get_name(__clk_get_parent(src_clk)));
135 *field_val = max_clkr->val;
141 * _write_clksel_reg() - program a clock's clksel register in hardware
142 * @clk: struct clk * to program
143 * @v: clksel bitfield value to program (with LSB at bit 0)
145 * Shift the clksel register bitfield value @v to its appropriate
146 * location in the clksel register and write it in. This function
147 * will ensure that the write to the clksel_reg reaches its
148 * destination before returning -- important since PRM and CM register
149 * accesses can be quite slow compared to ARM cycles -- but does not
150 * take into account any time the hardware might take to switch the
153 static void _write_clksel_reg(struct clk *clk, u32 field_val)
157 v = __raw_readl(clk->clksel_reg);
158 v &= ~clk->clksel_mask;
159 v |= field_val << __ffs(clk->clksel_mask);
160 __raw_writel(v, clk->clksel_reg);
162 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
166 * _clksel_to_divisor() - turn clksel field value into integer divider
167 * @clk: OMAP struct clk to use
168 * @field_val: register field value to find
170 * Given a struct clk of a rate-selectable clksel clock, and a register field
171 * value to search for, find the corresponding clock divisor. The register
172 * field value should be pre-masked and shifted down so the LSB is at bit 0
173 * before calling. Returns 0 on error or returns the actual integer divisor
176 static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
178 const struct clksel *clks;
179 const struct clksel_rate *clkr;
182 parent = __clk_get_parent(clk);
183 clks = _get_clksel_by_parent(clk, parent);
187 for (clkr = clks->rates; clkr->div; clkr++) {
188 if (!(clkr->flags & cpu_mask))
191 if (clkr->val == field_val)
196 /* This indicates a data error */
197 WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
198 __clk_get_name(clk), field_val, __clk_get_name(parent));
206 * _divisor_to_clksel() - turn clksel integer divisor into a field value
207 * @clk: OMAP struct clk to use
208 * @div: integer divisor to search for
210 * Given a struct clk of a rate-selectable clksel clock, and a clock
211 * divisor, find the corresponding register field value. Returns the
212 * register field value _before_ left-shifting (i.e., LSB is at bit
213 * 0); or returns 0xFFFFFFFF (~0) upon error.
215 static u32 _divisor_to_clksel(struct clk *clk, u32 div)
217 const struct clksel *clks;
218 const struct clksel_rate *clkr;
221 /* should never happen */
224 parent = __clk_get_parent(clk);
225 clks = _get_clksel_by_parent(clk, parent);
229 for (clkr = clks->rates; clkr->div; clkr++) {
230 if (!(clkr->flags & cpu_mask))
233 if (clkr->div == div)
238 pr_err("clock: %s: could not find divisor %d for parent %s\n",
239 __clk_get_name(clk), div, __clk_get_name(parent));
247 * _read_divisor() - get current divisor applied to parent clock (from hdwr)
248 * @clk: OMAP struct clk to use.
250 * Read the current divisor register value for @clk that is programmed
251 * into the hardware, convert it into the actual divisor value, and
252 * return it; or return 0 on error.
254 static u32 _read_divisor(struct clk *clk)
258 if (!clk->clksel || !clk->clksel_mask)
261 v = __raw_readl(clk->clksel_reg);
262 v &= clk->clksel_mask;
263 v >>= __ffs(clk->clksel_mask);
265 return _clksel_to_divisor(clk, v);
268 /* Public functions */
271 * omap2_clksel_round_rate_div() - find divisor for the given clock and rate
272 * @clk: OMAP struct clk to use
273 * @target_rate: desired clock rate
274 * @new_div: ptr to where we should store the divisor
276 * Finds 'best' divider value in an array based on the source and target
277 * rates. The divider array must be sorted with smallest divider first.
278 * This function is also used by the DPLL3 M2 divider code.
280 * Returns the rounded clock rate or returns 0xffffffff on error.
282 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
285 unsigned long test_rate;
286 const struct clksel *clks;
287 const struct clksel_rate *clkr;
290 unsigned long parent_rate;
291 const char *clk_name;
293 parent = __clk_get_parent(clk);
294 parent_rate = __clk_get_rate(parent);
295 clk_name = __clk_get_name(clk);
297 if (!clk->clksel || !clk->clksel_mask)
300 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
301 clk_name, target_rate);
305 clks = _get_clksel_by_parent(clk, parent);
309 for (clkr = clks->rates; clkr->div; clkr++) {
310 if (!(clkr->flags & cpu_mask))
314 if (clkr->div <= last_div)
315 pr_err("clock: %s: clksel_rate table not sorted\n",
318 last_div = clkr->div;
320 test_rate = parent_rate / clkr->div;
322 if (test_rate <= target_rate)
323 break; /* found it */
327 pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
328 clk_name, target_rate, __clk_get_name(parent));
332 *new_div = clkr->div;
334 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
335 (parent_rate / clkr->div));
337 return parent_rate / clkr->div;
341 * Clocktype interface functions to the OMAP clock code
342 * (i.e., those used in struct clk field function pointers, etc.)
346 * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
347 * @clk: OMAP clock struct ptr to use
349 * Given a pointer @clk to a source-selectable struct clk, read the
350 * hardware register and determine what its parent is currently set
351 * to. Update @clk's .parent field with the appropriate clk ptr. No
354 void omap2_init_clksel_parent(struct clk *clk)
356 const struct clksel *clks;
357 const struct clksel_rate *clkr;
360 const char *clk_name;
362 if (!clk->clksel || !clk->clksel_mask)
365 parent = __clk_get_parent(clk);
366 clk_name = __clk_get_name(clk);
368 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
369 r >>= __ffs(clk->clksel_mask);
371 for (clks = clk->clksel; clks->parent && !found; clks++) {
372 for (clkr = clks->rates; clkr->div && !found; clkr++) {
373 if (!(clkr->flags & cpu_mask))
376 if (clkr->val == r) {
377 if (parent != clks->parent) {
378 pr_debug("clock: %s: inited parent to %s (was %s)\n",
380 __clk_get_name(clks->parent),
382 __clk_get_name(parent) :
384 clk_reparent(clk, clks->parent);
391 /* This indicates a data error */
392 WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
399 * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
402 * This function is intended to be called only by the clock framework.
403 * Each clksel clock should have its struct clk .recalc field set to this
404 * function. Returns the clock's current rate, based on its parent's rate
405 * and its current divisor setting in the hardware.
407 unsigned long omap2_clksel_recalc(struct clk *clk)
413 div = _read_divisor(clk);
415 return __clk_get_rate(clk);
417 parent = __clk_get_parent(clk);
418 rate = __clk_get_rate(parent) / div;
420 pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
421 __clk_get_name(clk), rate, div);
427 * omap2_clksel_round_rate() - find rounded rate for the given clock and rate
428 * @clk: OMAP struct clk to use
429 * @target_rate: desired clock rate
431 * This function is intended to be called only by the clock framework.
432 * Finds best target rate based on the source clock and possible dividers.
433 * rates. The divider array must be sorted with smallest divider first.
435 * Returns the rounded clock rate or returns 0xffffffff on error.
437 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
441 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
445 * omap2_clksel_set_rate() - program clock rate in hardware
446 * @clk: struct clk * to program rate
447 * @rate: target rate to program
449 * This function is intended to be called only by the clock framework.
450 * Program @clk's rate to @rate in the hardware. The clock can be
451 * either enabled or disabled when this happens, although if the clock
452 * is enabled, some downstream devices may glitch or behave
453 * unpredictably when the clock rate is changed - this depends on the
454 * hardware. This function does not currently check the usecount of
455 * the clock, so if multiple drivers are using the clock, and the rate
456 * is changed, they will all be affected without any notification.
457 * Returns -EINVAL upon error, or 0 upon success.
459 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
461 u32 field_val, validrate, new_div = 0;
463 if (!clk->clksel || !clk->clksel_mask)
466 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
467 if (validrate != rate)
470 field_val = _divisor_to_clksel(clk, new_div);
474 _write_clksel_reg(clk, field_val);
476 clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
478 pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
479 __clk_get_rate(clk));
485 * Clksel parent setting function - not passed in struct clk function
486 * pointer - instead, the OMAP clock code currently assumes that any
487 * parent-setting clock is a clksel clock, and calls
488 * omap2_clksel_set_parent() by default
492 * omap2_clksel_set_parent() - change a clock's parent clock
493 * @clk: struct clk * of the child clock
494 * @new_parent: struct clk * of the new parent clock
496 * This function is intended to be called only by the clock framework.
497 * Change the parent clock of clock @clk to @new_parent. This is
498 * intended to be used while @clk is disabled. This function does not
499 * currently check the usecount of the clock, so if multiple drivers
500 * are using the clock, and the parent is changed, they will all be
501 * affected without any notification. Returns -EINVAL upon error, or
504 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
509 if (!clk->clksel || !clk->clksel_mask)
512 parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
516 _write_clksel_reg(clk, field_val);
518 clk_reparent(clk, new_parent);
520 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
521 clk->rate = __clk_get_rate(new_parent);
524 __clk_get_rate(clk) /= parent_div;
526 pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
528 __clk_get_name(__clk_get_parent(clk)),
529 __clk_get_rate(clk));