Pileus Git - ~andy/linux/blob - arch/arm/mach-omap1/clock_data.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock_data.c
   3  *
   4  *  Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * To do:
  13  * - Clocks that are only available on some chips should be marked with the
  14  *   chips that they are present on.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/io.h>
  19 #include <linux/clk.h>
  20 #include <linux/cpufreq.h>
  21 #include <linux/delay.h>
  22
  23 #include <asm/mach-types.h>  /* for machine_is_* */
  24
  25 #include <plat/clock.h>
  26 #include <plat/cpu.h>
  27 #include <plat/clkdev_omap.h>
  28 #include <plat/board.h>
  29 #include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
  30
  31 #include <mach/hardware.h>
  32 #include <mach/usb.h>   /* for OTG_BASE */
  33
  34 #include "iomap.h"
  35 #include "clock.h"
  36
  37 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
  38 #define IDL_CLKOUT_ARM_SHIFT                    12
  39 #define IDLTIM_ARM_SHIFT                        9
  40 #define IDLAPI_ARM_SHIFT                        8
  41 #define IDLIF_ARM_SHIFT                         6
  42 #define IDLLB_ARM_SHIFT                         4       /* undocumented? */
  43 #define OMAP1510_IDLLCD_ARM_SHIFT               3       /* undocumented? */
  44 #define IDLPER_ARM_SHIFT                        2
  45 #define IDLXORP_ARM_SHIFT                       1
  46 #define IDLWDT_ARM_SHIFT                        0
  47
  48 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
  49 #define CONF_MOD_UART3_CLK_MODE_R               31
  50 #define CONF_MOD_UART2_CLK_MODE_R               30
  51 #define CONF_MOD_UART1_CLK_MODE_R               29
  52 #define CONF_MOD_MMC_SD_CLK_REQ_R               23
  53 #define CONF_MOD_MCBSP3_AUXON                   20
  54
  55 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
  56 #define CONF_MOD_SOSSI_CLK_EN_R                 16
  57
  58 /* Some OTG_SYSCON_2-specific bit fields */
  59 #define OTG_SYSCON_2_UHOST_EN_SHIFT             8
  60
  61 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
  62 #define SOFT_MMC2_DPLL_REQ_SHIFT        13
  63 #define SOFT_MMC_DPLL_REQ_SHIFT         12
  64 #define SOFT_UART3_DPLL_REQ_SHIFT       11
  65 #define SOFT_UART2_DPLL_REQ_SHIFT       10
  66 #define SOFT_UART1_DPLL_REQ_SHIFT       9
  67 #define SOFT_USB_OTG_DPLL_REQ_SHIFT     8
  68 #define SOFT_CAM_DPLL_REQ_SHIFT         7
  69 #define SOFT_COM_MCKO_REQ_SHIFT         6
  70 #define SOFT_PERIPH_REQ_SHIFT           5       /* sys_ck gate for UART2 ? */
  71 #define USB_REQ_EN_SHIFT                4
  72 #define SOFT_USB_REQ_SHIFT              3       /* sys_ck gate for USB host? */
  73 #define SOFT_SDW_REQ_SHIFT              2       /* sys_ck gate for Bluetooth? */
  74 #define SOFT_COM_REQ_SHIFT              1       /* sys_ck gate for com proc? */
  75 #define SOFT_DPLL_REQ_SHIFT             0
  76
  77 /*
  78  * Omap1 clocks
  79  */
  80
  81 static struct clk ck_ref = {
  82         .name           = "ck_ref",
  83         .ops            = &clkops_null,
  84         .rate           = 12000000,
  85 };
  86
  87 static struct clk ck_dpll1 = {
  88         .name           = "ck_dpll1",
  89         .ops            = &clkops_null,
  90         .parent         = &ck_ref,
  91 };
  92
  93 /*
  94  * FIXME: This clock seems to be necessary but no-one has asked for its
  95  * activation.  [ FIX: SoSSI, SSR ]
  96  */
  97 static struct arm_idlect1_clk ck_dpll1out = {
  98         .clk = {
  99                 .name           = "ck_dpll1out",
 100                 .ops            = &clkops_generic,
 101                 .parent         = &ck_dpll1,
 102                 .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
 103                                   ENABLE_ON_INIT,
 104                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 105                 .enable_bit     = EN_CKOUT_ARM,
 106                 .recalc         = &followparent_recalc,
 107         },
 108         .idlect_shift   = IDL_CLKOUT_ARM_SHIFT,
 109 };
 110
 111 static struct clk sossi_ck = {
 112         .name           = "ck_sossi",
 113         .ops            = &clkops_generic,
 114         .parent         = &ck_dpll1out.clk,
 115         .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
 116         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
 117         .enable_bit     = CONF_MOD_SOSSI_CLK_EN_R,
 118         .recalc         = &omap1_sossi_recalc,
 119         .set_rate       = &omap1_set_sossi_rate,
 120 };
 121
 122 static struct clk arm_ck = {
 123         .name           = "arm_ck",
 124         .ops            = &clkops_null,
 125         .parent         = &ck_dpll1,
 126         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 127         .recalc         = &omap1_ckctl_recalc,
 128         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 129         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 130 };
 131
 132 static struct arm_idlect1_clk armper_ck = {
 133         .clk = {
 134                 .name           = "armper_ck",
 135                 .ops            = &clkops_generic,
 136                 .parent         = &ck_dpll1,
 137                 .flags          = CLOCK_IDLE_CONTROL,
 138                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 139                 .enable_bit     = EN_PERCK,
 140                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 141                 .recalc         = &omap1_ckctl_recalc,
 142                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 143                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 144         },
 145         .idlect_shift   = IDLPER_ARM_SHIFT,
 146 };
 147
 148 /*
 149  * FIXME: This clock seems to be necessary but no-one has asked for its
 150  * activation.  [ GPIO code for 1510 ]
 151  */
 152 static struct clk arm_gpio_ck = {
 153         .name           = "ick",
 154         .ops            = &clkops_generic,
 155         .parent         = &ck_dpll1,
 156         .flags          = ENABLE_ON_INIT,
 157         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 158         .enable_bit     = EN_GPIOCK,
 159         .recalc         = &followparent_recalc,
 160 };
 161
 162 static struct arm_idlect1_clk armxor_ck = {
 163         .clk = {
 164                 .name           = "armxor_ck",
 165                 .ops            = &clkops_generic,
 166                 .parent         = &ck_ref,
 167                 .flags          = CLOCK_IDLE_CONTROL,
 168                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 169                 .enable_bit     = EN_XORPCK,
 170                 .recalc         = &followparent_recalc,
 171         },
 172         .idlect_shift   = IDLXORP_ARM_SHIFT,
 173 };
 174
 175 static struct arm_idlect1_clk armtim_ck = {
 176         .clk = {
 177                 .name           = "armtim_ck",
 178                 .ops            = &clkops_generic,
 179                 .parent         = &ck_ref,
 180                 .flags          = CLOCK_IDLE_CONTROL,
 181                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 182                 .enable_bit     = EN_TIMCK,
 183                 .recalc         = &followparent_recalc,
 184         },
 185         .idlect_shift   = IDLTIM_ARM_SHIFT,
 186 };
 187
 188 static struct arm_idlect1_clk armwdt_ck = {
 189         .clk = {
 190                 .name           = "armwdt_ck",
 191                 .ops            = &clkops_generic,
 192                 .parent         = &ck_ref,
 193                 .flags          = CLOCK_IDLE_CONTROL,
 194                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 195                 .enable_bit     = EN_WDTCK,
 196                 .fixed_div      = 14,
 197                 .recalc         = &omap_fixed_divisor_recalc,
 198         },
 199         .idlect_shift   = IDLWDT_ARM_SHIFT,
 200 };
 201
 202 static struct clk arminth_ck16xx = {
 203         .name           = "arminth_ck",
 204         .ops            = &clkops_null,
 205         .parent         = &arm_ck,
 206         .recalc         = &followparent_recalc,
 207         /* Note: On 16xx the frequency can be divided by 2 by programming
 208          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 209          *
 210          * 1510 version is in TC clocks.
 211          */
 212 };
 213
 214 static struct clk dsp_ck = {
 215         .name           = "dsp_ck",
 216         .ops            = &clkops_generic,
 217         .parent         = &ck_dpll1,
 218         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 219         .enable_bit     = EN_DSPCK,
 220         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 221         .recalc         = &omap1_ckctl_recalc,
 222         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 223         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 224 };
 225
 226 static struct clk dspmmu_ck = {
 227         .name           = "dspmmu_ck",
 228         .ops            = &clkops_null,
 229         .parent         = &ck_dpll1,
 230         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 231         .recalc         = &omap1_ckctl_recalc,
 232         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 233         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 234 };
 235
 236 static struct clk dspper_ck = {
 237         .name           = "dspper_ck",
 238         .ops            = &clkops_dspck,
 239         .parent         = &ck_dpll1,
 240         .enable_reg     = DSP_IDLECT2,
 241         .enable_bit     = EN_PERCK,
 242         .rate_offset    = CKCTL_PERDIV_OFFSET,
 243         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 244         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 245         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 246 };
 247
 248 static struct clk dspxor_ck = {
 249         .name           = "dspxor_ck",
 250         .ops            = &clkops_dspck,
 251         .parent         = &ck_ref,
 252         .enable_reg     = DSP_IDLECT2,
 253         .enable_bit     = EN_XORPCK,
 254         .recalc         = &followparent_recalc,
 255 };
 256
 257 static struct clk dsptim_ck = {
 258         .name           = "dsptim_ck",
 259         .ops            = &clkops_dspck,
 260         .parent         = &ck_ref,
 261         .enable_reg     = DSP_IDLECT2,
 262         .enable_bit     = EN_DSPTIMCK,
 263         .recalc         = &followparent_recalc,
 264 };
 265
 266 static struct arm_idlect1_clk tc_ck = {
 267         .clk = {
 268                 .name           = "tc_ck",
 269                 .ops            = &clkops_null,
 270                 .parent         = &ck_dpll1,
 271                 .flags          = CLOCK_IDLE_CONTROL,
 272                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 273                 .recalc         = &omap1_ckctl_recalc,
 274                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 275                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 276         },
 277         .idlect_shift   = IDLIF_ARM_SHIFT,
 278 };
 279
 280 static struct clk arminth_ck1510 = {
 281         .name           = "arminth_ck",
 282         .ops            = &clkops_null,
 283         .parent         = &tc_ck.clk,
 284         .recalc         = &followparent_recalc,
 285         /* Note: On 1510 the frequency follows TC_CK
 286          *
 287          * 16xx version is in MPU clocks.
 288          */
 289 };
 290
 291 static struct clk tipb_ck = {
 292         /* No-idle controlled by "tc_ck" */
 293         .name           = "tipb_ck",
 294         .ops            = &clkops_null,
 295         .parent         = &tc_ck.clk,
 296         .recalc         = &followparent_recalc,
 297 };
 298
 299 static struct clk l3_ocpi_ck = {
 300         /* No-idle controlled by "tc_ck" */
 301         .name           = "l3_ocpi_ck",
 302         .ops            = &clkops_generic,
 303         .parent         = &tc_ck.clk,
 304         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 305         .enable_bit     = EN_OCPI_CK,
 306         .recalc         = &followparent_recalc,
 307 };
 308
 309 static struct clk tc1_ck = {
 310         .name           = "tc1_ck",
 311         .ops            = &clkops_generic,
 312         .parent         = &tc_ck.clk,
 313         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 314         .enable_bit     = EN_TC1_CK,
 315         .recalc         = &followparent_recalc,
 316 };
 317
 318 /*
 319  * FIXME: This clock seems to be necessary but no-one has asked for its
 320  * activation.  [ pm.c (SRAM), CCP, Camera ]
 321  */
 322 static struct clk tc2_ck = {
 323         .name           = "tc2_ck",
 324         .ops            = &clkops_generic,
 325         .parent         = &tc_ck.clk,
 326         .flags          = ENABLE_ON_INIT,
 327         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 328         .enable_bit     = EN_TC2_CK,
 329         .recalc         = &followparent_recalc,
 330 };
 331
 332 static struct clk dma_ck = {
 333         /* No-idle controlled by "tc_ck" */
 334         .name           = "dma_ck",
 335         .ops            = &clkops_null,
 336         .parent         = &tc_ck.clk,
 337         .recalc         = &followparent_recalc,
 338 };
 339
 340 static struct clk dma_lcdfree_ck = {
 341         .name           = "dma_lcdfree_ck",
 342         .ops            = &clkops_null,
 343         .parent         = &tc_ck.clk,
 344         .recalc         = &followparent_recalc,
 345 };
 346
 347 static struct arm_idlect1_clk api_ck = {
 348         .clk = {
 349                 .name           = "api_ck",
 350                 .ops            = &clkops_generic,
 351                 .parent         = &tc_ck.clk,
 352                 .flags          = CLOCK_IDLE_CONTROL,
 353                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 354                 .enable_bit     = EN_APICK,
 355                 .recalc         = &followparent_recalc,
 356         },
 357         .idlect_shift   = IDLAPI_ARM_SHIFT,
 358 };
 359
 360 static struct arm_idlect1_clk lb_ck = {
 361         .clk = {
 362                 .name           = "lb_ck",
 363                 .ops            = &clkops_generic,
 364                 .parent         = &tc_ck.clk,
 365                 .flags          = CLOCK_IDLE_CONTROL,
 366                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 367                 .enable_bit     = EN_LBCK,
 368                 .recalc         = &followparent_recalc,
 369         },
 370         .idlect_shift   = IDLLB_ARM_SHIFT,
 371 };
 372
 373 static struct clk rhea1_ck = {
 374         .name           = "rhea1_ck",
 375         .ops            = &clkops_null,
 376         .parent         = &tc_ck.clk,
 377         .recalc         = &followparent_recalc,
 378 };
 379
 380 static struct clk rhea2_ck = {
 381         .name           = "rhea2_ck",
 382         .ops            = &clkops_null,
 383         .parent         = &tc_ck.clk,
 384         .recalc         = &followparent_recalc,
 385 };
 386
 387 static struct clk lcd_ck_16xx = {
 388         .name           = "lcd_ck",
 389         .ops            = &clkops_generic,
 390         .parent         = &ck_dpll1,
 391         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 392         .enable_bit     = EN_LCDCK,
 393         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 394         .recalc         = &omap1_ckctl_recalc,
 395         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 396         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 397 };
 398
 399 static struct arm_idlect1_clk lcd_ck_1510 = {
 400         .clk = {
 401                 .name           = "lcd_ck",
 402                 .ops            = &clkops_generic,
 403                 .parent         = &ck_dpll1,
 404                 .flags          = CLOCK_IDLE_CONTROL,
 405                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 406                 .enable_bit     = EN_LCDCK,
 407                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 408                 .recalc         = &omap1_ckctl_recalc,
 409                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 410                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 411         },
 412         .idlect_shift   = OMAP1510_IDLLCD_ARM_SHIFT,
 413 };
 414
 415 /*
 416  * XXX The enable_bit here is misused - it simply switches between 12MHz
 417  * and 48MHz.  Reimplement with clksel.
 418  *
 419  * XXX does this need SYSC register handling?
 420  */
 421 static struct clk uart1_1510 = {
 422         .name           = "uart1_ck",
 423         .ops            = &clkops_null,
 424         /* Direct from ULPD, no real parent */
 425         .parent         = &armper_ck.clk,
 426         .rate           = 12000000,
 427         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 428         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 429         .enable_bit     = CONF_MOD_UART1_CLK_MODE_R,
 430         .set_rate       = &omap1_set_uart_rate,
 431         .recalc         = &omap1_uart_recalc,
 432 };
 433
 434 /*
 435  * XXX The enable_bit here is misused - it simply switches between 12MHz
 436  * and 48MHz.  Reimplement with clksel.
 437  *
 438  * XXX SYSC register handling does not belong in the clock framework
 439  */
 440 static struct uart_clk uart1_16xx = {
 441         .clk    = {
 442                 .name           = "uart1_ck",
 443                 .ops            = &clkops_uart_16xx,
 444                 /* Direct from ULPD, no real parent */
 445                 .parent         = &armper_ck.clk,
 446                 .rate           = 48000000,
 447                 .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 448                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 449                 .enable_bit     = CONF_MOD_UART1_CLK_MODE_R,
 450         },
 451         .sysc_addr      = 0xfffb0054,
 452 };
 453
 454 /*
 455  * XXX The enable_bit here is misused - it simply switches between 12MHz
 456  * and 48MHz.  Reimplement with clksel.
 457  *
 458  * XXX does this need SYSC register handling?
 459  */
 460 static struct clk uart2_ck = {
 461         .name           = "uart2_ck",
 462         .ops            = &clkops_null,
 463         /* Direct from ULPD, no real parent */
 464         .parent         = &armper_ck.clk,
 465         .rate           = 12000000,
 466         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 467         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 468         .enable_bit     = CONF_MOD_UART2_CLK_MODE_R,
 469         .set_rate       = &omap1_set_uart_rate,
 470         .recalc         = &omap1_uart_recalc,
 471 };
 472
 473 /*
 474  * XXX The enable_bit here is misused - it simply switches between 12MHz
 475  * and 48MHz.  Reimplement with clksel.
 476  *
 477  * XXX does this need SYSC register handling?
 478  */
 479 static struct clk uart3_1510 = {
 480         .name           = "uart3_ck",
 481         .ops            = &clkops_null,
 482         /* Direct from ULPD, no real parent */
 483         .parent         = &armper_ck.clk,
 484         .rate           = 12000000,
 485         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 486         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 487         .enable_bit     = CONF_MOD_UART3_CLK_MODE_R,
 488         .set_rate       = &omap1_set_uart_rate,
 489         .recalc         = &omap1_uart_recalc,
 490 };
 491
 492 /*
 493  * XXX The enable_bit here is misused - it simply switches between 12MHz
 494  * and 48MHz.  Reimplement with clksel.
 495  *
 496  * XXX SYSC register handling does not belong in the clock framework
 497  */
 498 static struct uart_clk uart3_16xx = {
 499         .clk    = {
 500                 .name           = "uart3_ck",
 501                 .ops            = &clkops_uart_16xx,
 502                 /* Direct from ULPD, no real parent */
 503                 .parent         = &armper_ck.clk,
 504                 .rate           = 48000000,
 505                 .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 506                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 507                 .enable_bit     = CONF_MOD_UART3_CLK_MODE_R,
 508         },
 509         .sysc_addr      = 0xfffb9854,
 510 };
 511
 512 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 513         .name           = "usb_clko",
 514         .ops            = &clkops_generic,
 515         /* Direct from ULPD, no parent */
 516         .rate           = 6000000,
 517         .flags          = ENABLE_REG_32BIT,
 518         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 519         .enable_bit     = USB_MCLK_EN_BIT,
 520 };
 521
 522 static struct clk usb_hhc_ck1510 = {
 523         .name           = "usb_hhc_ck",
 524         .ops            = &clkops_generic,
 525         /* Direct from ULPD, no parent */
 526         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 527         .flags          = ENABLE_REG_32BIT,
 528         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 529         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 530 };
 531
 532 static struct clk usb_hhc_ck16xx = {
 533         .name           = "usb_hhc_ck",
 534         .ops            = &clkops_generic,
 535         /* Direct from ULPD, no parent */
 536         .rate           = 48000000,
 537         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 538         .flags          = ENABLE_REG_32BIT,
 539         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 540         .enable_bit     = OTG_SYSCON_2_UHOST_EN_SHIFT
 541 };
 542
 543 static struct clk usb_dc_ck = {
 544         .name           = "usb_dc_ck",
 545         .ops            = &clkops_generic,
 546         /* Direct from ULPD, no parent */
 547         .rate           = 48000000,
 548         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 549         .enable_bit     = USB_REQ_EN_SHIFT,
 550 };
 551
 552 static struct clk usb_dc_ck7xx = {
 553         .name           = "usb_dc_ck",
 554         .ops            = &clkops_generic,
 555         /* Direct from ULPD, no parent */
 556         .rate           = 48000000,
 557         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 558         .enable_bit     = SOFT_USB_OTG_DPLL_REQ_SHIFT,
 559 };
 560
 561 static struct clk uart1_7xx = {
 562         .name           = "uart1_ck",
 563         .ops            = &clkops_generic,
 564         /* Direct from ULPD, no parent */
 565         .rate           = 12000000,
 566         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 567         .enable_bit     = 9,
 568 };
 569
 570 static struct clk uart2_7xx = {
 571         .name           = "uart2_ck",
 572         .ops            = &clkops_generic,
 573         /* Direct from ULPD, no parent */
 574         .rate           = 12000000,
 575         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 576         .enable_bit     = 11,
 577 };
 578
 579 static struct clk mclk_1510 = {
 580         .name           = "mclk",
 581         .ops            = &clkops_generic,
 582         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 583         .rate           = 12000000,
 584         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 585         .enable_bit     = SOFT_COM_MCKO_REQ_SHIFT,
 586 };
 587
 588 static struct clk mclk_16xx = {
 589         .name           = "mclk",
 590         .ops            = &clkops_generic,
 591         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 592         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 593         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 594         .set_rate       = &omap1_set_ext_clk_rate,
 595         .round_rate     = &omap1_round_ext_clk_rate,
 596         .init           = &omap1_init_ext_clk,
 597 };
 598
 599 static struct clk bclk_1510 = {
 600         .name           = "bclk",
 601         .ops            = &clkops_generic,
 602         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 603         .rate           = 12000000,
 604 };
 605
 606 static struct clk bclk_16xx = {
 607         .name           = "bclk",
 608         .ops            = &clkops_generic,
 609         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 610         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 611         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 612         .set_rate       = &omap1_set_ext_clk_rate,
 613         .round_rate     = &omap1_round_ext_clk_rate,
 614         .init           = &omap1_init_ext_clk,
 615 };
 616
 617 static struct clk mmc1_ck = {
 618         .name           = "mmc1_ck",
 619         .ops            = &clkops_generic,
 620         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 621         .parent         = &armper_ck.clk,
 622         .rate           = 48000000,
 623         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 624         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 625         .enable_bit     = CONF_MOD_MMC_SD_CLK_REQ_R,
 626 };
 627
 628 /*
 629  * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
 630  * CONF_MOD_MCBSP3_AUXON ??
 631  */
 632 static struct clk mmc2_ck = {
 633         .name           = "mmc2_ck",
 634         .ops            = &clkops_generic,
 635         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 636         .parent         = &armper_ck.clk,
 637         .rate           = 48000000,
 638         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 639         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 640         .enable_bit     = 20,
 641 };
 642
 643 static struct clk mmc3_ck = {
 644         .name           = "mmc3_ck",
 645         .ops            = &clkops_generic,
 646         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 647         .parent         = &armper_ck.clk,
 648         .rate           = 48000000,
 649         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 650         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 651         .enable_bit     = SOFT_MMC_DPLL_REQ_SHIFT,
 652 };
 653
 654 static struct clk virtual_ck_mpu = {
 655         .name           = "mpu",
 656         .ops            = &clkops_null,
 657         .parent         = &arm_ck, /* Is smarter alias for */
 658         .recalc         = &followparent_recalc,
 659         .set_rate       = &omap1_select_table_rate,
 660         .round_rate     = &omap1_round_to_table_rate,
 661 };
 662
 663 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 664 remains active during MPU idle whenever this is enabled */
 665 static struct clk i2c_fck = {
 666         .name           = "i2c_fck",
 667         .ops            = &clkops_null,
 668         .flags          = CLOCK_NO_IDLE_PARENT,
 669         .parent         = &armxor_ck.clk,
 670         .recalc         = &followparent_recalc,
 671 };
 672
 673 static struct clk i2c_ick = {
 674         .name           = "i2c_ick",
 675         .ops            = &clkops_null,
 676         .flags          = CLOCK_NO_IDLE_PARENT,
 677         .parent         = &armper_ck.clk,
 678         .recalc         = &followparent_recalc,
 679 };
 680
 681 /*
 682  * clkdev integration
 683  */
 684
 685 static struct omap_clk omap_clks[] = {
 686         /* non-ULPD clocks */
 687         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
 688         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310 | CK_7XX),
 689         /* CK_GEN1 clocks */
 690         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
 691         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
 692         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
 693         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 694         CLK("omap_gpio.0", "ick",       &arm_gpio_ck,   CK_1510 | CK_310),
 695         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 696         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
 697         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
 698         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
 699         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
 700         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
 701         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
 702         /* CK_GEN2 clocks */
 703         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
 704         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
 705         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
 706         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 707         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
 708         /* CK_GEN3 clocks */
 709         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
 710         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 711         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
 712         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 713         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 714         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 715         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 716         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310 | CK_7XX),
 717         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 718         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 719         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 720         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
 721         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 722         /* ULPD clocks */
 723         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 724         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 725         CLK(NULL,       "uart1_ck",     &uart1_7xx,     CK_7XX),
 726         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 727         CLK(NULL,       "uart2_ck",     &uart2_7xx,     CK_7XX),
 728         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 729         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 730         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 731         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 732         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 733         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 734         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
 735         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 736         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 737         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 738         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 739         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 740         CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
 741         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 742         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 743         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 744         /* Virtual clocks */
 745         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 746         CLK("omap_i2c.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
 747         CLK("omap_i2c.1", "ick",        &i2c_ick,       CK_16XX),
 748         CLK("omap_i2c.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
 749         CLK("omap1_spi100k.1", "fck",   &dummy_ck,      CK_7XX),
 750         CLK("omap1_spi100k.1", "ick",   &dummy_ck,      CK_7XX),
 751         CLK("omap1_spi100k.2", "fck",   &dummy_ck,      CK_7XX),
 752         CLK("omap1_spi100k.2", "ick",   &dummy_ck,      CK_7XX),
 753         CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 754         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 755         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 756         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 757         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 758         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 759         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 760         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 761         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 762         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 763 };
 764
 765 /*
 766  * init
 767  */
 768
 769 static struct clk_functions omap1_clk_functions = {
 770         .clk_enable             = omap1_clk_enable,
 771         .clk_disable            = omap1_clk_disable,
 772         .clk_round_rate         = omap1_clk_round_rate,
 773         .clk_set_rate           = omap1_clk_set_rate,
 774         .clk_disable_unused     = omap1_clk_disable_unused,
 775 };
 776
 777 static void __init omap1_show_rates(void)
 778 {
 779         pr_notice("Clocking rate (xtal/DPLL1/MPU): "
 780                         "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 781                 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 782                 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 783                 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 784 }
 785
 786 u32 cpu_mask;
 787
 788 int __init omap1_clk_init(void)
 789 {
 790         struct omap_clk *c;
 791         const struct omap_clock_config *info;
 792         int crystal_type = 0; /* Default 12 MHz */
 793         u32 reg;
 794
 795 #ifdef CONFIG_DEBUG_LL
 796         /*
 797          * Resets some clocks that may be left on from bootloader,
 798          * but leaves serial clocks on.
 799          */
 800         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 801 #endif
 802
 803         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 804         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 805         omap_writew(reg, SOFT_REQ_REG);
 806         if (!cpu_is_omap15xx())
 807                 omap_writew(0, SOFT_REQ_REG2);
 808
 809         clk_init(&omap1_clk_functions);
 810
 811         /* By default all idlect1 clocks are allowed to idle */
 812         arm_idlect1_mask = ~0;
 813
 814         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 815                 clk_preinit(c->lk.clk);
 816
 817         cpu_mask = 0;
 818         if (cpu_is_omap1710())
 819                 cpu_mask |= CK_1710;
 820         if (cpu_is_omap16xx())
 821                 cpu_mask |= CK_16XX;
 822         if (cpu_is_omap1510())
 823                 cpu_mask |= CK_1510;
 824         if (cpu_is_omap7xx())
 825                 cpu_mask |= CK_7XX;
 826         if (cpu_is_omap310())
 827                 cpu_mask |= CK_310;
 828
 829         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 830                 if (c->cpu & cpu_mask) {
 831                         clkdev_add(&c->lk);
 832                         clk_register(c->lk.clk);
 833                 }
 834
 835         /* Pointers to these clocks are needed by code in clock.c */
 836         api_ck_p = clk_get(NULL, "api_ck");
 837         ck_dpll1_p = clk_get(NULL, "ck_dpll1");
 838         ck_ref_p = clk_get(NULL, "ck_ref");
 839
 840         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 841         if (info != NULL) {
 842                 if (!cpu_is_omap15xx())
 843                         crystal_type = info->system_clock_type;
 844         }
 845
 846         if (cpu_is_omap7xx())
 847                 ck_ref.rate = 13000000;
 848         if (cpu_is_omap16xx() && crystal_type == 2)
 849                 ck_ref.rate = 19200000;
 850
 851         pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
 852                 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 853                 omap_readw(ARM_CKCTL));
 854
 855         /* We want to be in syncronous scalable mode */
 856         omap_writew(0x1000, ARM_SYSST);
 857
 858
 859         /*
 860          * Initially use the values set by bootloader. Determine PLL rate and
 861          * recalculate dependent clocks as if kernel had changed PLL or
 862          * divisors. See also omap1_clk_late_init() that can reprogram dpll1
 863          * after the SRAM is initialized.
 864          */
 865         {
 866                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 867
 868                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 869                 if (pll_ctl_val & 0x10) {
 870                         /* PLL enabled, apply multiplier and divisor */
 871                         if (pll_ctl_val & 0xf80)
 872                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 873                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 874                 } else {
 875                         /* PLL disabled, apply bypass divisor */
 876                         switch (pll_ctl_val & 0xc) {
 877                         case 0:
 878                                 break;
 879                         case 0x4:
 880                                 ck_dpll1.rate /= 2;
 881                                 break;
 882                         default:
 883                                 ck_dpll1.rate /= 4;
 884                                 break;
 885                         }
 886                 }
 887         }
 888         propagate_rate(&ck_dpll1);
 889         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 890         propagate_rate(&ck_ref);
 891         omap1_show_rates();
 892         if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
 893                 /* Select slicer output as OMAP input clock */
 894                 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
 895                                 OMAP7XX_PCC_UPLD_CTRL);
 896         }
 897
 898         /* Amstrad Delta wants BCLK high when inactive */
 899         if (machine_is_ams_delta())
 900                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 901                                 (1 << SDW_MCLK_INV_BIT),
 902                                 ULPD_CLOCK_CTRL);
 903
 904         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 905         /* (on 730, bit 13 must not be cleared) */
 906         if (cpu_is_omap7xx())
 907                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 908         else
 909                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 910
 911         /* Put DSP/MPUI into reset until needed */
 912         omap_writew(0, ARM_RSTCT1);
 913         omap_writew(1, ARM_RSTCT2);
 914         omap_writew(0x400, ARM_IDLECT1);
 915
 916         /*
 917          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 918          * of the ARM_IDLECT2 register must be set to zero. The power-on
 919          * default value of this bit is one.
 920          */
 921         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 922
 923         /*
 924          * Only enable those clocks we will need, let the drivers
 925          * enable other clocks as necessary
 926          */
 927         clk_enable(&armper_ck.clk);
 928         clk_enable(&armxor_ck.clk);
 929         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 930
 931         if (cpu_is_omap15xx())
 932                 clk_enable(&arm_gpio_ck);
 933
 934         return 0;
 935 }
 936
 937 #define OMAP1_DPLL1_SANE_VALUE  60000000
 938
 939 void __init omap1_clk_late_init(void)
 940 {
 941         unsigned long rate = ck_dpll1.rate;
 942
 943         /* Find the highest supported frequency and enable it */
 944         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 945                 pr_err("System frequencies not set, using default. Check your config.\n");
 946                 /*
 947                  * Reprogramming the DPLL is tricky, it must be done from SRAM.
 948                  */
 949                 omap_sram_reprogram_clock(0x2290, 0x0005);
 950                 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
 951         }
 952         propagate_rate(&ck_dpll1);
 953         omap1_show_rates();
 954         loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
 955 }