2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/clk/mxs.h>
15 #include <linux/clkdev.h>
16 #include <linux/clocksource.h>
17 #include <linux/can/platform/flexcan.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/irqchip.h>
23 #include <linux/irqchip/mxs.h>
24 #include <linux/micrel_phy.h>
25 #include <linux/mxsfb.h>
26 #include <linux/of_address.h>
27 #include <linux/of_platform.h>
28 #include <linux/phy.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/time.h>
33 #include <asm/system_misc.h>
34 #include <mach/digctl.h>
37 static struct fb_videomode mx23evk_video_modes[] = {
39 .name = "Samsung-LMS430HF02",
43 .pixclock = 108096, /* picosecond (9.2 MHz) */
53 static struct fb_videomode mx28evk_video_modes[] = {
55 .name = "Seiko-43WVF1G",
59 .pixclock = 29851, /* picosecond (33.5 MHz) */
69 static struct fb_videomode m28evk_video_modes[] = {
71 .name = "Ampire AM-800480R2TMQW-T01H",
75 .pixclock = 30066, /* picosecond (33.26 MHz) */
85 static struct fb_videomode apx4devkit_video_modes[] = {
87 .name = "HannStar PJ70112A",
91 .pixclock = 33333, /* picosecond (30.00 MHz) */
98 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
102 static struct fb_videomode apf28dev_video_modes[] = {
108 .pixclock = 30303, /* picosecond */
110 .right_margin = 96, /* at least 3 & 1 */
111 .upper_margin = 0x14,
112 .lower_margin = 0x15,
115 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
119 static struct fb_videomode cfa10049_video_modes[] = {
121 .name = "Himax HX8357-B",
125 .pixclock = 108506, /* picosecond (9.216 MHz) */
135 static struct mxsfb_platform_data mxsfb_pdata __initdata;
138 * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
140 #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
142 static int flexcan0_en, flexcan1_en;
144 static void mx28evk_flexcan_switch(void)
146 if (flexcan0_en || flexcan1_en)
147 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
149 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
152 static void mx28evk_flexcan0_switch(int enable)
154 flexcan0_en = enable;
155 mx28evk_flexcan_switch();
158 static void mx28evk_flexcan1_switch(int enable)
160 flexcan1_en = enable;
161 mx28evk_flexcan_switch();
164 static struct flexcan_platform_data flexcan_pdata[2];
166 static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
167 OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
168 OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
169 OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]),
170 OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]),
174 static void __init imx23_timer_init(void)
177 clocksource_of_init();
180 static void __init imx28_timer_init(void)
183 clocksource_of_init();
186 #define OCOTP_WORD_OFFSET 0x20
187 #define OCOTP_WORD_COUNT 0x20
189 #define BM_OCOTP_CTRL_BUSY (1 << 8)
190 #define BM_OCOTP_CTRL_ERROR (1 << 9)
191 #define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
193 static DEFINE_MUTEX(ocotp_mutex);
194 static u32 ocotp_words[OCOTP_WORD_COUNT];
196 static const u32 *mxs_get_ocotp(void)
198 struct device_node *np;
199 void __iomem *ocotp_base;
207 np = of_find_compatible_node(NULL, NULL, "fsl,ocotp");
208 ocotp_base = of_iomap(np, 0);
209 WARN_ON(!ocotp_base);
211 mutex_lock(&ocotp_mutex);
214 * clk_enable(hbus_clk) for ocotp can be skipped
215 * as it must be on when system is running.
218 /* try to clear ERROR bit */
219 __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
221 /* check both BUSY and ERROR cleared */
222 while ((__raw_readl(ocotp_base) &
223 (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
226 if (unlikely(!timeout))
229 /* open OCOTP banks for read */
230 __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
232 /* approximately wait 32 hclk cycles */
235 /* poll BUSY bit becoming cleared */
237 while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
240 if (unlikely(!timeout))
243 for (i = 0; i < OCOTP_WORD_COUNT; i++)
244 ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
247 /* close banks for power saving */
248 __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
252 mutex_unlock(&ocotp_mutex);
257 mutex_unlock(&ocotp_mutex);
258 pr_err("%s: timeout in reading OCOTP\n", __func__);
268 static void __init update_fec_mac_prop(enum mac_oui oui)
270 struct device_node *np, *from = NULL;
271 struct property *newmac;
272 const u32 *ocotp = mxs_get_ocotp();
277 for (i = 0; i < 2; i++) {
278 np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
284 if (of_get_property(np, "local-mac-address", NULL))
287 newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
290 newmac->value = newmac + 1;
293 newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
300 * OCOTP only stores the last 4 octets for each mac address,
301 * so hard-code OUI here.
303 macaddr = newmac->value;
315 case OUI_CRYSTALFONTZ:
322 macaddr[3] = (val >> 16) & 0xff;
323 macaddr[4] = (val >> 8) & 0xff;
324 macaddr[5] = (val >> 0) & 0xff;
326 of_update_property(np, newmac);
330 static void __init imx23_evk_init(void)
332 mxsfb_pdata.mode_list = mx23evk_video_modes;
333 mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes);
334 mxsfb_pdata.default_bpp = 32;
335 mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
336 mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
337 MXSFB_SYNC_DOTCLK_FAILING_ACT;
340 static inline void enable_clk_enet_out(void)
342 struct clk *clk = clk_get_sys("enet_out", NULL);
345 clk_prepare_enable(clk);
348 static void __init imx28_evk_init(void)
350 enable_clk_enet_out();
351 update_fec_mac_prop(OUI_FSL);
353 mxsfb_pdata.mode_list = mx28evk_video_modes;
354 mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
355 mxsfb_pdata.default_bpp = 32;
356 mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
357 mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
358 MXSFB_SYNC_DOTCLK_FAILING_ACT;
360 mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
363 static void __init imx28_evk_post_init(void)
365 if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
367 flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch;
368 flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch;
372 static void __init m28evk_init(void)
374 mxsfb_pdata.mode_list = m28evk_video_modes;
375 mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
376 mxsfb_pdata.default_bpp = 16;
377 mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
378 mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
381 static void __init sc_sps1_init(void)
383 enable_clk_enet_out();
386 static int apx4devkit_phy_fixup(struct phy_device *phy)
388 phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
392 static void __init apx4devkit_init(void)
394 enable_clk_enet_out();
396 if (IS_BUILTIN(CONFIG_PHYLIB))
397 phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
398 apx4devkit_phy_fixup);
400 mxsfb_pdata.mode_list = apx4devkit_video_modes;
401 mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes);
402 mxsfb_pdata.default_bpp = 32;
403 mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
404 mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
405 MXSFB_SYNC_DOTCLK_FAILING_ACT;
408 #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0)
409 #define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1)
410 #define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2)
411 #define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3)
412 #define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4)
413 #define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6)
414 #define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7)
415 #define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8)
416 #define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16)
418 #define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29)
419 #define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
420 #define TX28_FEC_nINT MXS_GPIO_NR(4, 5)
422 static const struct gpio tx28_gpios[] __initconst = {
423 { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
424 { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
425 { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
426 { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
427 { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
428 { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
429 { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
430 { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
431 { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
432 { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
433 { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
434 { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
437 static void __init tx28_post_init(void)
439 struct device_node *np;
440 struct platform_device *pdev;
441 struct pinctrl *pctl;
444 enable_clk_enet_out();
446 np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
447 pdev = of_find_device_by_node(np);
449 pr_err("%s: failed to find fec device\n", __func__);
453 pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
455 pr_err("%s: failed to get pinctrl state\n", __func__);
459 ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
461 pr_err("%s: failed to request gpios: %d\n", __func__, ret);
465 /* Power up fec phy */
466 gpio_set_value(TX28_FEC_PHY_POWER, 1);
467 msleep(26); /* 25ms according to data sheet */
469 /* Mode strap pins */
470 gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
471 gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
472 gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
474 udelay(100); /* minimum assertion time for nRST */
476 /* Deasserting FEC PHY RESET */
477 gpio_set_value(TX28_FEC_PHY_RESET, 1);
482 static void __init cfa10049_init(void)
484 enable_clk_enet_out();
485 update_fec_mac_prop(OUI_CRYSTALFONTZ);
487 mxsfb_pdata.mode_list = cfa10049_video_modes;
488 mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes);
489 mxsfb_pdata.default_bpp = 32;
490 mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
491 mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
494 static void __init cfa10037_init(void)
496 enable_clk_enet_out();
497 update_fec_mac_prop(OUI_CRYSTALFONTZ);
500 static void __init apf28_init(void)
502 enable_clk_enet_out();
504 mxsfb_pdata.mode_list = apf28dev_video_modes;
505 mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes);
506 mxsfb_pdata.default_bpp = 16;
507 mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT;
508 mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
509 MXSFB_SYNC_DOTCLK_FAILING_ACT;
512 static void __init mxs_machine_init(void)
514 if (of_machine_is_compatible("fsl,imx28-evk"))
516 else if (of_machine_is_compatible("fsl,imx23-evk"))
518 else if (of_machine_is_compatible("denx,m28evk"))
520 else if (of_machine_is_compatible("bluegiga,apx4devkit"))
522 else if (of_machine_is_compatible("crystalfontz,cfa10037"))
524 else if (of_machine_is_compatible("crystalfontz,cfa10049"))
526 else if (of_machine_is_compatible("armadeus,imx28-apf28"))
528 else if (of_machine_is_compatible("schulercontrol,imx28-sps1"))
531 of_platform_populate(NULL, of_default_bus_match_table,
532 mxs_auxdata_lookup, NULL);
534 if (of_machine_is_compatible("karo,tx28"))
537 if (of_machine_is_compatible("fsl,imx28-evk"))
538 imx28_evk_post_init();
541 #define MX23_CLKCTRL_RESET_OFFSET 0x120
542 #define MX28_CLKCTRL_RESET_OFFSET 0x1e0
543 #define MXS_CLKCTRL_RESET_CHIP (1 << 1)
546 * Reset the system. It is called by machine_restart().
548 static void mxs_restart(char mode, const char *cmd)
550 struct device_node *np;
551 void __iomem *reset_addr;
553 np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
554 reset_addr = of_iomap(np, 0);
558 if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
559 reset_addr += MX23_CLKCTRL_RESET_OFFSET;
561 reset_addr += MX28_CLKCTRL_RESET_OFFSET;
564 __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
566 pr_err("Failed to assert the chip reset\n");
568 /* Delay to allow the serial port to show the message */
572 /* We'll take a jump through zero as a poor second */
576 static const char *imx23_dt_compat[] __initdata = {
581 static const char *imx28_dt_compat[] __initdata = {
586 DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
587 .map_io = debug_ll_io_init,
588 .init_irq = irqchip_init,
589 .handle_irq = icoll_handle_irq,
590 .init_time = imx23_timer_init,
591 .init_machine = mxs_machine_init,
592 .dt_compat = imx23_dt_compat,
593 .restart = mxs_restart,
596 DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
597 .map_io = debug_ll_io_init,
598 .init_irq = irqchip_init,
599 .handle_irq = icoll_handle_irq,
600 .init_time = imx28_timer_init,
601 .init_machine = mxs_machine_init,
602 .dt_compat = imx28_dt_compat,
603 .restart = mxs_restart,