Pileus Git - ~andy/linux/blob - arch/arm/mach-mxs/clock-mx28.c

   1 /*
   2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/mm.h>
  20 #include <linux/delay.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/clkdev.h>
  25 #include <linux/spinlock.h>
  26
  27 #include <asm/clkdev.h>
  28 #include <asm/div64.h>
  29
  30 #include <mach/mx28.h>
  31 #include <mach/common.h>
  32 #include <mach/clock.h>
  33 #include <mach/digctl.h>
  34
  35 #include "regs-clkctrl-mx28.h"
  36
  37 #define CLKCTRL_BASE_ADDR       MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
  38 #define DIGCTRL_BASE_ADDR       MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
  39
  40 #define PARENT_RATE_SHIFT       8
  41
  42 static struct clk pll2_clk;
  43 static struct clk cpu_clk;
  44 static struct clk emi_clk;
  45 static struct clk saif0_clk;
  46 static struct clk saif1_clk;
  47 static struct clk clk32k_clk;
  48 static DEFINE_SPINLOCK(clkmux_lock);
  49
  50 /*
  51  * HW_SAIF_CLKMUX_SEL:
  52  *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
  53  *              clock pins selected for SAIF1 input clocks.
  54  *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
  55  *              SAIF0 clock inputs selected for SAIF1 input clocks.
  56  *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
  57  *              clocks.
  58  *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
  59  *              clocks.
  60  */
  61 int mxs_saif_clkmux_select(unsigned int clkmux)
  62 {
  63         if (clkmux > 0x3)
  64                 return -EINVAL;
  65
  66         spin_lock(&clkmux_lock);
  67         __raw_writel(BM_DIGCTL_CTRL_SAIF_CLKMUX,
  68                         DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_CLR_ADDR);
  69         __raw_writel(clkmux << BP_DIGCTL_CTRL_SAIF_CLKMUX,
  70                         DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_SET_ADDR);
  71         spin_unlock(&clkmux_lock);
  72
  73         return 0;
  74 }
  75
  76 static int _raw_clk_enable(struct clk *clk)
  77 {
  78         u32 reg;
  79
  80         if (clk->enable_reg) {
  81                 reg = __raw_readl(clk->enable_reg);
  82                 reg &= ~(1 << clk->enable_shift);
  83                 __raw_writel(reg, clk->enable_reg);
  84         }
  85
  86         return 0;
  87 }
  88
  89 static void _raw_clk_disable(struct clk *clk)
  90 {
  91         u32 reg;
  92
  93         if (clk->enable_reg) {
  94                 reg = __raw_readl(clk->enable_reg);
  95                 reg |= 1 << clk->enable_shift;
  96                 __raw_writel(reg, clk->enable_reg);
  97         }
  98 }
  99
 100 /*
 101  * ref_xtal_clk
 102  */
 103 static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
 104 {
 105         return 24000000;
 106 }
 107
 108 static struct clk ref_xtal_clk = {
 109         .get_rate = ref_xtal_clk_get_rate,
 110 };
 111
 112 /*
 113  * pll_clk
 114  */
 115 static unsigned long pll0_clk_get_rate(struct clk *clk)
 116 {
 117         return 480000000;
 118 }
 119
 120 static unsigned long pll1_clk_get_rate(struct clk *clk)
 121 {
 122         return 480000000;
 123 }
 124
 125 static unsigned long pll2_clk_get_rate(struct clk *clk)
 126 {
 127         return 50000000;
 128 }
 129
 130 #define _CLK_ENABLE_PLL(name, r, g)                                     \
 131 static int name##_enable(struct clk *clk)                               \
 132 {                                                                       \
 133         __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
 134                      CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET);    \
 135         udelay(10);                                                     \
 136                                                                         \
 137         if (clk == &pll2_clk)                                           \
 138                 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
 139                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
 140         else                                                            \
 141                 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
 142                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
 143                                                                         \
 144         return 0;                                                       \
 145 }
 146
 147 _CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
 148 _CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
 149 _CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
 150
 151 #define _CLK_DISABLE_PLL(name, r, g)                                    \
 152 static void name##_disable(struct clk *clk)                             \
 153 {                                                                       \
 154         __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
 155                      CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR);    \
 156                                                                         \
 157         if (clk == &pll2_clk)                                           \
 158                 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
 159                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
 160         else                                                            \
 161                 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
 162                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
 163                                                                         \
 164 }
 165
 166 _CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
 167 _CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
 168 _CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
 169
 170 #define _DEFINE_CLOCK_PLL(name)                                         \
 171         static struct clk name = {                                      \
 172                 .get_rate       = name##_get_rate,                      \
 173                 .enable         = name##_enable,                        \
 174                 .disable        = name##_disable,                       \
 175                 .parent         = &ref_xtal_clk,                        \
 176         }
 177
 178 _DEFINE_CLOCK_PLL(pll0_clk);
 179 _DEFINE_CLOCK_PLL(pll1_clk);
 180 _DEFINE_CLOCK_PLL(pll2_clk);
 181
 182 /*
 183  * ref_clk
 184  */
 185 #define _CLK_GET_RATE_REF(name, sr, ss)                                 \
 186 static unsigned long name##_get_rate(struct clk *clk)                   \
 187 {                                                                       \
 188         unsigned long parent_rate;                                      \
 189         u32 reg, div;                                                   \
 190                                                                         \
 191         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
 192         div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
 193         parent_rate = clk_get_rate(clk->parent);                        \
 194                                                                         \
 195         return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
 196                         div, PARENT_RATE_SHIFT);                        \
 197 }
 198
 199 _CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
 200 _CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
 201 _CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
 202 _CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
 203 _CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
 204 _CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
 205
 206 #define _DEFINE_CLOCK_REF(name, er, es)                                 \
 207         static struct clk name = {                                      \
 208                 .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
 209                 .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
 210                 .get_rate       = name##_get_rate,                      \
 211                 .enable         = _raw_clk_enable,                      \
 212                 .disable        = _raw_clk_disable,                     \
 213                 .parent         = &pll0_clk,                            \
 214         }
 215
 216 _DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
 217 _DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
 218 _DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
 219 _DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
 220 _DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
 221 _DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
 222
 223 /*
 224  * General clocks
 225  *
 226  * clk_get_rate
 227  */
 228 static unsigned long lradc_clk_get_rate(struct clk *clk)
 229 {
 230         return clk_get_rate(clk->parent) / 16;
 231 }
 232
 233 static unsigned long rtc_clk_get_rate(struct clk *clk)
 234 {
 235         /* ref_xtal_clk is implemented as the only parent */
 236         return clk_get_rate(clk->parent) / 768;
 237 }
 238
 239 static unsigned long clk32k_clk_get_rate(struct clk *clk)
 240 {
 241         return clk->parent->get_rate(clk->parent) / 750;
 242 }
 243
 244 static unsigned long spdif_clk_get_rate(struct clk *clk)
 245 {
 246         return clk_get_rate(clk->parent) / 4;
 247 }
 248
 249 #define _CLK_GET_RATE(name, rs)                                         \
 250 static unsigned long name##_get_rate(struct clk *clk)                   \
 251 {                                                                       \
 252         u32 reg, div;                                                   \
 253                                                                         \
 254         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
 255                                                                         \
 256         if (clk->parent == &ref_xtal_clk)                               \
 257                 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
 258                         BP_CLKCTRL_##rs##_DIV_XTAL;                     \
 259         else                                                            \
 260                 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
 261                         BP_CLKCTRL_##rs##_DIV_##rs;                     \
 262                                                                         \
 263         if (!div)                                                       \
 264                 return -EINVAL;                                         \
 265                                                                         \
 266         return clk_get_rate(clk->parent) / div;                         \
 267 }
 268
 269 _CLK_GET_RATE(cpu_clk, CPU)
 270 _CLK_GET_RATE(emi_clk, EMI)
 271
 272 #define _CLK_GET_RATE1(name, rs)                                        \
 273 static unsigned long name##_get_rate(struct clk *clk)                   \
 274 {                                                                       \
 275         u32 reg, div;                                                   \
 276                                                                         \
 277         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
 278         div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
 279                                                                         \
 280         if (!div)                                                       \
 281                 return -EINVAL;                                         \
 282                                                                         \
 283         if (clk == &saif0_clk || clk == &saif1_clk)                     \
 284                 return clk_get_rate(clk->parent) >> 16 * div;           \
 285         else                                                            \
 286                 return clk_get_rate(clk->parent) / div;                 \
 287 }
 288
 289 _CLK_GET_RATE1(hbus_clk, HBUS)
 290 _CLK_GET_RATE1(xbus_clk, XBUS)
 291 _CLK_GET_RATE1(ssp0_clk, SSP0)
 292 _CLK_GET_RATE1(ssp1_clk, SSP1)
 293 _CLK_GET_RATE1(ssp2_clk, SSP2)
 294 _CLK_GET_RATE1(ssp3_clk, SSP3)
 295 _CLK_GET_RATE1(gpmi_clk, GPMI)
 296 _CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
 297 _CLK_GET_RATE1(saif0_clk, SAIF0)
 298 _CLK_GET_RATE1(saif1_clk, SAIF1)
 299
 300 #define _CLK_GET_RATE_STUB(name)                                        \
 301 static unsigned long name##_get_rate(struct clk *clk)                   \
 302 {                                                                       \
 303         return clk_get_rate(clk->parent);                               \
 304 }
 305
 306 _CLK_GET_RATE_STUB(uart_clk)
 307 _CLK_GET_RATE_STUB(pwm_clk)
 308 _CLK_GET_RATE_STUB(can0_clk)
 309 _CLK_GET_RATE_STUB(can1_clk)
 310 _CLK_GET_RATE_STUB(fec_clk)
 311
 312 /*
 313  * clk_set_rate
 314  */
 315 /* fool compiler */
 316 #define BM_CLKCTRL_CPU_DIV      0
 317 #define BP_CLKCTRL_CPU_DIV      0
 318 #define BM_CLKCTRL_CPU_BUSY     0
 319
 320 #define _CLK_SET_RATE(name, dr, fr, fs)                                 \
 321 static int name##_set_rate(struct clk *clk, unsigned long rate)         \
 322 {                                                                       \
 323         u32 reg, bm_busy, div_max, d, f, div, frac;                     \
 324         unsigned long diff, parent_rate, calc_rate;                     \
 325                                                                         \
 326         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
 327         bm_busy = BM_CLKCTRL_##dr##_BUSY;                               \
 328                                                                         \
 329         if (clk->parent == &ref_xtal_clk) {                             \
 330                 parent_rate = clk_get_rate(clk->parent);                \
 331                 div = DIV_ROUND_UP(parent_rate, rate);                  \
 332                 if (clk == &cpu_clk) {                                  \
 333                         div_max = BM_CLKCTRL_CPU_DIV_XTAL >>            \
 334                                 BP_CLKCTRL_CPU_DIV_XTAL;                \
 335                         bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;         \
 336                 }                                                       \
 337                 if (div == 0 || div > div_max)                          \
 338                         return -EINVAL;                                 \
 339         } else {                                                        \
 340                 /*                                                      \
 341                  * hack alert: this block modifies clk->parent, too,    \
 342                  * so the base to use it the grand parent.              \
 343                  */                                                     \
 344                 parent_rate = clk_get_rate(clk->parent->parent);        \
 345                 rate >>= PARENT_RATE_SHIFT;                             \
 346                 parent_rate >>= PARENT_RATE_SHIFT;                      \
 347                 diff = parent_rate;                                     \
 348                 div = frac = 1;                                         \
 349                 if (clk == &cpu_clk) {                                  \
 350                         div_max = BM_CLKCTRL_CPU_DIV_CPU >>             \
 351                                 BP_CLKCTRL_CPU_DIV_CPU;                 \
 352                         bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;          \
 353                 }                                                       \
 354                 for (d = 1; d <= div_max; d++) {                        \
 355                         f = parent_rate * 18 / d / rate;                \
 356                         if ((parent_rate * 18 / d) % rate)              \
 357                                 f++;                                    \
 358                         if (f < 18 || f > 35)                           \
 359                                 continue;                               \
 360                                                                         \
 361                         calc_rate = parent_rate * 18 / f / d;           \
 362                         if (calc_rate > rate)                           \
 363                                 continue;                               \
 364                                                                         \
 365                         if (rate - calc_rate < diff) {                  \
 366                                 frac = f;                               \
 367                                 div = d;                                \
 368                                 diff = rate - calc_rate;                \
 369                         }                                               \
 370                                                                         \
 371                         if (diff == 0)                                  \
 372                                 break;                                  \
 373                 }                                                       \
 374                                                                         \
 375                 if (diff == parent_rate)                                \
 376                         return -EINVAL;                                 \
 377                                                                         \
 378                 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
 379                 reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC;                   \
 380                 reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC;            \
 381                 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
 382         }                                                               \
 383                                                                         \
 384         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
 385         if (clk == &cpu_clk) {                                          \
 386                 reg &= ~BM_CLKCTRL_CPU_DIV_CPU;                         \
 387                 reg |= div << BP_CLKCTRL_CPU_DIV_CPU;                   \
 388         } else {                                                        \
 389                 reg &= ~BM_CLKCTRL_##dr##_DIV;                          \
 390                 reg |= div << BP_CLKCTRL_##dr##_DIV;                    \
 391                 if (reg & (1 << clk->enable_shift)) {                   \
 392                         pr_err("%s: clock is gated\n", __func__);       \
 393                         return -EINVAL;                                 \
 394                 }                                                       \
 395         }                                                               \
 396         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
 397                                                                         \
 398         return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, bm_busy);           \
 399 }
 400
 401 _CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
 402 _CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
 403 _CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
 404 _CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
 405 _CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
 406 _CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
 407 _CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
 408
 409 #define _CLK_SET_RATE1(name, dr)                                        \
 410 static int name##_set_rate(struct clk *clk, unsigned long rate)         \
 411 {                                                                       \
 412         u32 reg, div_max, div;                                          \
 413         unsigned long parent_rate;                                      \
 414                                                                         \
 415         parent_rate = clk_get_rate(clk->parent);                        \
 416         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
 417                                                                         \
 418         div = DIV_ROUND_UP(parent_rate, rate);                          \
 419         if (div == 0 || div > div_max)                                  \
 420                 return -EINVAL;                                         \
 421                                                                         \
 422         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
 423         reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
 424         reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
 425         if (reg & (1 << clk->enable_shift)) {                           \
 426                 pr_err("%s: clock is gated\n", __func__);               \
 427                 return -EINVAL;                                         \
 428         }                                                               \
 429         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
 430                                                                         \
 431         return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);\
 432 }
 433
 434 _CLK_SET_RATE1(xbus_clk, XBUS)
 435
 436 /* saif clock uses 16 bits frac div */
 437 #define _CLK_SET_RATE_SAIF(name, rs)                                    \
 438 static int name##_set_rate(struct clk *clk, unsigned long rate)         \
 439 {                                                                       \
 440         u16 div;                                                        \
 441         u32 reg;                                                        \
 442         u64 lrate;                                                      \
 443         unsigned long parent_rate;                                      \
 444                                                                         \
 445         parent_rate = clk_get_rate(clk->parent);                        \
 446         if (rate > parent_rate)                                         \
 447                 return -EINVAL;                                         \
 448                                                                         \
 449         lrate = (u64)rate << 16;                                        \
 450         do_div(lrate, parent_rate);                                     \
 451         div = (u16)lrate;                                               \
 452                                                                         \
 453         if (!div)                                                       \
 454                 return -EINVAL;                                         \
 455                                                                         \
 456         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
 457         reg &= ~BM_CLKCTRL_##rs##_DIV;                                  \
 458         reg |= div << BP_CLKCTRL_##rs##_DIV;                            \
 459         if (reg & (1 << clk->enable_shift)) {                           \
 460                 pr_err("%s: clock is gated\n", __func__);               \
 461                 return -EINVAL;                                         \
 462         }                                                               \
 463         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
 464                                                                         \
 465         return mxs_clkctrl_timeout(HW_CLKCTRL_##rs, BM_CLKCTRL_##rs##_BUSY);\
 466 }
 467
 468 _CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
 469 _CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
 470
 471 #define _CLK_SET_RATE_STUB(name)                                        \
 472 static int name##_set_rate(struct clk *clk, unsigned long rate)         \
 473 {                                                                       \
 474         return -EINVAL;                                                 \
 475 }
 476
 477 _CLK_SET_RATE_STUB(emi_clk)
 478 _CLK_SET_RATE_STUB(uart_clk)
 479 _CLK_SET_RATE_STUB(pwm_clk)
 480 _CLK_SET_RATE_STUB(spdif_clk)
 481 _CLK_SET_RATE_STUB(clk32k_clk)
 482 _CLK_SET_RATE_STUB(can0_clk)
 483 _CLK_SET_RATE_STUB(can1_clk)
 484 _CLK_SET_RATE_STUB(fec_clk)
 485
 486 /*
 487  * clk_set_parent
 488  */
 489 #define _CLK_SET_PARENT(name, bit)                                      \
 490 static int name##_set_parent(struct clk *clk, struct clk *parent)       \
 491 {                                                                       \
 492         if (parent != clk->parent) {                                    \
 493                 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
 494                          CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG);    \
 495                 clk->parent = parent;                                   \
 496         }                                                               \
 497                                                                         \
 498         return 0;                                                       \
 499 }
 500
 501 _CLK_SET_PARENT(cpu_clk, CPU)
 502 _CLK_SET_PARENT(emi_clk, EMI)
 503 _CLK_SET_PARENT(ssp0_clk, SSP0)
 504 _CLK_SET_PARENT(ssp1_clk, SSP1)
 505 _CLK_SET_PARENT(ssp2_clk, SSP2)
 506 _CLK_SET_PARENT(ssp3_clk, SSP3)
 507 _CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
 508 _CLK_SET_PARENT(gpmi_clk, GPMI)
 509 _CLK_SET_PARENT(saif0_clk, SAIF0)
 510 _CLK_SET_PARENT(saif1_clk, SAIF1)
 511
 512 #define _CLK_SET_PARENT_STUB(name)                                      \
 513 static int name##_set_parent(struct clk *clk, struct clk *parent)       \
 514 {                                                                       \
 515         if (parent != clk->parent)                                      \
 516                 return -EINVAL;                                         \
 517         else                                                            \
 518                 return 0;                                               \
 519 }
 520
 521 _CLK_SET_PARENT_STUB(pwm_clk)
 522 _CLK_SET_PARENT_STUB(uart_clk)
 523 _CLK_SET_PARENT_STUB(clk32k_clk)
 524 _CLK_SET_PARENT_STUB(spdif_clk)
 525 _CLK_SET_PARENT_STUB(fec_clk)
 526 _CLK_SET_PARENT_STUB(can0_clk)
 527 _CLK_SET_PARENT_STUB(can1_clk)
 528
 529 /*
 530  * clk definition
 531  */
 532 static struct clk cpu_clk = {
 533         .get_rate = cpu_clk_get_rate,
 534         .set_rate = cpu_clk_set_rate,
 535         .set_parent = cpu_clk_set_parent,
 536         .parent = &ref_cpu_clk,
 537 };
 538
 539 static struct clk hbus_clk = {
 540         .get_rate = hbus_clk_get_rate,
 541         .parent = &cpu_clk,
 542 };
 543
 544 static struct clk xbus_clk = {
 545         .get_rate = xbus_clk_get_rate,
 546         .set_rate = xbus_clk_set_rate,
 547         .parent = &ref_xtal_clk,
 548 };
 549
 550 static struct clk lradc_clk = {
 551         .get_rate = lradc_clk_get_rate,
 552         .parent = &clk32k_clk,
 553 };
 554
 555 static struct clk rtc_clk = {
 556         .get_rate = rtc_clk_get_rate,
 557         .parent = &ref_xtal_clk,
 558 };
 559
 560 /* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
 561 static struct clk usb0_clk = {
 562         .enable_reg = DIGCTRL_BASE_ADDR,
 563         .enable_shift = 2,
 564         .enable = _raw_clk_enable,
 565         .disable = _raw_clk_disable,
 566         .parent = &pll0_clk,
 567 };
 568
 569 static struct clk usb1_clk = {
 570         .enable_reg = DIGCTRL_BASE_ADDR,
 571         .enable_shift = 16,
 572         .enable = _raw_clk_enable,
 573         .disable = _raw_clk_disable,
 574         .parent = &pll1_clk,
 575 };
 576
 577 #define _DEFINE_CLOCK(name, er, es, p)                                  \
 578         static struct clk name = {                                      \
 579                 .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
 580                 .enable_shift   = BP_CLKCTRL_##er##_##es,               \
 581                 .get_rate       = name##_get_rate,                      \
 582                 .set_rate       = name##_set_rate,                      \
 583                 .set_parent     = name##_set_parent,                    \
 584                 .enable         = _raw_clk_enable,                      \
 585                 .disable        = _raw_clk_disable,                     \
 586                 .parent         = p,                                    \
 587         }
 588
 589 _DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
 590 _DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
 591 _DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
 592 _DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
 593 _DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
 594 _DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
 595 _DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
 596 _DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
 597 _DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
 598 _DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
 599 _DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
 600 _DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
 601 _DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
 602 _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
 603 _DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
 604 _DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
 605
 606 #define _REGISTER_CLOCK(d, n, c) \
 607         { \
 608                 .dev_id = d, \
 609                 .con_id = n, \
 610                 .clk = &c, \
 611         },
 612
 613 static struct clk_lookup lookups[] = {
 614         /* for amba bus driver */
 615         _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
 616         /* for amba-pl011 driver */
 617         _REGISTER_CLOCK("duart", NULL, uart_clk)
 618         _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
 619         _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
 620         _REGISTER_CLOCK("imx28-gpmi-nand", NULL, gpmi_clk)
 621         _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
 622         _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
 623         _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
 624         _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
 625         _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
 626         _REGISTER_CLOCK("rtc", NULL, rtc_clk)
 627         _REGISTER_CLOCK("enet_out", NULL, pll2_clk)
 628         _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
 629         _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
 630         _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
 631         _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
 632         _REGISTER_CLOCK("mxs-mmc.2", NULL, ssp2_clk)
 633         _REGISTER_CLOCK("mxs-mmc.3", NULL, ssp3_clk)
 634         _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
 635         _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
 636         _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
 637         _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
 638         _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
 639         _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
 640         _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
 641         _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
 642         _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
 643         _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
 644         _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
 645         _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
 646         _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
 647         _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
 648         _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
 649         _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
 650         _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
 651 };
 652
 653 static int clk_misc_init(void)
 654 {
 655         u32 reg;
 656         int ret;
 657
 658         /* Fix up parent per register setting */
 659         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
 660         cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
 661                         &ref_xtal_clk : &ref_cpu_clk;
 662         emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
 663                         &ref_xtal_clk : &ref_emi_clk;
 664         ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
 665                         &ref_xtal_clk : &ref_io0_clk;
 666         ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
 667                         &ref_xtal_clk : &ref_io0_clk;
 668         ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
 669                         &ref_xtal_clk : &ref_io1_clk;
 670         ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
 671                         &ref_xtal_clk : &ref_io1_clk;
 672         lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
 673                         &ref_xtal_clk : &ref_pix_clk;
 674         gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
 675                         &ref_xtal_clk : &ref_gpmi_clk;
 676         saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
 677                         &ref_xtal_clk : &pll0_clk;
 678         saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
 679                         &ref_xtal_clk : &pll0_clk;
 680
 681         /* Use int div over frac when both are available */
 682         __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
 683                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
 684         __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
 685                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
 686         __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
 687                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
 688
 689         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
 690         reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
 691         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
 692
 693         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
 694         reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
 695         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
 696
 697         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
 698         reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
 699         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
 700
 701         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
 702         reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
 703         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
 704
 705         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
 706         reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
 707         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
 708
 709         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
 710         reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
 711         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
 712
 713         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
 714         reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
 715         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
 716
 717         /* SAIF has to use frac div for functional operation */
 718         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
 719         reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
 720         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
 721
 722         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
 723         reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
 724         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
 725
 726         /*
 727          * Set safe hbus clock divider. A divider of 3 ensure that
 728          * the Vddd voltage required for the cpu clock is sufficiently
 729          * high for the hbus clock.
 730          */
 731         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
 732         reg &= BM_CLKCTRL_HBUS_DIV;
 733         reg |= 3 << BP_CLKCTRL_HBUS_DIV;
 734         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
 735
 736         ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_ASM_BUSY);
 737
 738         /* Gate off cpu clock in WFI for power saving */
 739         __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
 740                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
 741
 742         /*
 743          * Extra fec clock setting
 744          * The DENX M28 uses an external clock source
 745          * and the clock output must not be enabled
 746          */
 747         if (!machine_is_m28evk()) {
 748                 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
 749                 reg &= ~BM_CLKCTRL_ENET_SLEEP;
 750                 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
 751                 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
 752         }
 753
 754         /*
 755          * 480 MHz seems too high to be ssp clock source directly,
 756          * so set frac0 to get a 288 MHz ref_io0.
 757          */
 758         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
 759         reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
 760         reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
 761         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
 762
 763         return ret;
 764 }
 765
 766 int __init mx28_clocks_init(void)
 767 {
 768         clk_misc_init();
 769
 770         /*
 771          * source ssp clock from ref_io0 than ref_xtal,
 772          * as ref_xtal only provides 24 MHz as maximum.
 773          */
 774         clk_set_parent(&ssp0_clk, &ref_io0_clk);
 775         clk_set_parent(&ssp1_clk, &ref_io0_clk);
 776         clk_set_parent(&ssp2_clk, &ref_io1_clk);
 777         clk_set_parent(&ssp3_clk, &ref_io1_clk);
 778
 779         clk_prepare_enable(&cpu_clk);
 780         clk_prepare_enable(&hbus_clk);
 781         clk_prepare_enable(&xbus_clk);
 782         clk_prepare_enable(&emi_clk);
 783         clk_prepare_enable(&uart_clk);
 784
 785         clk_set_parent(&lcdif_clk, &ref_pix_clk);
 786         clk_set_parent(&saif0_clk, &pll0_clk);
 787         clk_set_parent(&saif1_clk, &pll0_clk);
 788
 789         /*
 790          * Set an initial clock rate for the saif internal logic to work
 791          * properly. This is important when working in EXTMASTER mode that
 792          * uses the other saif's BITCLK&LRCLK but it still needs a basic
 793          * clock which should be fast enough for the internal logic.
 794          */
 795         clk_set_rate(&saif0_clk, 24000000);
 796         clk_set_rate(&saif1_clk, 24000000);
 797
 798         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 799
 800         mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
 801
 802         return 0;
 803 }