2 * Copyright (C) 2010 Linaro Limited
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c.h>
20 #include <linux/gpio.h>
21 #include <linux/leds.h>
22 #include <linux/delay.h>
24 #include <linux/fsl_devices.h>
26 #include <mach/common.h>
27 #include <mach/hardware.h>
28 #include <mach/iomux-mx51.h>
30 #include <mach/mxc_ehci.h>
33 #include <asm/setup.h>
34 #include <asm/mach-types.h>
35 #include <asm/mach/arch.h>
36 #include <asm/mach/time.h>
38 #include "devices-imx51.h"
41 #define MX51_USB_PLL_DIV_24_MHZ 0x01
43 #define EFIKAMX_PCBID0 (2*32 + 16)
44 #define EFIKAMX_PCBID1 (2*32 + 17)
45 #define EFIKAMX_PCBID2 (2*32 + 11)
47 #define EFIKAMX_BLUE_LED (2*32 + 13)
48 #define EFIKAMX_GREEN_LED (2*32 + 14)
49 #define EFIKAMX_RED_LED (2*32 + 15)
51 /* the pci ids pin have pull up. they're driven low according to board id */
52 #define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
53 #define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
54 #define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
56 static iomux_v3_cfg_t mx51efikamx_pads[] = {
58 MX51_PAD_UART1_RXD__UART1_RXD,
59 MX51_PAD_UART1_TXD__UART1_TXD,
60 MX51_PAD_UART1_RTS__UART1_RTS,
61 MX51_PAD_UART1_CTS__UART1_CTS,
68 MX51_PAD_SD1_CMD__SD1_CMD,
69 MX51_PAD_SD1_CLK__SD1_CLK,
70 MX51_PAD_SD1_DATA0__SD1_DATA0,
71 MX51_PAD_SD1_DATA1__SD1_DATA1,
72 MX51_PAD_SD1_DATA2__SD1_DATA2,
73 MX51_PAD_SD1_DATA3__SD1_DATA3,
76 MX51_PAD_SD2_CMD__SD2_CMD,
77 MX51_PAD_SD2_CLK__SD2_CLK,
78 MX51_PAD_SD2_DATA0__SD2_DATA0,
79 MX51_PAD_SD2_DATA1__SD2_DATA1,
80 MX51_PAD_SD2_DATA2__SD2_DATA2,
81 MX51_PAD_SD2_DATA3__SD2_DATA3,
84 MX51_PAD_GPIO_1_0__ESDHC1_CD,
85 MX51_PAD_GPIO_1_1__ESDHC1_WP,
86 MX51_PAD_GPIO_1_7__ESDHC2_WP,
87 MX51_PAD_GPIO_1_8__ESDHC2_CD,
90 MX51_PAD_CSI1_D9__GPIO_3_13,
91 MX51_PAD_CSI1_VSYNC__GPIO_3_14,
92 MX51_PAD_CSI1_HSYNC__GPIO_3_15,
96 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
97 static const struct imxuart_platform_data uart_pdata = {
98 .flags = IMXUART_HAVE_RTSCTS,
101 static inline void mxc_init_imx_uart(void)
103 imx51_add_imx_uart(0, &uart_pdata);
104 imx51_add_imx_uart(1, &uart_pdata);
105 imx51_add_imx_uart(2, &uart_pdata);
107 #else /* !SERIAL_IMX */
108 static inline void mxc_init_imx_uart(void)
111 #endif /* SERIAL_IMX */
113 /* This function is board specific as the bit mask for the plldiv will also
114 * be different for other Freescale SoCs, thus a common bitmask is not
115 * possible and cannot get place in /plat-mxc/ehci.c.
117 static int initialize_otg_port(struct platform_device *pdev)
120 void __iomem *usb_base;
121 void __iomem *usbother_base;
122 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
123 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
125 /* Set the PHY clock to 19.2MHz */
126 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
127 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
128 v |= MX51_USB_PLL_DIV_24_MHZ;
129 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
134 static struct mxc_usbh_platform_data dr_utmi_config = {
135 .init = initialize_otg_port,
136 .portsc = MXC_EHCI_UTMI_16BIT,
137 .flags = MXC_EHCI_INTERNAL_PHY,
140 /* PCBID2 PCBID1 PCBID0 STATE
146 static void __init mx51_efikamx_board_id(void)
150 /* things are taking time to settle */
153 gpio_request(EFIKAMX_PCBID0, "pcbid0");
154 gpio_direction_input(EFIKAMX_PCBID0);
155 gpio_request(EFIKAMX_PCBID1, "pcbid1");
156 gpio_direction_input(EFIKAMX_PCBID1);
157 gpio_request(EFIKAMX_PCBID2, "pcbid2");
158 gpio_direction_input(EFIKAMX_PCBID2);
160 id = gpio_get_value(EFIKAMX_PCBID0);
161 id |= gpio_get_value(EFIKAMX_PCBID1) << 1;
162 id |= gpio_get_value(EFIKAMX_PCBID2) << 2;
182 if ((system_rev == 0x10)
183 || (system_rev == 0x12)
184 || (system_rev == 0x14)) {
186 "EfikaMX: Unsupported board revision 1.%u!\n",
191 static struct gpio_led mx51_efikamx_leds[] = {
193 .name = "efikamx:green",
194 .default_trigger = "default-on",
195 .gpio = EFIKAMX_GREEN_LED,
198 .name = "efikamx:red",
199 .default_trigger = "ide-disk",
200 .gpio = EFIKAMX_RED_LED,
203 .name = "efikamx:blue",
204 .default_trigger = "mmc0",
205 .gpio = EFIKAMX_BLUE_LED,
209 static struct gpio_led_platform_data mx51_efikamx_leds_data = {
210 .leds = mx51_efikamx_leds,
211 .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
214 static struct platform_device mx51_efikamx_leds_device = {
218 .platform_data = &mx51_efikamx_leds_data,
222 static void __init mxc_board_init(void)
224 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
225 ARRAY_SIZE(mx51efikamx_pads));
226 mx51_efikamx_board_id();
227 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
229 imx51_add_esdhc(0, NULL);
231 /* on < 1.2 boards both SD controllers are used */
232 if (system_rev < 0x12) {
233 imx51_add_esdhc(1, NULL);
234 mx51_efikamx_leds[2].default_trigger = "mmc1";
237 platform_device_register(&mx51_efikamx_leds_device);
240 static void __init mx51_efikamx_timer_init(void)
242 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
245 static struct sys_timer mxc_timer = {
246 .init = mx51_efikamx_timer_init,
249 MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
250 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
251 .boot_params = MX51_PHYS_OFFSET + 0x100,
252 .map_io = mx51_map_io,
253 .init_irq = mx51_init_irq,
254 .init_machine = mxc_board_init,