Pileus Git - ~andy/linux/blob - arch/arm/mach-lpc32xx/phy3250.c

   1 /*
   2  * Platform support for LPC32xx SoC
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
   7  * Copyright (C) 2010 NXP Semiconductors
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/device.h>
  27 #include <linux/spi/spi.h>
  28 #include <linux/spi/eeprom.h>
  29 #include <linux/gpio.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/amba/clcd.h>
  32 #include <linux/amba/pl022.h>
  33 #include <linux/amba/pl08x.h>
  34 #include <linux/amba/mmci.h>
  35 #include <linux/of.h>
  36 #include <linux/of_address.h>
  37 #include <linux/of_irq.h>
  38 #include <linux/of_platform.h>
  39 #include <linux/clk.h>
  40
  41 #include <asm/setup.h>
  42 #include <asm/mach-types.h>
  43 #include <asm/mach/arch.h>
  44
  45 #include <mach/hardware.h>
  46 #include <mach/platform.h>
  47 #include <mach/board.h>
  48 #include <mach/gpio-lpc32xx.h>
  49 #include "common.h"
  50
  51 /*
  52  * Mapped GPIOLIB GPIOs
  53  */
  54 #define SPI0_CS_GPIO            LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
  55 #define LCD_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
  56 #define BKL_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
  57 #define MMC_PWR_ENABLE_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
  58 #define MMC_CD_GPIO             LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1)
  59 #define MMC_WP_GPIO             LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
  60
  61 /*
  62  * AMBA LCD controller
  63  */
  64 static struct clcd_panel conn_lcd_panel = {
  65         .mode           = {
  66                 .name           = "QVGA portrait",
  67                 .refresh        = 60,
  68                 .xres           = 240,
  69                 .yres           = 320,
  70                 .pixclock       = 191828,
  71                 .left_margin    = 22,
  72                 .right_margin   = 11,
  73                 .upper_margin   = 2,
  74                 .lower_margin   = 1,
  75                 .hsync_len      = 5,
  76                 .vsync_len      = 2,
  77                 .sync           = 0,
  78                 .vmode          = FB_VMODE_NONINTERLACED,
  79         },
  80         .width          = -1,
  81         .height         = -1,
  82         .tim2           = (TIM2_IVS | TIM2_IHS),
  83         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
  84                                 CNTL_LCDBPP16_565),
  85         .bpp            = 16,
  86 };
  87 #define PANEL_SIZE (3 * SZ_64K)
  88
  89 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
  90 {
  91         dma_addr_t dma;
  92
  93         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
  94                 PANEL_SIZE, &dma, GFP_KERNEL);
  95         if (!fb->fb.screen_base) {
  96                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
  97                 return -ENOMEM;
  98         }
  99
 100         fb->fb.fix.smem_start = dma;
 101         fb->fb.fix.smem_len = PANEL_SIZE;
 102         fb->panel = &conn_lcd_panel;
 103
 104         if (gpio_request(LCD_POWER_GPIO, "LCD power"))
 105                 printk(KERN_ERR "Error requesting gpio %u",
 106                         LCD_POWER_GPIO);
 107         else if (gpio_direction_output(LCD_POWER_GPIO, 1))
 108                 printk(KERN_ERR "Error setting gpio %u to output",
 109                         LCD_POWER_GPIO);
 110
 111         if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
 112                 printk(KERN_ERR "Error requesting gpio %u",
 113                         BKL_POWER_GPIO);
 114         else if (gpio_direction_output(BKL_POWER_GPIO, 1))
 115                 printk(KERN_ERR "Error setting gpio %u to output",
 116                         BKL_POWER_GPIO);
 117
 118         return 0;
 119 }
 120
 121 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 122 {
 123         return dma_mmap_writecombine(&fb->dev->dev, vma,
 124                 fb->fb.screen_base, fb->fb.fix.smem_start,
 125                 fb->fb.fix.smem_len);
 126 }
 127
 128 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
 129 {
 130         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 131                 fb->fb.screen_base, fb->fb.fix.smem_start);
 132 }
 133
 134 /*
 135  * On some early LCD modules (1307.0), the backlight logic is inverted.
 136  * For those board variants, swap the disable and enable states for
 137  * BKL_POWER_GPIO.
 138 */
 139 static void clcd_disable(struct clcd_fb *fb)
 140 {
 141         gpio_set_value(BKL_POWER_GPIO, 0);
 142         gpio_set_value(LCD_POWER_GPIO, 0);
 143 }
 144
 145 static void clcd_enable(struct clcd_fb *fb)
 146 {
 147         gpio_set_value(BKL_POWER_GPIO, 1);
 148         gpio_set_value(LCD_POWER_GPIO, 1);
 149 }
 150
 151 static struct clcd_board lpc32xx_clcd_data = {
 152         .name           = "Phytec LCD",
 153         .check          = clcdfb_check,
 154         .decode         = clcdfb_decode,
 155         .disable        = clcd_disable,
 156         .enable         = clcd_enable,
 157         .setup          = lpc32xx_clcd_setup,
 158         .mmap           = lpc32xx_clcd_mmap,
 159         .remove         = lpc32xx_clcd_remove,
 160 };
 161
 162 /*
 163  * AMBA SSP (SPI)
 164  */
 165 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
 166         .bus_id                 = 0,
 167         .num_chipselect         = 1,
 168         .enable_dma             = 0,
 169 };
 170
 171 static struct pl022_ssp_controller lpc32xx_ssp1_data = {
 172         .bus_id                 = 1,
 173         .num_chipselect         = 1,
 174         .enable_dma             = 0,
 175 };
 176
 177 static struct pl08x_channel_data pl08x_slave_channels[] = {
 178         {
 179                 .bus_id = "nand-slc",
 180                 .min_signal = 1, /* SLC NAND Flash */
 181                 .max_signal = 1,
 182                 .periph_buses = PL08X_AHB1,
 183         },
 184         {
 185                 .bus_id = "nand-mlc",
 186                 .min_signal = 12, /* MLC NAND Flash */
 187                 .max_signal = 12,
 188                 .periph_buses = PL08X_AHB1,
 189         },
 190 };
 191
 192 /* NOTE: These will change, according to RMK */
 193 static int pl08x_get_signal(struct pl08x_dma_chan *ch)
 194 {
 195         return ch->cd->min_signal;
 196 }
 197
 198 static void pl08x_put_signal(struct pl08x_dma_chan *ch)
 199 {
 200 }
 201
 202 static struct pl08x_platform_data pl08x_pd = {
 203         .slave_channels = &pl08x_slave_channels[0],
 204         .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
 205         .get_signal = pl08x_get_signal,
 206         .put_signal = pl08x_put_signal,
 207         .lli_buses = PL08X_AHB1,
 208         .mem_buses = PL08X_AHB1,
 209 };
 210
 211 static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
 212 {
 213         /* Only on and off are supported */
 214         if (ios->power_mode == MMC_POWER_OFF)
 215                 gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
 216         else
 217                 gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
 218         return 0;
 219 }
 220
 221 static struct mmci_platform_data lpc32xx_mmci_data = {
 222         .ocr_mask       = MMC_VDD_30_31 | MMC_VDD_31_32 |
 223                           MMC_VDD_32_33 | MMC_VDD_33_34,
 224         .ios_handler    = mmc_handle_ios,
 225         .dma_filter     = NULL,
 226         /* No DMA for now since AMBA PL080 dmaengine driver only does scatter
 227          * gather, and the MMCI driver doesn't do it this way */
 228 };
 229
 230 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
 231         OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
 232         OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
 233         OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
 234         OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
 235         OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
 236                        &lpc32xx_mmci_data),
 237         { }
 238 };
 239
 240 static void __init lpc3250_machine_init(void)
 241 {
 242         u32 tmp;
 243
 244         /* Setup LCD muxing to RGB565 */
 245         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
 246                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
 247                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
 248         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
 249         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
 250
 251         /* Set up USB power */
 252         tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 253         tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
 254                 LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
 255         __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
 256
 257         /* Set up I2C pull levels */
 258         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
 259         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
 260                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
 261         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
 262
 263         lpc32xx_serial_init();
 264
 265         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
 266         tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
 267                 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
 268         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 269
 270         /* Test clock needed for UDA1380 initial init */
 271         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
 272                 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
 273                 LPC32XX_CLKPWR_TEST_CLK_SEL);
 274
 275         of_platform_populate(NULL, of_default_bus_match_table,
 276                              lpc32xx_auxdata_lookup, NULL);
 277
 278         /* Register GPIOs used on this board */
 279         if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
 280                 pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
 281         else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
 282                 pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
 283 }
 284
 285 static char const *lpc32xx_dt_compat[] __initdata = {
 286         "nxp,lpc3220",
 287         "nxp,lpc3230",
 288         "nxp,lpc3240",
 289         "nxp,lpc3250",
 290         NULL
 291 };
 292
 293 DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
 294         .atag_offset    = 0x100,
 295         .map_io         = lpc32xx_map_io,
 296         .init_irq       = lpc32xx_init_irq,
 297         .timer          = &lpc32xx_timer,
 298         .init_machine   = lpc3250_machine_init,
 299         .dt_compat      = lpc32xx_dt_compat,
 300         .restart        = lpc23xx_restart,
 301 MACHINE_END