Pileus Git - ~andy/linux/blob - arch/arm/mach-lpc32xx/phy3250.c

   1 /*
   2  * Platform support for LPC32xx SoC
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
   7  * Copyright (C) 2010 NXP Semiconductors
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/device.h>
  27 #include <linux/spi/spi.h>
  28 #include <linux/spi/eeprom.h>
  29 #include <linux/gpio.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/amba/clcd.h>
  32 #include <linux/amba/pl022.h>
  33 #include <linux/amba/pl08x.h>
  34 #include <linux/amba/mmci.h>
  35 #include <linux/of.h>
  36 #include <linux/of_address.h>
  37 #include <linux/of_irq.h>
  38 #include <linux/of_platform.h>
  39 #include <linux/clk.h>
  40
  41 #include <asm/setup.h>
  42 #include <asm/mach-types.h>
  43 #include <asm/mach/arch.h>
  44
  45 #include <mach/hardware.h>
  46 #include <mach/platform.h>
  47 #include <mach/board.h>
  48 #include <mach/gpio-lpc32xx.h>
  49 #include "common.h"
  50
  51 /*
  52  * Mapped GPIOLIB GPIOs
  53  */
  54 #define LCD_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
  55 #define BKL_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
  56 #define MMC_PWR_ENABLE_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
  57
  58 /*
  59  * AMBA LCD controller
  60  */
  61 static struct clcd_panel conn_lcd_panel = {
  62         .mode           = {
  63                 .name           = "QVGA portrait",
  64                 .refresh        = 60,
  65                 .xres           = 240,
  66                 .yres           = 320,
  67                 .pixclock       = 191828,
  68                 .left_margin    = 22,
  69                 .right_margin   = 11,
  70                 .upper_margin   = 2,
  71                 .lower_margin   = 1,
  72                 .hsync_len      = 5,
  73                 .vsync_len      = 2,
  74                 .sync           = 0,
  75                 .vmode          = FB_VMODE_NONINTERLACED,
  76         },
  77         .width          = -1,
  78         .height         = -1,
  79         .tim2           = (TIM2_IVS | TIM2_IHS),
  80         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
  81                                 CNTL_LCDBPP16_565),
  82         .bpp            = 16,
  83 };
  84 #define PANEL_SIZE (3 * SZ_64K)
  85
  86 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
  87 {
  88         dma_addr_t dma;
  89
  90         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
  91                 PANEL_SIZE, &dma, GFP_KERNEL);
  92         if (!fb->fb.screen_base) {
  93                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
  94                 return -ENOMEM;
  95         }
  96
  97         fb->fb.fix.smem_start = dma;
  98         fb->fb.fix.smem_len = PANEL_SIZE;
  99         fb->panel = &conn_lcd_panel;
 100
 101         if (gpio_request(LCD_POWER_GPIO, "LCD power"))
 102                 printk(KERN_ERR "Error requesting gpio %u",
 103                         LCD_POWER_GPIO);
 104         else if (gpio_direction_output(LCD_POWER_GPIO, 1))
 105                 printk(KERN_ERR "Error setting gpio %u to output",
 106                         LCD_POWER_GPIO);
 107
 108         if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
 109                 printk(KERN_ERR "Error requesting gpio %u",
 110                         BKL_POWER_GPIO);
 111         else if (gpio_direction_output(BKL_POWER_GPIO, 1))
 112                 printk(KERN_ERR "Error setting gpio %u to output",
 113                         BKL_POWER_GPIO);
 114
 115         return 0;
 116 }
 117
 118 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 119 {
 120         return dma_mmap_writecombine(&fb->dev->dev, vma,
 121                 fb->fb.screen_base, fb->fb.fix.smem_start,
 122                 fb->fb.fix.smem_len);
 123 }
 124
 125 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
 126 {
 127         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 128                 fb->fb.screen_base, fb->fb.fix.smem_start);
 129 }
 130
 131 /*
 132  * On some early LCD modules (1307.0), the backlight logic is inverted.
 133  * For those board variants, swap the disable and enable states for
 134  * BKL_POWER_GPIO.
 135 */
 136 static void clcd_disable(struct clcd_fb *fb)
 137 {
 138         gpio_set_value(BKL_POWER_GPIO, 0);
 139         gpio_set_value(LCD_POWER_GPIO, 0);
 140 }
 141
 142 static void clcd_enable(struct clcd_fb *fb)
 143 {
 144         gpio_set_value(BKL_POWER_GPIO, 1);
 145         gpio_set_value(LCD_POWER_GPIO, 1);
 146 }
 147
 148 static struct clcd_board lpc32xx_clcd_data = {
 149         .name           = "Phytec LCD",
 150         .check          = clcdfb_check,
 151         .decode         = clcdfb_decode,
 152         .disable        = clcd_disable,
 153         .enable         = clcd_enable,
 154         .setup          = lpc32xx_clcd_setup,
 155         .mmap           = lpc32xx_clcd_mmap,
 156         .remove         = lpc32xx_clcd_remove,
 157 };
 158
 159 /*
 160  * AMBA SSP (SPI)
 161  */
 162 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
 163         .bus_id                 = 0,
 164         .num_chipselect         = 1,
 165         .enable_dma             = 0,
 166 };
 167
 168 static struct pl022_ssp_controller lpc32xx_ssp1_data = {
 169         .bus_id                 = 1,
 170         .num_chipselect         = 1,
 171         .enable_dma             = 0,
 172 };
 173
 174 static struct pl08x_channel_data pl08x_slave_channels[] = {
 175         {
 176                 .bus_id = "nand-slc",
 177                 .min_signal = 1, /* SLC NAND Flash */
 178                 .max_signal = 1,
 179                 .periph_buses = PL08X_AHB1,
 180         },
 181         {
 182                 .bus_id = "nand-mlc",
 183                 .min_signal = 12, /* MLC NAND Flash */
 184                 .max_signal = 12,
 185                 .periph_buses = PL08X_AHB1,
 186         },
 187 };
 188
 189 static int pl08x_get_signal(const struct pl08x_channel_data *cd)
 190 {
 191         return cd->min_signal;
 192 }
 193
 194 static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
 195 {
 196 }
 197
 198 static struct pl08x_platform_data pl08x_pd = {
 199         .slave_channels = &pl08x_slave_channels[0],
 200         .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
 201         .get_signal = pl08x_get_signal,
 202         .put_signal = pl08x_put_signal,
 203         .lli_buses = PL08X_AHB1,
 204         .mem_buses = PL08X_AHB1,
 205 };
 206
 207 static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
 208 {
 209         /* Only on and off are supported */
 210         if (ios->power_mode == MMC_POWER_OFF)
 211                 gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
 212         else
 213                 gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
 214         return 0;
 215 }
 216
 217 static struct mmci_platform_data lpc32xx_mmci_data = {
 218         .ocr_mask       = MMC_VDD_30_31 | MMC_VDD_31_32 |
 219                           MMC_VDD_32_33 | MMC_VDD_33_34,
 220         .ios_handler    = mmc_handle_ios,
 221         .dma_filter     = NULL,
 222         /* No DMA for now since AMBA PL080 dmaengine driver only does scatter
 223          * gather, and the MMCI driver doesn't do it this way */
 224 };
 225
 226 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
 227         OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
 228         OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
 229         OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
 230         OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
 231         OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
 232                        &lpc32xx_mmci_data),
 233         { }
 234 };
 235
 236 static void __init lpc3250_machine_init(void)
 237 {
 238         u32 tmp;
 239
 240         /* Setup LCD muxing to RGB565 */
 241         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
 242                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
 243                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
 244         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
 245         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
 246
 247         lpc32xx_serial_init();
 248
 249         /* Test clock needed for UDA1380 initial init */
 250         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
 251                 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
 252                 LPC32XX_CLKPWR_TEST_CLK_SEL);
 253
 254         of_platform_populate(NULL, of_default_bus_match_table,
 255                              lpc32xx_auxdata_lookup, NULL);
 256
 257         /* Register GPIOs used on this board */
 258         if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
 259                 pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
 260         else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
 261                 pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
 262 }
 263
 264 static char const *lpc32xx_dt_compat[] __initdata = {
 265         "nxp,lpc3220",
 266         "nxp,lpc3230",
 267         "nxp,lpc3240",
 268         "nxp,lpc3250",
 269         NULL
 270 };
 271
 272 DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
 273         .atag_offset    = 0x100,
 274         .map_io         = lpc32xx_map_io,
 275         .init_irq       = lpc32xx_init_irq,
 276         .timer          = &lpc32xx_timer,
 277         .init_machine   = lpc3250_machine_init,
 278         .dt_compat      = lpc32xx_dt_compat,
 279         .restart        = lpc23xx_restart,
 280 MACHINE_END