Pileus Git - ~andy/linux/blob - arch/arm/mach-ixp2000/ixdp2x01.c

   1 /*
   2  * arch/arm/mach-ixp2000/ixdp2x01.c
   3  *
   4  * Code common to Intel IXDP2401 and IXDP2801 platforms
   5  *
   6  * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
   7  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   8  *
   9  * Copyright (C) 2002-2003 Intel Corp.
  10  * Copyright (C) 2003-2004 MontaVista Software, Inc.
  11  *
  12  *  This program is free software; you can redistribute  it and/or modify it
  13  *  under  the terms of  the GNU General  Public License as published by the
  14  *  Free Software Foundation;  either version 2 of the  License, or (at your
  15  *  option) any later version.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/mm.h>
  21 #include <linux/sched.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bitops.h>
  24 #include <linux/pci.h>
  25 #include <linux/ioport.h>
  26 #include <linux/delay.h>
  27 #include <linux/serial.h>
  28 #include <linux/tty.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/serial_8250.h>
  32 #include <linux/io.h>
  33
  34 #include <asm/irq.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/page.h>
  37 #include <mach/hardware.h>
  38 #include <asm/mach-types.h>
  39
  40 #include <asm/mach/pci.h>
  41 #include <asm/mach/map.h>
  42 #include <asm/mach/irq.h>
  43 #include <asm/mach/time.h>
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/flash.h>
  46
  47 /*************************************************************************
  48  * IXDP2x01 IRQ Handling
  49  *************************************************************************/
  50 static void ixdp2x01_irq_mask(struct irq_data *d)
  51 {
  52         ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
  53                                 IXP2000_BOARD_IRQ_MASK(d->irq));
  54 }
  55
  56 static void ixdp2x01_irq_unmask(struct irq_data *d)
  57 {
  58         ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
  59                                 IXP2000_BOARD_IRQ_MASK(d->irq));
  60 }
  61
  62 static u32 valid_irq_mask;
  63
  64 static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
  65 {
  66         u32 ex_interrupt;
  67         int i;
  68
  69         desc->irq_data.chip->irq_mask(&desc->irq_data);
  70
  71         ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
  72
  73         if (!ex_interrupt) {
  74                 printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
  75                 return;
  76         }
  77
  78         for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
  79                 if (ex_interrupt & (1 << i)) {
  80                         int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
  81                         generic_handle_irq(cpld_irq);
  82                 }
  83         }
  84
  85         desc->irq_data.chip->irq_unmask(&desc->irq_data);
  86 }
  87
  88 static struct irq_chip ixdp2x01_irq_chip = {
  89         .irq_mask       = ixdp2x01_irq_mask,
  90         .irq_ack        = ixdp2x01_irq_mask,
  91         .irq_unmask     = ixdp2x01_irq_unmask
  92 };
  93
  94 /*
  95  * We only do anything if we are the master NPU on the board.
  96  * The slave NPU only has the ethernet chip going directly to
  97  * the PCIB interrupt input.
  98  */
  99 void __init ixdp2x01_init_irq(void)
 100 {
 101         int irq = 0;
 102
 103         /* initialize chip specific interrupts */
 104         ixp2000_init_irq();
 105
 106         if (machine_is_ixdp2401())
 107                 valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
 108         else
 109                 valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
 110
 111         /* Mask all interrupts from CPLD, disable simulation */
 112         ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
 113         ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
 114
 115         for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
 116                 if (irq & valid_irq_mask) {
 117                         irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
 118                                                  handle_level_irq);
 119                         set_irq_flags(irq, IRQF_VALID);
 120                 } else {
 121                         set_irq_flags(irq, 0);
 122                 }
 123         }
 124
 125         /* Hook into PCI interrupts */
 126         irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
 127 }
 128
 129
 130 /*************************************************************************
 131  * IXDP2x01 memory map
 132  *************************************************************************/
 133 static struct map_desc ixdp2x01_io_desc __initdata = {
 134         .virtual        = IXDP2X01_VIRT_CPLD_BASE,
 135         .pfn            = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
 136         .length         = IXDP2X01_CPLD_REGION_SIZE,
 137         .type           = MT_DEVICE
 138 };
 139
 140 static void __init ixdp2x01_map_io(void)
 141 {
 142         ixp2000_map_io();
 143         iotable_init(&ixdp2x01_io_desc, 1);
 144 }
 145
 146
 147 /*************************************************************************
 148  * IXDP2x01 serial ports
 149  *************************************************************************/
 150 static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
 151         {
 152                 .mapbase        = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
 153                 .membase        = (char *)IXDP2X01_UART1_VIRT_BASE,
 154                 .irq            = IRQ_IXDP2X01_UART1,
 155                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 156                 .iotype         = UPIO_MEM32,
 157                 .regshift       = 2,
 158                 .uartclk        = IXDP2X01_UART_CLK,
 159         },
 160         { }
 161 };
 162
 163 static struct resource ixdp2x01_uart_resource1 = {
 164         .start          = IXDP2X01_UART1_PHYS_BASE,
 165         .end            = IXDP2X01_UART1_PHYS_BASE + 0xffff,
 166         .flags          = IORESOURCE_MEM,
 167 };
 168
 169 static struct platform_device ixdp2x01_serial_device1 = {
 170         .name           = "serial8250",
 171         .id             = PLAT8250_DEV_PLATFORM1,
 172         .dev            = {
 173                 .platform_data          = ixdp2x01_serial_port1,
 174         },
 175         .num_resources  = 1,
 176         .resource       = &ixdp2x01_uart_resource1,
 177 };
 178
 179 static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
 180         {
 181                 .mapbase        = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
 182                 .membase        = (char *)IXDP2X01_UART2_VIRT_BASE,
 183                 .irq            = IRQ_IXDP2X01_UART2,
 184                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 185                 .iotype         = UPIO_MEM32,
 186                 .regshift       = 2,
 187                 .uartclk        = IXDP2X01_UART_CLK,
 188         },
 189         { }
 190 };
 191
 192 static struct resource ixdp2x01_uart_resource2 = {
 193         .start          = IXDP2X01_UART2_PHYS_BASE,
 194         .end            = IXDP2X01_UART2_PHYS_BASE + 0xffff,
 195         .flags          = IORESOURCE_MEM,
 196 };
 197
 198 static struct platform_device ixdp2x01_serial_device2 = {
 199         .name           = "serial8250",
 200         .id             = PLAT8250_DEV_PLATFORM2,
 201         .dev            = {
 202                 .platform_data          = ixdp2x01_serial_port2,
 203         },
 204         .num_resources  = 1,
 205         .resource       = &ixdp2x01_uart_resource2,
 206 };
 207
 208 static void ixdp2x01_uart_init(void)
 209 {
 210         platform_device_register(&ixdp2x01_serial_device1);
 211         platform_device_register(&ixdp2x01_serial_device2);
 212 }
 213
 214
 215 /*************************************************************************
 216  * IXDP2x01 timer tick configuration
 217  *************************************************************************/
 218 static unsigned int ixdp2x01_clock;
 219
 220 static int __init ixdp2x01_clock_setup(char *str)
 221 {
 222         ixdp2x01_clock = simple_strtoul(str, NULL, 10);
 223
 224         return 1;
 225 }
 226
 227 __setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
 228
 229 static void __init ixdp2x01_timer_init(void)
 230 {
 231         if (!ixdp2x01_clock)
 232                 ixdp2x01_clock = 50000000;
 233
 234         ixp2000_init_time(ixdp2x01_clock);
 235 }
 236
 237 static struct sys_timer ixdp2x01_timer = {
 238         .init           = ixdp2x01_timer_init,
 239         .offset         = ixp2000_gettimeoffset,
 240 };
 241
 242 /*************************************************************************
 243  * IXDP2x01 PCI
 244  *************************************************************************/
 245 void __init ixdp2x01_pci_preinit(void)
 246 {
 247         ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
 248         ixp2000_pci_preinit();
 249         pcibios_setup("firmware");
 250 }
 251
 252 #define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
 253
 254 static int __init ixdp2x01_pci_map_irq(const struct pci_dev *dev, u8 slot,
 255         u8 pin)
 256 {
 257         u8 bus = dev->bus->number;
 258         u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
 259         struct pci_bus *tmp_bus = dev->bus;
 260
 261         /* Primary bus, no interrupts here */
 262         if (bus == 0) {
 263                 return -1;
 264         }
 265
 266         /* Lookup first leaf in bus tree */
 267         while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
 268                 tmp_bus = tmp_bus->parent;
 269         }
 270
 271         /* Select between known bridges */
 272         switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
 273         /* Device is located after first MB bridge */
 274         case 0x0008:
 275                 if (tmp_bus == dev->bus) {
 276                         /* Device is located directly after first MB bridge */
 277                         switch (devpin) {
 278                         case DEVPIN(1, 1):      /* Onboard 82546 ch 0 */
 279                                 if (machine_is_ixdp2401())
 280                                         return IRQ_IXDP2401_INTA_82546;
 281                                 return -1;
 282                         case DEVPIN(1, 2):      /* Onboard 82546 ch 1 */
 283                                 if (machine_is_ixdp2401())
 284                                         return IRQ_IXDP2401_INTB_82546;
 285                                 return -1;
 286                         case DEVPIN(0, 1):      /* PMC INTA# */
 287                                 return IRQ_IXDP2X01_SPCI_PMC_INTA;
 288                         case DEVPIN(0, 2):      /* PMC INTB# */
 289                                 return IRQ_IXDP2X01_SPCI_PMC_INTB;
 290                         case DEVPIN(0, 3):      /* PMC INTC# */
 291                                 return IRQ_IXDP2X01_SPCI_PMC_INTC;
 292                         case DEVPIN(0, 4):      /* PMC INTD# */
 293                                 return IRQ_IXDP2X01_SPCI_PMC_INTD;
 294                         }
 295                 }
 296                 break;
 297         case 0x0010:
 298                 if (tmp_bus == dev->bus) {
 299                         /* Device is located directly after second MB bridge */
 300                         /* Secondary bus of second bridge */
 301                         switch (devpin) {
 302                         case DEVPIN(0, 1):      /* DB#0 */
 303                                 return IRQ_IXDP2X01_SPCI_DB_0;
 304                         case DEVPIN(1, 1):      /* DB#1 */
 305                                 return IRQ_IXDP2X01_SPCI_DB_1;
 306                         }
 307                 } else {
 308                         /* Device is located indirectly after second MB bridge */
 309                         /* Not supported now */
 310                 }
 311                 break;
 312         }
 313
 314         return -1;
 315 }
 316
 317
 318 static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
 319 {
 320         sys->mem_offset = 0xe0000000;
 321
 322         if (machine_is_ixdp2801() || machine_is_ixdp28x5())
 323                 sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
 324
 325         return ixp2000_pci_setup(nr, sys);
 326 }
 327
 328 struct hw_pci ixdp2x01_pci __initdata = {
 329         .nr_controllers = 1,
 330         .setup          = ixdp2x01_pci_setup,
 331         .preinit        = ixdp2x01_pci_preinit,
 332         .scan           = ixp2000_pci_scan_bus,
 333         .map_irq        = ixdp2x01_pci_map_irq,
 334 };
 335
 336 int __init ixdp2x01_pci_init(void)
 337 {
 338         if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\
 339                 machine_is_ixdp28x5())
 340                 pci_common_init(&ixdp2x01_pci);
 341
 342         return 0;
 343 }
 344
 345 subsys_initcall(ixdp2x01_pci_init);
 346
 347 /*************************************************************************
 348  * IXDP2x01 Machine Initialization
 349  *************************************************************************/
 350 static struct flash_platform_data ixdp2x01_flash_platform_data = {
 351         .map_name       = "cfi_probe",
 352         .width          = 1,
 353 };
 354
 355 static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
 356 {
 357         ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
 358                 ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
 359         return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
 360 }
 361
 362 static struct ixp2000_flash_data ixdp2x01_flash_data = {
 363         .platform_data  = &ixdp2x01_flash_platform_data,
 364         .bank_setup     = ixdp2x01_flash_bank_setup
 365 };
 366
 367 static struct resource ixdp2x01_flash_resource = {
 368         .start          = 0xc4000000,
 369         .end            = 0xc4000000 + 0x01ffffff,
 370         .flags          = IORESOURCE_MEM,
 371 };
 372
 373 static struct platform_device ixdp2x01_flash = {
 374         .name           = "IXP2000-Flash",
 375         .id             = 0,
 376         .dev            = {
 377                 .platform_data = &ixdp2x01_flash_data,
 378         },
 379         .num_resources  = 1,
 380         .resource       = &ixdp2x01_flash_resource,
 381 };
 382
 383 static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
 384         .sda_pin        = IXDP2X01_GPIO_SDA,
 385         .scl_pin        = IXDP2X01_GPIO_SCL,
 386 };
 387
 388 static struct platform_device ixdp2x01_i2c_controller = {
 389         .name           = "IXP2000-I2C",
 390         .id             = 0,
 391         .dev            = {
 392                 .platform_data = &ixdp2x01_i2c_gpio_pins,
 393         },
 394         .num_resources  = 0
 395 };
 396
 397 static struct platform_device *ixdp2x01_devices[] __initdata = {
 398         &ixdp2x01_flash,
 399         &ixdp2x01_i2c_controller
 400 };
 401
 402 static void __init ixdp2x01_init_machine(void)
 403 {
 404         ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
 405                 (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
 406
 407         ixdp2x01_flash_data.nr_banks =
 408                 ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
 409
 410         platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
 411         ixp2000_uart_init();
 412         ixdp2x01_uart_init();
 413 }
 414
 415 static void ixdp2401_restart(char mode, const char *cmd)
 416 {
 417         /*
 418          * Reset flash banking register so that we are pointing at
 419          * RedBoot bank.
 420          */
 421         ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
 422                                 ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
 423                                         | IXDP2X01_CPLD_FLASH_INTERN));
 424         ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
 425
 426         ixp2000_restart(mode, cmd);
 427 }
 428
 429 static void ixdp280x_restart(char mode, const char *cmd)
 430 {
 431         /*
 432          * On IXDP2801 we need to write this magic sequence to the CPLD
 433          * to cause a complete reset of the CPU and all external devices
 434          * and move the flash bank register back to 0.
 435          */
 436         unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
 437
 438         reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
 439         ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
 440         ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
 441
 442         ixp2000_restart(mode, cmd);
 443 }
 444
 445 #ifdef CONFIG_ARCH_IXDP2401
 446 MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
 447         /* Maintainer: MontaVista Software, Inc. */
 448         .atag_offset    = 0x100,
 449         .map_io         = ixdp2x01_map_io,
 450         .init_irq       = ixdp2x01_init_irq,
 451         .timer          = &ixdp2x01_timer,
 452         .init_machine   = ixdp2x01_init_machine,
 453         .restart        = ixdp2401_restart,
 454 MACHINE_END
 455 #endif
 456
 457 #ifdef CONFIG_ARCH_IXDP2801
 458 MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
 459         /* Maintainer: MontaVista Software, Inc. */
 460         .atag_offset    = 0x100,
 461         .map_io         = ixdp2x01_map_io,
 462         .init_irq       = ixdp2x01_init_irq,
 463         .timer          = &ixdp2x01_timer,
 464         .init_machine   = ixdp2x01_init_machine,
 465         .restart        = ixdp280x_restart,
 466 MACHINE_END
 467
 468 /*
 469  * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel
 470  * changed the machine ID in the bootloader
 471  */
 472 MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
 473         /* Maintainer: MontaVista Software, Inc. */
 474         .atag_offset    = 0x100,
 475         .map_io         = ixdp2x01_map_io,
 476         .init_irq       = ixdp2x01_init_irq,
 477         .timer          = &ixdp2x01_timer,
 478         .init_machine   = ixdp2x01_init_machine,
 479         .restart        = ixdp280x_restart,
 480 MACHINE_END
 481 #endif
 482
 483