Pileus Git - ~andy/linux/blob - arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/string.h>
  17 #include <linux/device.h>
  18 #include <linux/amba/bus.h>
  19 #include <linux/amba/kmi.h>
  20 #include <linux/amba/clcd.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/io.h>
  23 #include <linux/irqchip/versatile-fpga.h>
  24 #include <linux/gfp.h>
  25 #include <linux/mtd/physmap.h>
  26 #include <linux/platform_data/clk-integrator.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/sys_soc.h>
  31
  32 #include <mach/hardware.h>
  33 #include <mach/platform.h>
  34 #include <asm/setup.h>
  35 #include <asm/mach-types.h>
  36 #include <asm/hardware/arm_timer.h>
  37 #include <asm/hardware/icst.h>
  38
  39 #include <mach/lm.h>
  40
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/irq.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/time.h>
  45
  46 #include <asm/hardware/timer-sp.h>
  47
  48 #include <plat/clcd.h>
  49 #include <plat/sched_clock.h>
  50
  51 #include "cm.h"
  52 #include "common.h"
  53
  54 /* Base address to the CP controller */
  55 static void __iomem *intcp_con_base;
  56
  57 #define INTCP_PA_FLASH_BASE             0x24000000
  58
  59 #define INTCP_PA_CLCD_BASE              0xc0000000
  60
  61 #define INTCP_FLASHPROG                 0x04
  62 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  63 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  64
  65 /*
  66  * Logical      Physical
  67  * f1300000     13000000        Counter/Timer
  68  * f1400000     14000000        Interrupt controller
  69  * f1600000     16000000        UART 0
  70  * f1700000     17000000        UART 1
  71  * f1a00000     1a000000        Debug LEDs
  72  * fc900000     c9000000        GPIO
  73  * fca00000     ca000000        SIC
  74  */
  75
  76 static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
  77         {
  78                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
  79                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
  80                 .length         = SZ_4K,
  81                 .type           = MT_DEVICE
  82         }, {
  83                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
  84                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
  85                 .length         = SZ_4K,
  86                 .type           = MT_DEVICE
  87         }, {
  88                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
  89                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
  90                 .length         = SZ_4K,
  91                 .type           = MT_DEVICE
  92         }, {
  93                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
  94                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
  95                 .length         = SZ_4K,
  96                 .type           = MT_DEVICE
  97         }, {
  98                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
  99                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
 100                 .length         = SZ_4K,
 101                 .type           = MT_DEVICE
 102         }, {
 103                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
 104                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
 105                 .length         = SZ_4K,
 106                 .type           = MT_DEVICE
 107         }
 108 };
 109
 110 static void __init intcp_map_io(void)
 111 {
 112         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 113 }
 114
 115 /*
 116  * Flash handling.
 117  */
 118 static int intcp_flash_init(struct platform_device *dev)
 119 {
 120         u32 val;
 121
 122         val = readl(intcp_con_base + INTCP_FLASHPROG);
 123         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 124         writel(val, intcp_con_base + INTCP_FLASHPROG);
 125
 126         return 0;
 127 }
 128
 129 static void intcp_flash_exit(struct platform_device *dev)
 130 {
 131         u32 val;
 132
 133         val = readl(intcp_con_base + INTCP_FLASHPROG);
 134         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 135         writel(val, intcp_con_base + INTCP_FLASHPROG);
 136 }
 137
 138 static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
 139 {
 140         u32 val;
 141
 142         val = readl(intcp_con_base + INTCP_FLASHPROG);
 143         if (on)
 144                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 145         else
 146                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 147         writel(val, intcp_con_base + INTCP_FLASHPROG);
 148 }
 149
 150 static struct physmap_flash_data intcp_flash_data = {
 151         .width          = 4,
 152         .init           = intcp_flash_init,
 153         .exit           = intcp_flash_exit,
 154         .set_vpp        = intcp_flash_set_vpp,
 155 };
 156
 157 /*
 158  * It seems that the card insertion interrupt remains active after
 159  * we've acknowledged it.  We therefore ignore the interrupt, and
 160  * rely on reading it from the SIC.  This also means that we must
 161  * clear the latched interrupt.
 162  */
 163 static unsigned int mmc_status(struct device *dev)
 164 {
 165         unsigned int status = readl(__io_address(0xca000000 + 4));
 166         writel(8, intcp_con_base + 8);
 167
 168         return status & 8;
 169 }
 170
 171 static struct mmci_platform_data mmc_data = {
 172         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 173         .status         = mmc_status,
 174         .gpio_wp        = -1,
 175         .gpio_cd        = -1,
 176 };
 177
 178 /*
 179  * CLCD support
 180  */
 181 /*
 182  * Ensure VGA is selected.
 183  */
 184 static void cp_clcd_enable(struct clcd_fb *fb)
 185 {
 186         struct fb_var_screeninfo *var = &fb->fb.var;
 187         u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
 188                         | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
 189
 190         if (var->bits_per_pixel <= 8 ||
 191             (var->bits_per_pixel == 16 && var->green.length == 5))
 192                 /* Pseudocolor, RGB555, BGR555 */
 193                 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
 194         else if (fb->fb.var.bits_per_pixel <= 16)
 195                 /* truecolor RGB565 */
 196                 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
 197         else
 198                 val = 0; /* no idea for this, don't trust the docs */
 199
 200         cm_control(CM_CTRL_LCDMUXSEL_MASK|
 201                    CM_CTRL_LCDEN0|
 202                    CM_CTRL_LCDEN1|
 203                    CM_CTRL_STATIC1|
 204                    CM_CTRL_STATIC2|
 205                    CM_CTRL_STATIC|
 206                    CM_CTRL_n24BITEN, val);
 207 }
 208
 209 static int cp_clcd_setup(struct clcd_fb *fb)
 210 {
 211         fb->panel = versatile_clcd_get_panel("VGA");
 212         if (!fb->panel)
 213                 return -EINVAL;
 214
 215         return versatile_clcd_setup_dma(fb, SZ_1M);
 216 }
 217
 218 static struct clcd_board clcd_data = {
 219         .name           = "Integrator/CP",
 220         .caps           = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
 221         .check          = clcdfb_check,
 222         .decode         = clcdfb_decode,
 223         .enable         = cp_clcd_enable,
 224         .setup          = cp_clcd_setup,
 225         .mmap           = versatile_clcd_mmap_dma,
 226         .remove         = versatile_clcd_remove_dma,
 227 };
 228
 229 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 230
 231 static void __init intcp_init_early(void)
 232 {
 233 #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
 234         versatile_sched_clock_init(REFCOUNTER, 24000000);
 235 #endif
 236 }
 237
 238 static const struct of_device_id fpga_irq_of_match[] __initconst = {
 239         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
 240         { /* Sentinel */ }
 241 };
 242
 243 static void __init intcp_init_irq_of(void)
 244 {
 245         cm_init();
 246         of_irq_init(fpga_irq_of_match);
 247         integrator_clk_init(true);
 248 }
 249
 250 /*
 251  * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
 252  * and enforce the bus names since these are used for clock lookups.
 253  */
 254 static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
 255         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
 256                 "rtc", NULL),
 257         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
 258                 "uart0", NULL),
 259         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
 260                 "uart1", NULL),
 261         OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
 262                 "kmi0", NULL),
 263         OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 264                 "kmi1", NULL),
 265         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
 266                 "mmci", &mmc_data),
 267         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
 268                 "aaci", &mmc_data),
 269         OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
 270                 "clcd", &clcd_data),
 271         OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
 272                 "physmap-flash", &intcp_flash_data),
 273         { /* sentinel */ },
 274 };
 275
 276 static const struct of_device_id intcp_syscon_match[] = {
 277         { .compatible = "arm,integrator-cp-syscon"},
 278         { },
 279 };
 280
 281 static void __init intcp_init_of(void)
 282 {
 283         struct device_node *root;
 284         struct device_node *cpcon;
 285         struct device *parent;
 286         struct soc_device *soc_dev;
 287         struct soc_device_attribute *soc_dev_attr;
 288         u32 intcp_sc_id;
 289         int err;
 290
 291         /* Here we create an SoC device for the root node */
 292         root = of_find_node_by_path("/");
 293         if (!root)
 294                 return;
 295
 296         cpcon = of_find_matching_node(root, intcp_syscon_match);
 297         if (!cpcon)
 298                 return;
 299
 300         intcp_con_base = of_iomap(cpcon, 0);
 301         if (!intcp_con_base)
 302                 return;
 303
 304         intcp_sc_id = readl(intcp_con_base);
 305
 306         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 307         if (!soc_dev_attr)
 308                 return;
 309
 310         err = of_property_read_string(root, "compatible",
 311                                       &soc_dev_attr->soc_id);
 312         if (err)
 313                 return;
 314         err = of_property_read_string(root, "model", &soc_dev_attr->machine);
 315         if (err)
 316                 return;
 317         soc_dev_attr->family = "Integrator";
 318         soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
 319                                            'A' + (intcp_sc_id & 0x0f));
 320
 321         soc_dev = soc_device_register(soc_dev_attr);
 322         if (IS_ERR(soc_dev)) {
 323                 kfree(soc_dev_attr->revision);
 324                 kfree(soc_dev_attr);
 325                 return;
 326         }
 327
 328         parent = soc_device_to_device(soc_dev);
 329         integrator_init_sysfs(parent, intcp_sc_id);
 330         of_platform_populate(root, of_default_bus_match_table,
 331                         intcp_auxdata_lookup, parent);
 332 }
 333
 334 static const char * intcp_dt_board_compat[] = {
 335         "arm,integrator-cp",
 336         NULL,
 337 };
 338
 339 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
 340         .reserve        = integrator_reserve,
 341         .map_io         = intcp_map_io,
 342         .init_early     = intcp_init_early,
 343         .init_irq       = intcp_init_irq_of,
 344         .handle_irq     = fpga_handle_irq,
 345         .init_machine   = intcp_init_of,
 346         .restart        = integrator_restart,
 347         .dt_compat      = intcp_dt_board_compat,
 348 MACHINE_END