Pileus Git - ~andy/linux/blob - arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/syscore_ops.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/kmi.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34 #include <linux/mtd/physmap.h>
  35 #include <linux/clk.h>
  36 #include <linux/platform_data/clk-integrator.h>
  37 #include <linux/of_irq.h>
  38 #include <linux/of_address.h>
  39 #include <linux/of_platform.h>
  40 #include <video/vga.h>
  41
  42 #include <mach/hardware.h>
  43 #include <mach/platform.h>
  44 #include <asm/hardware/arm_timer.h>
  45 #include <asm/setup.h>
  46 #include <asm/param.h>          /* HZ */
  47 #include <asm/mach-types.h>
  48 #include <asm/sched_clock.h>
  49
  50 #include <mach/lm.h>
  51 #include <mach/irqs.h>
  52
  53 #include <asm/mach/arch.h>
  54 #include <asm/mach/irq.h>
  55 #include <asm/mach/map.h>
  56 #include <asm/mach/pci.h>
  57 #include <asm/mach/time.h>
  58
  59 #include <plat/fpga-irq.h>
  60
  61 #include "common.h"
  62
  63 /*
  64  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  65  * is the (PA >> 12).
  66  *
  67  * Setup a VA for the Integrator interrupt controller (for header #0,
  68  * just for now).
  69  */
  70 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
  71 #define VA_SC_BASE      __io_address(INTEGRATOR_SC_BASE)
  72 #define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
  73 #define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
  74
  75 /*
  76  * Logical      Physical
  77  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  78  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  79  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
  80  * fee00000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  81  * ef000000                     Cache flush
  82  * f1000000     10000000        Core module registers
  83  * f1100000     11000000        System controller registers
  84  * f1200000     12000000        EBI registers
  85  * f1300000     13000000        Counter/Timer
  86  * f1400000     14000000        Interrupt controller
  87  * f1600000     16000000        UART 0
  88  * f1700000     17000000        UART 1
  89  * f1a00000     1a000000        Debug LEDs
  90  * f1b00000     1b000000        GPIO
  91  */
  92
  93 static struct map_desc ap_io_desc[] __initdata = {
  94         {
  95                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  96                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  97                 .length         = SZ_4K,
  98                 .type           = MT_DEVICE
  99         }, {
 100                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
 101                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
 102                 .length         = SZ_4K,
 103                 .type           = MT_DEVICE
 104         }, {
 105                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
 106                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE
 109         }, {
 110                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
 111                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
 112                 .length         = SZ_4K,
 113                 .type           = MT_DEVICE
 114         }, {
 115                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 116                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 117                 .length         = SZ_4K,
 118                 .type           = MT_DEVICE
 119         }, {
 120                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 121                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 122                 .length         = SZ_4K,
 123                 .type           = MT_DEVICE
 124         }, {
 125                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 126                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE
 129         }, {
 130                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 131                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 132                 .length         = SZ_4K,
 133                 .type           = MT_DEVICE
 134         }, {
 135                 .virtual        = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 136                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 137                 .length         = SZ_4K,
 138                 .type           = MT_DEVICE
 139         }, {
 140                 .virtual        = (unsigned long)PCI_MEMORY_VADDR,
 141                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
 142                 .length         = SZ_16M,
 143                 .type           = MT_DEVICE
 144         }, {
 145                 .virtual        = (unsigned long)PCI_CONFIG_VADDR,
 146                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 147                 .length         = SZ_16M,
 148                 .type           = MT_DEVICE
 149         }, {
 150                 .virtual        = (unsigned long)PCI_V3_VADDR,
 151                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
 152                 .length         = SZ_64K,
 153                 .type           = MT_DEVICE
 154         }
 155 };
 156
 157 static void __init ap_map_io(void)
 158 {
 159         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 160         vga_base = (unsigned long)PCI_MEMORY_VADDR;
 161         pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
 162 }
 163
 164 #ifdef CONFIG_PM
 165 static unsigned long ic_irq_enable;
 166
 167 static int irq_suspend(void)
 168 {
 169         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 170         return 0;
 171 }
 172
 173 static void irq_resume(void)
 174 {
 175         /* disable all irq sources */
 176         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 177         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 178         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 179
 180         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 181 }
 182 #else
 183 #define irq_suspend NULL
 184 #define irq_resume NULL
 185 #endif
 186
 187 static struct syscore_ops irq_syscore_ops = {
 188         .suspend        = irq_suspend,
 189         .resume         = irq_resume,
 190 };
 191
 192 static int __init irq_syscore_init(void)
 193 {
 194         register_syscore_ops(&irq_syscore_ops);
 195
 196         return 0;
 197 }
 198
 199 device_initcall(irq_syscore_init);
 200
 201 /*
 202  * Flash handling.
 203  */
 204 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 205 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 206 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 207 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 208
 209 static int ap_flash_init(struct platform_device *dev)
 210 {
 211         u32 tmp;
 212
 213         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 214
 215         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 216         writel(tmp, EBI_CSR1);
 217
 218         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 219                 writel(0xa05f, EBI_LOCK);
 220                 writel(tmp, EBI_CSR1);
 221                 writel(0, EBI_LOCK);
 222         }
 223         return 0;
 224 }
 225
 226 static void ap_flash_exit(struct platform_device *dev)
 227 {
 228         u32 tmp;
 229
 230         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 231
 232         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 233         writel(tmp, EBI_CSR1);
 234
 235         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 236                 writel(0xa05f, EBI_LOCK);
 237                 writel(tmp, EBI_CSR1);
 238                 writel(0, EBI_LOCK);
 239         }
 240 }
 241
 242 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 243 {
 244         void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
 245
 246         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 247 }
 248
 249 static struct physmap_flash_data ap_flash_data = {
 250         .width          = 4,
 251         .init           = ap_flash_init,
 252         .exit           = ap_flash_exit,
 253         .set_vpp        = ap_flash_set_vpp,
 254 };
 255
 256 /*
 257  * Where is the timer (VA)?
 258  */
 259 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
 260 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
 261 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
 262
 263 static unsigned long timer_reload;
 264
 265 static u32 notrace integrator_read_sched_clock(void)
 266 {
 267         return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 268 }
 269
 270 static void integrator_clocksource_init(unsigned long inrate,
 271                                         void __iomem *base)
 272 {
 273         u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
 274         unsigned long rate = inrate;
 275
 276         if (rate >= 1500000) {
 277                 rate /= 16;
 278                 ctrl |= TIMER_CTRL_DIV16;
 279         }
 280
 281         writel(0xffff, base + TIMER_LOAD);
 282         writel(ctrl, base + TIMER_CTRL);
 283
 284         clocksource_mmio_init(base + TIMER_VALUE, "timer2",
 285                         rate, 200, 16, clocksource_mmio_readl_down);
 286         setup_sched_clock(integrator_read_sched_clock, 16, rate);
 287 }
 288
 289 static void __iomem * clkevt_base;
 290
 291 /*
 292  * IRQ handler for the timer
 293  */
 294 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
 295 {
 296         struct clock_event_device *evt = dev_id;
 297
 298         /* clear the interrupt */
 299         writel(1, clkevt_base + TIMER_INTCLR);
 300
 301         evt->event_handler(evt);
 302
 303         return IRQ_HANDLED;
 304 }
 305
 306 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 307 {
 308         u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
 309
 310         /* Disable timer */
 311         writel(ctrl, clkevt_base + TIMER_CTRL);
 312
 313         switch (mode) {
 314         case CLOCK_EVT_MODE_PERIODIC:
 315                 /* Enable the timer and start the periodic tick */
 316                 writel(timer_reload, clkevt_base + TIMER_LOAD);
 317                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 318                 writel(ctrl, clkevt_base + TIMER_CTRL);
 319                 break;
 320         case CLOCK_EVT_MODE_ONESHOT:
 321                 /* Leave the timer disabled, .set_next_event will enable it */
 322                 ctrl &= ~TIMER_CTRL_PERIODIC;
 323                 writel(ctrl, clkevt_base + TIMER_CTRL);
 324                 break;
 325         case CLOCK_EVT_MODE_UNUSED:
 326         case CLOCK_EVT_MODE_SHUTDOWN:
 327         case CLOCK_EVT_MODE_RESUME:
 328         default:
 329                 /* Just leave in disabled state */
 330                 break;
 331         }
 332
 333 }
 334
 335 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
 336 {
 337         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 338
 339         writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 340         writel(next, clkevt_base + TIMER_LOAD);
 341         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 342
 343         return 0;
 344 }
 345
 346 static struct clock_event_device integrator_clockevent = {
 347         .name           = "timer1",
 348         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 349         .set_mode       = clkevt_set_mode,
 350         .set_next_event = clkevt_set_next_event,
 351         .rating         = 300,
 352 };
 353
 354 static struct irqaction integrator_timer_irq = {
 355         .name           = "timer",
 356         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 357         .handler        = integrator_timer_interrupt,
 358         .dev_id         = &integrator_clockevent,
 359 };
 360
 361 static void integrator_clockevent_init(unsigned long inrate,
 362                                 void __iomem *base, int irq)
 363 {
 364         unsigned long rate = inrate;
 365         unsigned int ctrl = 0;
 366
 367         clkevt_base = base;
 368         /* Calculate and program a divisor */
 369         if (rate > 0x100000 * HZ) {
 370                 rate /= 256;
 371                 ctrl |= TIMER_CTRL_DIV256;
 372         } else if (rate > 0x10000 * HZ) {
 373                 rate /= 16;
 374                 ctrl |= TIMER_CTRL_DIV16;
 375         }
 376         timer_reload = rate / HZ;
 377         writel(ctrl, clkevt_base + TIMER_CTRL);
 378
 379         setup_irq(irq, &integrator_timer_irq);
 380         clockevents_config_and_register(&integrator_clockevent,
 381                                         rate,
 382                                         1,
 383                                         0xffffU);
 384 }
 385
 386 void __init ap_init_early(void)
 387 {
 388 }
 389
 390 #ifdef CONFIG_OF
 391
 392 static void __init ap_init_timer_of(void)
 393 {
 394         struct device_node *node;
 395         const char *path;
 396         void __iomem *base;
 397         int err;
 398         int irq;
 399         struct clk *clk;
 400         unsigned long rate;
 401
 402         clk = clk_get_sys("ap_timer", NULL);
 403         BUG_ON(IS_ERR(clk));
 404         clk_prepare_enable(clk);
 405         rate = clk_get_rate(clk);
 406
 407         err = of_property_read_string(of_aliases,
 408                                 "arm,timer-primary", &path);
 409         if (WARN_ON(err))
 410                 return;
 411         node = of_find_node_by_path(path);
 412         base = of_iomap(node, 0);
 413         if (WARN_ON(!base))
 414                 return;
 415         writel(0, base + TIMER_CTRL);
 416         integrator_clocksource_init(rate, base);
 417
 418         err = of_property_read_string(of_aliases,
 419                                 "arm,timer-secondary", &path);
 420         if (WARN_ON(err))
 421                 return;
 422         node = of_find_node_by_path(path);
 423         base = of_iomap(node, 0);
 424         if (WARN_ON(!base))
 425                 return;
 426         irq = irq_of_parse_and_map(node, 0);
 427         writel(0, base + TIMER_CTRL);
 428         integrator_clockevent_init(rate, base, irq);
 429 }
 430
 431 static struct sys_timer ap_of_timer = {
 432         .init           = ap_init_timer_of,
 433 };
 434
 435 static const struct of_device_id fpga_irq_of_match[] __initconst = {
 436         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
 437         { /* Sentinel */ }
 438 };
 439
 440 static void __init ap_init_irq_of(void)
 441 {
 442         /* disable core module IRQs */
 443         writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 444         of_irq_init(fpga_irq_of_match);
 445         integrator_clk_init(false);
 446 }
 447
 448 /* For the Device Tree, add in the UART callbacks as AUXDATA */
 449 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
 450         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
 451                 "rtc", NULL),
 452         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
 453                 "uart0", &integrator_uart_data),
 454         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
 455                 "uart1", &integrator_uart_data),
 456         OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
 457                 "kmi0", NULL),
 458         OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 459                 "kmi1", NULL),
 460         OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
 461                 "physmap-flash", &ap_flash_data),
 462         { /* sentinel */ },
 463 };
 464
 465 static void __init ap_init_of(void)
 466 {
 467         unsigned long sc_dec;
 468         int i;
 469
 470         of_platform_populate(NULL, of_default_bus_match_table,
 471                         ap_auxdata_lookup, NULL);
 472
 473         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 474         for (i = 0; i < 4; i++) {
 475                 struct lm_device *lmdev;
 476
 477                 if ((sc_dec & (16 << i)) == 0)
 478                         continue;
 479
 480                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 481                 if (!lmdev)
 482                         continue;
 483
 484                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 485                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 486                 lmdev->resource.flags = IORESOURCE_MEM;
 487                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 488                 lmdev->id = i;
 489
 490                 lm_device_register(lmdev);
 491         }
 492 }
 493
 494 static const char * ap_dt_board_compat[] = {
 495         "arm,integrator-ap",
 496         NULL,
 497 };
 498
 499 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
 500         .reserve        = integrator_reserve,
 501         .map_io         = ap_map_io,
 502         .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
 503         .init_early     = ap_init_early,
 504         .init_irq       = ap_init_irq_of,
 505         .handle_irq     = fpga_handle_irq,
 506         .timer          = &ap_of_timer,
 507         .init_machine   = ap_init_of,
 508         .restart        = integrator_restart,
 509         .dt_compat      = ap_dt_board_compat,
 510 MACHINE_END
 511
 512 #endif
 513
 514 #ifdef CONFIG_ATAGS
 515
 516 /*
 517  * This is where non-devicetree initialization code is collected and stashed
 518  * for eventual deletion.
 519  */
 520
 521 static struct resource cfi_flash_resource = {
 522         .start          = INTEGRATOR_FLASH_BASE,
 523         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 524         .flags          = IORESOURCE_MEM,
 525 };
 526
 527 static struct platform_device cfi_flash_device = {
 528         .name           = "physmap-flash",
 529         .id             = 0,
 530         .dev            = {
 531                 .platform_data  = &ap_flash_data,
 532         },
 533         .num_resources  = 1,
 534         .resource       = &cfi_flash_resource,
 535 };
 536
 537 static void __init ap_init_timer(void)
 538 {
 539         struct clk *clk;
 540         unsigned long rate;
 541
 542         clk = clk_get_sys("ap_timer", NULL);
 543         BUG_ON(IS_ERR(clk));
 544         clk_prepare_enable(clk);
 545         rate = clk_get_rate(clk);
 546
 547         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 548         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 549         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 550
 551         integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
 552         integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
 553                                 IRQ_TIMERINT1);
 554 }
 555
 556 static struct sys_timer ap_timer = {
 557         .init           = ap_init_timer,
 558 };
 559
 560 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 561
 562 static void __init ap_init_irq(void)
 563 {
 564         /* Disable all interrupts initially. */
 565         /* Do the core module ones */
 566         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 567
 568         /* do the header card stuff next */
 569         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 570         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 571
 572         fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
 573                 -1, INTEGRATOR_SC_VALID_INT, NULL);
 574         integrator_clk_init(false);
 575 }
 576
 577 static void __init ap_init(void)
 578 {
 579         unsigned long sc_dec;
 580         int i;
 581
 582         platform_device_register(&cfi_flash_device);
 583
 584         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 585         for (i = 0; i < 4; i++) {
 586                 struct lm_device *lmdev;
 587
 588                 if ((sc_dec & (16 << i)) == 0)
 589                         continue;
 590
 591                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 592                 if (!lmdev)
 593                         continue;
 594
 595                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 596                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 597                 lmdev->resource.flags = IORESOURCE_MEM;
 598                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 599                 lmdev->id = i;
 600
 601                 lm_device_register(lmdev);
 602         }
 603
 604         integrator_init(false);
 605 }
 606
 607 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 608         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 609         .atag_offset    = 0x100,
 610         .reserve        = integrator_reserve,
 611         .map_io         = ap_map_io,
 612         .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
 613         .init_early     = ap_init_early,
 614         .init_irq       = ap_init_irq,
 615         .handle_irq     = fpga_handle_irq,
 616         .timer          = &ap_timer,
 617         .init_machine   = ap_init,
 618         .restart        = integrator_restart,
 619 MACHINE_END
 620
 621 #endif