Pileus Git - ~andy/linux/blob - arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/syscore_ops.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/kmi.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34 #include <linux/mtd/physmap.h>
  35 #include <linux/clk.h>
  36 #include <video/vga.h>
  37
  38 #include <mach/hardware.h>
  39 #include <mach/platform.h>
  40 #include <asm/hardware/arm_timer.h>
  41 #include <asm/setup.h>
  42 #include <asm/param.h>          /* HZ */
  43 #include <asm/mach-types.h>
  44 #include <asm/sched_clock.h>
  45
  46 #include <mach/lm.h>
  47 #include <mach/irqs.h>
  48
  49 #include <asm/mach/arch.h>
  50 #include <asm/mach/irq.h>
  51 #include <asm/mach/map.h>
  52 #include <asm/mach/time.h>
  53
  54 #include <plat/fpga-irq.h>
  55
  56 #include "common.h"
  57
  58 /*
  59  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  60  * is the (PA >> 12).
  61  *
  62  * Setup a VA for the Integrator interrupt controller (for header #0,
  63  * just for now).
  64  */
  65 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
  66 #define VA_SC_BASE      __io_address(INTEGRATOR_SC_BASE)
  67 #define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
  68 #define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
  69
  70 /*
  71  * Logical      Physical
  72  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  73  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  74  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
  75  * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  76  * ef000000                     Cache flush
  77  * f1000000     10000000        Core module registers
  78  * f1100000     11000000        System controller registers
  79  * f1200000     12000000        EBI registers
  80  * f1300000     13000000        Counter/Timer
  81  * f1400000     14000000        Interrupt controller
  82  * f1600000     16000000        UART 0
  83  * f1700000     17000000        UART 1
  84  * f1a00000     1a000000        Debug LEDs
  85  * f1b00000     1b000000        GPIO
  86  */
  87
  88 static struct map_desc ap_io_desc[] __initdata = {
  89         {
  90                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  91                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  92                 .length         = SZ_4K,
  93                 .type           = MT_DEVICE
  94         }, {
  95                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  96                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  97                 .length         = SZ_4K,
  98                 .type           = MT_DEVICE
  99         }, {
 100                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
 101                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
 102                 .length         = SZ_4K,
 103                 .type           = MT_DEVICE
 104         }, {
 105                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
 106                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE
 109         }, {
 110                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 111                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 112                 .length         = SZ_4K,
 113                 .type           = MT_DEVICE
 114         }, {
 115                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 116                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 117                 .length         = SZ_4K,
 118                 .type           = MT_DEVICE
 119         }, {
 120                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 121                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 122                 .length         = SZ_4K,
 123                 .type           = MT_DEVICE
 124         }, {
 125                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 126                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE
 129         }, {
 130                 .virtual        = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 131                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 132                 .length         = SZ_4K,
 133                 .type           = MT_DEVICE
 134         }, {
 135                 .virtual        = PCI_MEMORY_VADDR,
 136                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
 137                 .length         = SZ_16M,
 138                 .type           = MT_DEVICE
 139         }, {
 140                 .virtual        = PCI_CONFIG_VADDR,
 141                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 142                 .length         = SZ_16M,
 143                 .type           = MT_DEVICE
 144         }, {
 145                 .virtual        = PCI_V3_VADDR,
 146                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
 147                 .length         = SZ_64K,
 148                 .type           = MT_DEVICE
 149         }, {
 150                 .virtual        = PCI_IO_VADDR,
 151                 .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
 152                 .length         = SZ_64K,
 153                 .type           = MT_DEVICE
 154         }
 155 };
 156
 157 static void __init ap_map_io(void)
 158 {
 159         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 160         vga_base = PCI_MEMORY_VADDR;
 161 }
 162
 163 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 164
 165 static struct fpga_irq_data sc_irq_data = {
 166         .base           = VA_IC_BASE,
 167         .irq_start      = 0,
 168         .chip.name      = "SC",
 169 };
 170
 171 static void __init ap_init_irq(void)
 172 {
 173         /* Disable all interrupts initially. */
 174         /* Do the core module ones */
 175         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 176
 177         /* do the header card stuff next */
 178         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 179         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 180
 181         fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
 182 }
 183
 184 #ifdef CONFIG_PM
 185 static unsigned long ic_irq_enable;
 186
 187 static int irq_suspend(void)
 188 {
 189         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 190         return 0;
 191 }
 192
 193 static void irq_resume(void)
 194 {
 195         /* disable all irq sources */
 196         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 197         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 198         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 199
 200         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 201 }
 202 #else
 203 #define irq_suspend NULL
 204 #define irq_resume NULL
 205 #endif
 206
 207 static struct syscore_ops irq_syscore_ops = {
 208         .suspend        = irq_suspend,
 209         .resume         = irq_resume,
 210 };
 211
 212 static int __init irq_syscore_init(void)
 213 {
 214         register_syscore_ops(&irq_syscore_ops);
 215
 216         return 0;
 217 }
 218
 219 device_initcall(irq_syscore_init);
 220
 221 /*
 222  * Flash handling.
 223  */
 224 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 225 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 226 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 227 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 228
 229 static int ap_flash_init(struct platform_device *dev)
 230 {
 231         u32 tmp;
 232
 233         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 234
 235         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 236         writel(tmp, EBI_CSR1);
 237
 238         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 239                 writel(0xa05f, EBI_LOCK);
 240                 writel(tmp, EBI_CSR1);
 241                 writel(0, EBI_LOCK);
 242         }
 243         return 0;
 244 }
 245
 246 static void ap_flash_exit(struct platform_device *dev)
 247 {
 248         u32 tmp;
 249
 250         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 251
 252         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 253         writel(tmp, EBI_CSR1);
 254
 255         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 256                 writel(0xa05f, EBI_LOCK);
 257                 writel(tmp, EBI_CSR1);
 258                 writel(0, EBI_LOCK);
 259         }
 260 }
 261
 262 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 263 {
 264         void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
 265
 266         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 267 }
 268
 269 static struct physmap_flash_data ap_flash_data = {
 270         .width          = 4,
 271         .init           = ap_flash_init,
 272         .exit           = ap_flash_exit,
 273         .set_vpp        = ap_flash_set_vpp,
 274 };
 275
 276 static struct resource cfi_flash_resource = {
 277         .start          = INTEGRATOR_FLASH_BASE,
 278         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 279         .flags          = IORESOURCE_MEM,
 280 };
 281
 282 static struct platform_device cfi_flash_device = {
 283         .name           = "physmap-flash",
 284         .id             = 0,
 285         .dev            = {
 286                 .platform_data  = &ap_flash_data,
 287         },
 288         .num_resources  = 1,
 289         .resource       = &cfi_flash_resource,
 290 };
 291
 292 static void __init ap_init(void)
 293 {
 294         unsigned long sc_dec;
 295         int i;
 296
 297         platform_device_register(&cfi_flash_device);
 298
 299         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 300         for (i = 0; i < 4; i++) {
 301                 struct lm_device *lmdev;
 302
 303                 if ((sc_dec & (16 << i)) == 0)
 304                         continue;
 305
 306                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 307                 if (!lmdev)
 308                         continue;
 309
 310                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 311                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 312                 lmdev->resource.flags = IORESOURCE_MEM;
 313                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 314                 lmdev->id = i;
 315
 316                 lm_device_register(lmdev);
 317         }
 318 }
 319
 320 /*
 321  * Where is the timer (VA)?
 322  */
 323 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
 324 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
 325 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
 326
 327 static unsigned long timer_reload;
 328
 329 static u32 notrace integrator_read_sched_clock(void)
 330 {
 331         return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 332 }
 333
 334 static void integrator_clocksource_init(unsigned long inrate)
 335 {
 336         void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
 337         u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
 338         unsigned long rate = inrate;
 339
 340         if (rate >= 1500000) {
 341                 rate /= 16;
 342                 ctrl |= TIMER_CTRL_DIV16;
 343         }
 344
 345         writel(0xffff, base + TIMER_LOAD);
 346         writel(ctrl, base + TIMER_CTRL);
 347
 348         clocksource_mmio_init(base + TIMER_VALUE, "timer2",
 349                         rate, 200, 16, clocksource_mmio_readl_down);
 350         setup_sched_clock(integrator_read_sched_clock, 16, rate);
 351 }
 352
 353 static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
 354
 355 /*
 356  * IRQ handler for the timer
 357  */
 358 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
 359 {
 360         struct clock_event_device *evt = dev_id;
 361
 362         /* clear the interrupt */
 363         writel(1, clkevt_base + TIMER_INTCLR);
 364
 365         evt->event_handler(evt);
 366
 367         return IRQ_HANDLED;
 368 }
 369
 370 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 371 {
 372         u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
 373
 374         /* Disable timer */
 375         writel(ctrl, clkevt_base + TIMER_CTRL);
 376
 377         switch (mode) {
 378         case CLOCK_EVT_MODE_PERIODIC:
 379                 /* Enable the timer and start the periodic tick */
 380                 writel(timer_reload, clkevt_base + TIMER_LOAD);
 381                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 382                 writel(ctrl, clkevt_base + TIMER_CTRL);
 383                 break;
 384         case CLOCK_EVT_MODE_ONESHOT:
 385                 /* Leave the timer disabled, .set_next_event will enable it */
 386                 ctrl &= ~TIMER_CTRL_PERIODIC;
 387                 writel(ctrl, clkevt_base + TIMER_CTRL);
 388                 break;
 389         case CLOCK_EVT_MODE_UNUSED:
 390         case CLOCK_EVT_MODE_SHUTDOWN:
 391         case CLOCK_EVT_MODE_RESUME:
 392         default:
 393                 /* Just leave in disabled state */
 394                 break;
 395         }
 396
 397 }
 398
 399 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
 400 {
 401         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 402
 403         writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 404         writel(next, clkevt_base + TIMER_LOAD);
 405         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 406
 407         return 0;
 408 }
 409
 410 static struct clock_event_device integrator_clockevent = {
 411         .name           = "timer1",
 412         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 413         .set_mode       = clkevt_set_mode,
 414         .set_next_event = clkevt_set_next_event,
 415         .rating         = 300,
 416 };
 417
 418 static struct irqaction integrator_timer_irq = {
 419         .name           = "timer",
 420         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 421         .handler        = integrator_timer_interrupt,
 422         .dev_id         = &integrator_clockevent,
 423 };
 424
 425 static void integrator_clockevent_init(unsigned long inrate)
 426 {
 427         unsigned long rate = inrate;
 428         unsigned int ctrl = 0;
 429
 430         /* Calculate and program a divisor */
 431         if (rate > 0x100000 * HZ) {
 432                 rate /= 256;
 433                 ctrl |= TIMER_CTRL_DIV256;
 434         } else if (rate > 0x10000 * HZ) {
 435                 rate /= 16;
 436                 ctrl |= TIMER_CTRL_DIV16;
 437         }
 438         timer_reload = rate / HZ;
 439         writel(ctrl, clkevt_base + TIMER_CTRL);
 440
 441         setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
 442         clockevents_config_and_register(&integrator_clockevent,
 443                                         rate,
 444                                         1,
 445                                         0xffffU);
 446 }
 447
 448 /*
 449  * Set up timer(s).
 450  */
 451 static void __init ap_init_timer(void)
 452 {
 453         struct clk *clk;
 454         unsigned long rate;
 455
 456         clk = clk_get_sys("ap_timer", NULL);
 457         BUG_ON(IS_ERR(clk));
 458         clk_enable(clk);
 459         rate = clk_get_rate(clk);
 460
 461         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 462         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 463         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 464
 465         integrator_clocksource_init(rate);
 466         integrator_clockevent_init(rate);
 467 }
 468
 469 static struct sys_timer ap_timer = {
 470         .init           = ap_init_timer,
 471 };
 472
 473 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 474         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 475         .atag_offset    = 0x100,
 476         .reserve        = integrator_reserve,
 477         .map_io         = ap_map_io,
 478         .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
 479         .init_early     = integrator_init_early,
 480         .init_irq       = ap_init_irq,
 481         .timer          = &ap_timer,
 482         .init_machine   = ap_init,
 483         .restart        = integrator_restart,
 484 MACHINE_END