Pileus Git - ~andy/linux/blob - arch/arm/mach-integrator/core.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/core.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/device.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/memblock.h>
  18 #include <linux/sched.h>
  19 #include <linux/smp.h>
  20 #include <linux/termios.h>
  21 #include <linux/amba/bus.h>
  22 #include <linux/amba/serial.h>
  23 #include <linux/io.h>
  24 #include <linux/clkdev.h>
  25
  26 #include <mach/hardware.h>
  27 #include <mach/platform.h>
  28 #include <mach/cm.h>
  29 #include <mach/irqs.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/leds.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/mach/time.h>
  35 #include <asm/pgtable.h>
  36
  37 static struct amba_pl010_data integrator_uart_data;
  38
  39 static struct amba_device rtc_device = {
  40         .dev            = {
  41                 .init_name = "mb:15",
  42         },
  43         .res            = {
  44                 .start  = INTEGRATOR_RTC_BASE,
  45                 .end    = INTEGRATOR_RTC_BASE + SZ_4K - 1,
  46                 .flags  = IORESOURCE_MEM,
  47         },
  48         .irq            = { IRQ_RTCINT, NO_IRQ },
  49 };
  50
  51 static struct amba_device uart0_device = {
  52         .dev            = {
  53                 .init_name = "mb:16",
  54                 .platform_data = &integrator_uart_data,
  55         },
  56         .res            = {
  57                 .start  = INTEGRATOR_UART0_BASE,
  58                 .end    = INTEGRATOR_UART0_BASE + SZ_4K - 1,
  59                 .flags  = IORESOURCE_MEM,
  60         },
  61         .irq            = { IRQ_UARTINT0, NO_IRQ },
  62 };
  63
  64 static struct amba_device uart1_device = {
  65         .dev            = {
  66                 .init_name = "mb:17",
  67                 .platform_data = &integrator_uart_data,
  68         },
  69         .res            = {
  70                 .start  = INTEGRATOR_UART1_BASE,
  71                 .end    = INTEGRATOR_UART1_BASE + SZ_4K - 1,
  72                 .flags  = IORESOURCE_MEM,
  73         },
  74         .irq            = { IRQ_UARTINT1, NO_IRQ },
  75 };
  76
  77 static struct amba_device kmi0_device = {
  78         .dev            = {
  79                 .init_name = "mb:18",
  80         },
  81         .res            = {
  82                 .start  = KMI0_BASE,
  83                 .end    = KMI0_BASE + SZ_4K - 1,
  84                 .flags  = IORESOURCE_MEM,
  85         },
  86         .irq            = { IRQ_KMIINT0, NO_IRQ },
  87 };
  88
  89 static struct amba_device kmi1_device = {
  90         .dev            = {
  91                 .init_name = "mb:19",
  92         },
  93         .res            = {
  94                 .start  = KMI1_BASE,
  95                 .end    = KMI1_BASE + SZ_4K - 1,
  96                 .flags  = IORESOURCE_MEM,
  97         },
  98         .irq            = { IRQ_KMIINT1, NO_IRQ },
  99 };
 100
 101 static struct amba_device *amba_devs[] __initdata = {
 102         &rtc_device,
 103         &uart0_device,
 104         &uart1_device,
 105         &kmi0_device,
 106         &kmi1_device,
 107 };
 108
 109 /*
 110  * These are fixed clocks.
 111  */
 112 static struct clk clk24mhz = {
 113         .rate   = 24000000,
 114 };
 115
 116 static struct clk uartclk = {
 117         .rate   = 14745600,
 118 };
 119
 120 static struct clk dummy_apb_pclk;
 121
 122 static struct clk_lookup lookups[] = {
 123         {       /* Bus clock */
 124                 .con_id         = "apb_pclk",
 125                 .clk            = &dummy_apb_pclk,
 126         }, {
 127                 /* Integrator/AP timer frequency */
 128                 .dev_id         = "ap_timer",
 129                 .clk            = &clk24mhz,
 130         }, {    /* UART0 */
 131                 .dev_id         = "mb:16",
 132                 .clk            = &uartclk,
 133         }, {    /* UART1 */
 134                 .dev_id         = "mb:17",
 135                 .clk            = &uartclk,
 136         }, {    /* KMI0 */
 137                 .dev_id         = "mb:18",
 138                 .clk            = &clk24mhz,
 139         }, {    /* KMI1 */
 140                 .dev_id         = "mb:19",
 141                 .clk            = &clk24mhz,
 142         }, {    /* MMCI - IntegratorCP */
 143                 .dev_id         = "mb:1c",
 144                 .clk            = &uartclk,
 145         }
 146 };
 147
 148 void __init integrator_init_early(void)
 149 {
 150         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 151 }
 152
 153 static int __init integrator_init(void)
 154 {
 155         int i;
 156
 157         /*
 158          * The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to
 159          * hard-code them. The Integator/CP and forward have proper cell IDs.
 160          * Else we leave them undefined to the bus driver can autoprobe them.
 161          */
 162         if (machine_is_integrator()) {
 163                 rtc_device.periphid     = 0x00041030;
 164                 uart0_device.periphid   = 0x00041010;
 165                 uart1_device.periphid   = 0x00041010;
 166                 kmi0_device.periphid    = 0x00041050;
 167                 kmi1_device.periphid    = 0x00041050;
 168         }
 169
 170         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 171                 struct amba_device *d = amba_devs[i];
 172                 amba_device_register(d, &iomem_resource);
 173         }
 174
 175         return 0;
 176 }
 177
 178 arch_initcall(integrator_init);
 179
 180 /*
 181  * On the Integrator platform, the port RTS and DTR are provided by
 182  * bits in the following SC_CTRLS register bits:
 183  *        RTS  DTR
 184  *  UART0  7    6
 185  *  UART1  5    4
 186  */
 187 #define SC_CTRLC        IO_ADDRESS(INTEGRATOR_SC_CTRLC)
 188 #define SC_CTRLS        IO_ADDRESS(INTEGRATOR_SC_CTRLS)
 189
 190 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 191 {
 192         unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
 193
 194         if (dev == &uart0_device) {
 195                 rts_mask = 1 << 4;
 196                 dtr_mask = 1 << 5;
 197         } else {
 198                 rts_mask = 1 << 6;
 199                 dtr_mask = 1 << 7;
 200         }
 201
 202         if (mctrl & TIOCM_RTS)
 203                 ctrlc |= rts_mask;
 204         else
 205                 ctrls |= rts_mask;
 206
 207         if (mctrl & TIOCM_DTR)
 208                 ctrlc |= dtr_mask;
 209         else
 210                 ctrls |= dtr_mask;
 211
 212         __raw_writel(ctrls, SC_CTRLS);
 213         __raw_writel(ctrlc, SC_CTRLC);
 214 }
 215
 216 static struct amba_pl010_data integrator_uart_data = {
 217         .set_mctrl = integrator_uart_set_mctrl,
 218 };
 219
 220 #define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
 221
 222 static DEFINE_RAW_SPINLOCK(cm_lock);
 223
 224 /**
 225  * cm_control - update the CM_CTRL register.
 226  * @mask: bits to change
 227  * @set: bits to set
 228  */
 229 void cm_control(u32 mask, u32 set)
 230 {
 231         unsigned long flags;
 232         u32 val;
 233
 234         raw_spin_lock_irqsave(&cm_lock, flags);
 235         val = readl(CM_CTRL) & ~mask;
 236         writel(val | set, CM_CTRL);
 237         raw_spin_unlock_irqrestore(&cm_lock, flags);
 238 }
 239
 240 EXPORT_SYMBOL(cm_control);
 241
 242 /*
 243  * We need to stop things allocating the low memory; ideally we need a
 244  * better implementation of GFP_DMA which does not assume that DMA-able
 245  * memory starts at zero.
 246  */
 247 void __init integrator_reserve(void)
 248 {
 249         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 250 }
 251
 252 /*
 253  * To reset, we hit the on-board reset register in the system FPGA
 254  */
 255 void integrator_restart(char mode, const char *cmd)
 256 {
 257         cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 258 }