2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
23 #include <asm/pgtable.h>
24 #include <asm/hardware/cache-l2x0.h>
25 #include <asm/mach/map.h>
27 #include <mach/common.h>
28 #include <mach/devices-common.h>
29 #include <mach/hardware.h>
30 #include <mach/iomux-v3.h>
31 #include <mach/irqs.h>
33 void imx3_init_l2x0(void)
35 void __iomem *l2x0_base;
36 void __iomem *clkctl_base;
39 * First of all, we must repair broken chip settings. There are some
40 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
41 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
42 * Workaraound is to setup the correct register setting prior enabling the
43 * L2 cache. This should not hurt already working CPUs, as they are using the
46 #define L2_MEM_VAL 0x10
48 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
49 if (clkctl_base != NULL) {
50 writel(0x00000515, clkctl_base + L2_MEM_VAL);
53 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
56 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
57 if (IS_ERR(l2x0_base)) {
58 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
63 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
66 static struct map_desc mx31_io_desc[] __initdata = {
67 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
68 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
69 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
70 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
71 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
75 * This function initializes the memory map. It is called during the
76 * system startup to create static physical to virtual memory mappings
79 void __init mx31_map_io(void)
81 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
84 static struct map_desc mx35_io_desc[] __initdata = {
85 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
86 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
87 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
88 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
89 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
92 void __init mx35_map_io(void)
94 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
97 void __init imx31_init_early(void)
99 mxc_set_cpu_type(MXC_CPU_MX31);
100 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
103 void __init imx35_init_early(void)
105 mxc_set_cpu_type(MXC_CPU_MX35);
106 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
107 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
110 void __init mx31_init_irq(void)
112 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
115 void __init mx35_init_irq(void)
117 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
120 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
121 .per_2_per_addr = 1677,
124 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
127 .bp_2_ap_addr = 1029,
130 static struct sdma_platform_data imx31_sdma_pdata __initdata = {
131 .fw_name = "sdma-imx31-to2.bin",
132 .script_addrs = &imx31_to2_sdma_script,
135 void __init imx31_soc_init(void)
137 int to_version = mx31_revision() >> 4;
141 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
142 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
143 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
145 if (to_version == 1) {
146 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
147 strlen(imx31_sdma_pdata.fw_name));
148 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
151 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
154 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
156 .uart_2_mcu_addr = 817,
157 .mcu_2_app_addr = 747,
158 .uartsh_2_mcu_addr = 1183,
159 .per_2_shp_addr = 1033,
160 .mcu_2_shp_addr = 961,
161 .ata_2_mcu_addr = 1333,
162 .mcu_2_ata_addr = 1252,
163 .app_2_mcu_addr = 683,
164 .shp_2_per_addr = 1111,
165 .shp_2_mcu_addr = 892,
168 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
170 .uart_2_mcu_addr = 904,
171 .per_2_app_addr = 1597,
172 .mcu_2_app_addr = 834,
173 .uartsh_2_mcu_addr = 1270,
174 .per_2_shp_addr = 1120,
175 .mcu_2_shp_addr = 1048,
176 .ata_2_mcu_addr = 1429,
177 .mcu_2_ata_addr = 1339,
178 .app_2_per_addr = 1531,
179 .app_2_mcu_addr = 770,
180 .shp_2_per_addr = 1198,
181 .shp_2_mcu_addr = 979,
184 static struct sdma_platform_data imx35_sdma_pdata __initdata = {
185 .fw_name = "sdma-imx35-to2.bin",
186 .script_addrs = &imx35_to2_sdma_script,
189 void __init imx35_soc_init(void)
191 int to_version = mx35_revision() >> 4;
195 /* i.mx35 has the i.mx31 type gpio */
196 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
197 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
198 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
200 if (to_version == 1) {
201 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
202 strlen(imx35_sdma_pdata.fw_name));
203 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
206 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);