Pileus Git - ~andy/linux/blob - arch/arm/mach-imx/devices/platform-ahci-imx.c

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/clk.h>
  23 #include <linux/err.h>
  24 #include <linux/device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <asm/sizes.h>
  27
  28 #include "../hardware.h"
  29 #include "devices-common.h"
  30
  31 #define imx_ahci_imx_data_entry_single(soc, _devid)             \
  32         {                                                               \
  33                 .devid = _devid,                                        \
  34                 .iobase = soc ## _SATA_BASE_ADDR,                       \
  35                 .irq = soc ## _INT_SATA,                                \
  36         }
  37
  38 #ifdef CONFIG_SOC_IMX53
  39 const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
  40         imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
  41 #endif
  42
  43 enum {
  44         HOST_CAP = 0x00,
  45         HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
  46         HOST_PORTS_IMPL = 0x0c,
  47         HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
  48 };
  49
  50 static struct clk *sata_clk, *sata_ref_clk;
  51
  52 /* AHCI module Initialization, if return 0, initialization is successful. */
  53 static int imx_sata_init(struct device *dev, void __iomem *addr)
  54 {
  55         u32 tmpdata;
  56         int ret = 0;
  57         struct clk *clk;
  58
  59         sata_clk = clk_get(dev, "ahci");
  60         if (IS_ERR(sata_clk)) {
  61                 dev_err(dev, "no sata clock.\n");
  62                 return PTR_ERR(sata_clk);
  63         }
  64         ret = clk_prepare_enable(sata_clk);
  65         if (ret) {
  66                 dev_err(dev, "can't prepare/enable sata clock.\n");
  67                 goto put_sata_clk;
  68         }
  69
  70         /* Get the AHCI SATA PHY CLK */
  71         sata_ref_clk = clk_get(dev, "ahci_phy");
  72         if (IS_ERR(sata_ref_clk)) {
  73                 dev_err(dev, "no sata ref clock.\n");
  74                 ret = PTR_ERR(sata_ref_clk);
  75                 goto release_sata_clk;
  76         }
  77         ret = clk_prepare_enable(sata_ref_clk);
  78         if (ret) {
  79                 dev_err(dev, "can't prepare/enable sata ref clock.\n");
  80                 goto put_sata_ref_clk;
  81         }
  82
  83         /* Get the AHB clock rate, and configure the TIMER1MS reg later */
  84         clk = clk_get(dev, "ahci_dma");
  85         if (IS_ERR(clk)) {
  86                 dev_err(dev, "no dma clock.\n");
  87                 ret = PTR_ERR(clk);
  88                 goto release_sata_ref_clk;
  89         }
  90         tmpdata = clk_get_rate(clk) / 1000;
  91         clk_put(clk);
  92
  93         writel(tmpdata, addr + HOST_TIMER1MS);
  94
  95         tmpdata = readl(addr + HOST_CAP);
  96         if (!(tmpdata & HOST_CAP_SSS)) {
  97                 tmpdata |= HOST_CAP_SSS;
  98                 writel(tmpdata, addr + HOST_CAP);
  99         }
 100
 101         if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
 102                 writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
 103                         addr + HOST_PORTS_IMPL);
 104
 105         return 0;
 106
 107 release_sata_ref_clk:
 108         clk_disable_unprepare(sata_ref_clk);
 109 put_sata_ref_clk:
 110         clk_put(sata_ref_clk);
 111 release_sata_clk:
 112         clk_disable_unprepare(sata_clk);
 113 put_sata_clk:
 114         clk_put(sata_clk);
 115
 116         return ret;
 117 }
 118
 119 static void imx_sata_exit(struct device *dev)
 120 {
 121         clk_disable_unprepare(sata_ref_clk);
 122         clk_put(sata_ref_clk);
 123
 124         clk_disable_unprepare(sata_clk);
 125         clk_put(sata_clk);
 126
 127 }
 128 struct platform_device *__init imx_add_ahci_imx(
 129                 const struct imx_ahci_imx_data *data,
 130                 const struct ahci_platform_data *pdata)
 131 {
 132         struct resource res[] = {
 133                 {
 134                         .start = data->iobase,
 135                         .end = data->iobase + SZ_4K - 1,
 136                         .flags = IORESOURCE_MEM,
 137                 }, {
 138                         .start = data->irq,
 139                         .end = data->irq,
 140                         .flags = IORESOURCE_IRQ,
 141                 },
 142         };
 143
 144         return imx_add_platform_device_dmamask(data->devid, 0,
 145                         res, ARRAY_SIZE(res),
 146                         pdata, sizeof(*pdata),  DMA_BIT_MASK(32));
 147 }
 148
 149 struct platform_device *__init imx53_add_ahci_imx(void)
 150 {
 151         struct ahci_platform_data pdata = {
 152                 .init = imx_sata_init,
 153                 .exit = imx_sata_exit,
 154         };
 155
 156         return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
 157 }