Pileus Git - ~andy/linux/blob - arch/arm/mach-highbank/highbank.c

   1 /*
   2  * Copyright 2010-2011 Calxeda, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #include <linux/clk.h>
  17 #include <linux/clkdev.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/io.h>
  21 #include <linux/irqchip.h>
  22 #include <linux/of.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/of_address.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/clk-provider.h>
  28 #include <linux/platform_device.h>
  29
  30 #include <asm/psci.h>
  31 #include <asm/hardware/cache-l2x0.h>
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/map.h>
  34
  35 #include "core.h"
  36 #include "sysregs.h"
  37
  38 void __iomem *sregs_base;
  39 void __iomem *scu_base_addr;
  40
  41 static void __init highbank_scu_map_io(void)
  42 {
  43         unsigned long base;
  44
  45         /* Get SCU base */
  46         asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
  47
  48         scu_base_addr = ioremap(base, SZ_4K);
  49 }
  50
  51
  52 static void highbank_l2x0_disable(void)
  53 {
  54         /* Disable PL310 L2 Cache controller */
  55         highbank_smc1(0x102, 0x0);
  56 }
  57
  58 static void __init highbank_init_irq(void)
  59 {
  60         irqchip_init();
  61
  62         if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
  63                 highbank_scu_map_io();
  64
  65         /* Enable PL310 L2 Cache controller */
  66         if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
  67             of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
  68                 highbank_smc1(0x102, 0x1);
  69                 l2x0_of_init(0, ~0UL);
  70                 outer_cache.disable = highbank_l2x0_disable;
  71         }
  72 }
  73
  74 static void __init highbank_timer_init(void)
  75 {
  76         struct device_node *np;
  77
  78         /* Map system registers */
  79         np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
  80         sregs_base = of_iomap(np, 0);
  81         WARN_ON(!sregs_base);
  82
  83         of_clk_init(NULL);
  84
  85         clocksource_of_init();
  86 }
  87
  88 static void highbank_power_off(void)
  89 {
  90         highbank_set_pwr_shutdown();
  91
  92         while (1)
  93                 cpu_do_idle();
  94 }
  95
  96 static int highbank_platform_notifier(struct notifier_block *nb,
  97                                   unsigned long event, void *__dev)
  98 {
  99         struct resource *res;
 100         int reg = -1;
 101         u32 val;
 102         struct device *dev = __dev;
 103
 104         if (event != BUS_NOTIFY_ADD_DEVICE)
 105                 return NOTIFY_DONE;
 106
 107         if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci"))
 108                 reg = 0xc;
 109         else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci"))
 110                 reg = 0x18;
 111         else if (of_device_is_compatible(dev->of_node, "arm,pl330"))
 112                 reg = 0x20;
 113         else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) {
 114                 res = platform_get_resource(to_platform_device(dev),
 115                                             IORESOURCE_MEM, 0);
 116                 if (res) {
 117                         if (res->start == 0xfff50000)
 118                                 reg = 0;
 119                         else if (res->start == 0xfff51000)
 120                                 reg = 4;
 121                 }
 122         }
 123
 124         if (reg < 0)
 125                 return NOTIFY_DONE;
 126
 127         if (of_property_read_bool(dev->of_node, "dma-coherent")) {
 128                 val = readl(sregs_base + reg);
 129                 writel(val | 0xff01, sregs_base + reg);
 130                 set_dma_ops(dev, &arm_coherent_dma_ops);
 131         }
 132
 133         return NOTIFY_OK;
 134 }
 135
 136 static struct notifier_block highbank_amba_nb = {
 137         .notifier_call = highbank_platform_notifier,
 138 };
 139
 140 static struct notifier_block highbank_platform_nb = {
 141         .notifier_call = highbank_platform_notifier,
 142 };
 143
 144 static struct platform_device highbank_cpuidle_device = {
 145         .name = "cpuidle-calxeda",
 146 };
 147
 148 static void __init highbank_init(void)
 149 {
 150         pm_power_off = highbank_power_off;
 151         highbank_pm_init();
 152
 153         bus_register_notifier(&platform_bus_type, &highbank_platform_nb);
 154         bus_register_notifier(&amba_bustype, &highbank_amba_nb);
 155
 156         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 157
 158         if (psci_ops.cpu_suspend)
 159                 platform_device_register(&highbank_cpuidle_device);
 160 }
 161
 162 static const char *highbank_match[] __initconst = {
 163         "calxeda,highbank",
 164         "calxeda,ecx-2000",
 165         NULL,
 166 };
 167
 168 DT_MACHINE_START(HIGHBANK, "Highbank")
 169 #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
 170         .dma_zone_size  = (4ULL * SZ_1G),
 171 #endif
 172         .init_irq       = highbank_init_irq,
 173         .init_time      = highbank_timer_init,
 174         .init_machine   = highbank_init,
 175         .dt_compat      = highbank_match,
 176         .restart        = highbank_restart,
 177 MACHINE_END