Pileus Git - ~andy/linux/blob - arch/arm/mach-footbridge/common.c

   1 /*
   2  *  linux/arch/arm/mach-footbridge/common.c
   3  *
   4  *  Copyright (C) 1998-2000 Russell King, Dave Gilbert.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/types.h>
  12 #include <linux/mm.h>
  13 #include <linux/ioport.h>
  14 #include <linux/list.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/spinlock.h>
  18
  19 #include <asm/pgtable.h>
  20 #include <asm/page.h>
  21 #include <asm/irq.h>
  22 #include <asm/mach-types.h>
  23 #include <asm/setup.h>
  24 #include <asm/system_misc.h>
  25 #include <asm/hardware/dec21285.h>
  26
  27 #include <asm/mach/irq.h>
  28 #include <asm/mach/map.h>
  29
  30 #include "common.h"
  31
  32 unsigned int mem_fclk_21285 = 50000000;
  33
  34 EXPORT_SYMBOL(mem_fclk_21285);
  35
  36 static int __init early_fclk(char *arg)
  37 {
  38         mem_fclk_21285 = simple_strtoul(arg, NULL, 0);
  39         return 0;
  40 }
  41
  42 early_param("mem_fclk_21285", early_fclk);
  43
  44 static int __init parse_tag_memclk(const struct tag *tag)
  45 {
  46         mem_fclk_21285 = tag->u.memclk.fmemclk;
  47         return 0;
  48 }
  49
  50 __tagtable(ATAG_MEMCLK, parse_tag_memclk);
  51
  52 /*
  53  * Footbridge IRQ translation table
  54  *  Converts from our IRQ numbers into FootBridge masks
  55  */
  56 static const int fb_irq_mask[] = {
  57         IRQ_MASK_UART_RX,       /*  0 */
  58         IRQ_MASK_UART_TX,       /*  1 */
  59         IRQ_MASK_TIMER1,        /*  2 */
  60         IRQ_MASK_TIMER2,        /*  3 */
  61         IRQ_MASK_TIMER3,        /*  4 */
  62         IRQ_MASK_IN0,           /*  5 */
  63         IRQ_MASK_IN1,           /*  6 */
  64         IRQ_MASK_IN2,           /*  7 */
  65         IRQ_MASK_IN3,           /*  8 */
  66         IRQ_MASK_DOORBELLHOST,  /*  9 */
  67         IRQ_MASK_DMA1,          /* 10 */
  68         IRQ_MASK_DMA2,          /* 11 */
  69         IRQ_MASK_PCI,           /* 12 */
  70         IRQ_MASK_SDRAMPARITY,   /* 13 */
  71         IRQ_MASK_I2OINPOST,     /* 14 */
  72         IRQ_MASK_PCI_ABORT,     /* 15 */
  73         IRQ_MASK_PCI_SERR,      /* 16 */
  74         IRQ_MASK_DISCARD_TIMER, /* 17 */
  75         IRQ_MASK_PCI_DPERR,     /* 18 */
  76         IRQ_MASK_PCI_PERR,      /* 19 */
  77 };
  78
  79 static void fb_mask_irq(struct irq_data *d)
  80 {
  81         *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)];
  82 }
  83
  84 static void fb_unmask_irq(struct irq_data *d)
  85 {
  86         *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)];
  87 }
  88
  89 static struct irq_chip fb_chip = {
  90         .irq_ack        = fb_mask_irq,
  91         .irq_mask       = fb_mask_irq,
  92         .irq_unmask     = fb_unmask_irq,
  93 };
  94
  95 static void __init __fb_init_irq(void)
  96 {
  97         unsigned int irq;
  98
  99         /*
 100          * setup DC21285 IRQs
 101          */
 102         *CSR_IRQ_DISABLE = -1;
 103         *CSR_FIQ_DISABLE = -1;
 104
 105         for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
 106                 irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
 107                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 108         }
 109 }
 110
 111 void __init footbridge_init_irq(void)
 112 {
 113         __fb_init_irq();
 114
 115         if (!footbridge_cfn_mode())
 116                 return;
 117
 118         if (machine_is_ebsa285())
 119                 /* The following is dependent on which slot
 120                  * you plug the Southbridge card into.  We
 121                  * currently assume that you plug it into
 122                  * the right-hand most slot.
 123                  */
 124                 isa_init_irq(IRQ_PCI);
 125
 126         if (machine_is_cats())
 127                 isa_init_irq(IRQ_IN2);
 128
 129         if (machine_is_netwinder())
 130                 isa_init_irq(IRQ_IN3);
 131 }
 132
 133 /*
 134  * Common mapping for all systems.  Note that the outbound write flush is
 135  * commented out since there is a "No Fix" problem with it.  Not mapping
 136  * it means that we have extra bullet protection on our feet.
 137  */
 138 static struct map_desc fb_common_io_desc[] __initdata = {
 139         {
 140                 .virtual        = ARMCSR_BASE,
 141                 .pfn            = __phys_to_pfn(DC21285_ARMCSR_BASE),
 142                 .length         = ARMCSR_SIZE,
 143                 .type           = MT_DEVICE,
 144         }, {
 145                 .virtual        = XBUS_BASE,
 146                 .pfn            = __phys_to_pfn(0x40000000),
 147                 .length         = XBUS_SIZE,
 148                 .type           = MT_DEVICE,
 149         }
 150 };
 151
 152 /*
 153  * The mapping when the footbridge is in host mode.  We don't map any of
 154  * this when we are in add-in mode.
 155  */
 156 static struct map_desc ebsa285_host_io_desc[] __initdata = {
 157 #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
 158         {
 159                 .virtual        = PCIMEM_BASE,
 160                 .pfn            = __phys_to_pfn(DC21285_PCI_MEM),
 161                 .length         = PCIMEM_SIZE,
 162                 .type           = MT_DEVICE,
 163         }, {
 164                 .virtual        = PCICFG0_BASE,
 165                 .pfn            = __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG),
 166                 .length         = PCICFG0_SIZE,
 167                 .type           = MT_DEVICE,
 168         }, {
 169                 .virtual        = PCICFG1_BASE,
 170                 .pfn            = __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG),
 171                 .length         = PCICFG1_SIZE,
 172                 .type           = MT_DEVICE,
 173         }, {
 174                 .virtual        = PCIIACK_BASE,
 175                 .pfn            = __phys_to_pfn(DC21285_PCI_IACK),
 176                 .length         = PCIIACK_SIZE,
 177                 .type           = MT_DEVICE,
 178         }, {
 179                 .virtual        = PCIO_BASE,
 180                 .pfn            = __phys_to_pfn(DC21285_PCI_IO),
 181                 .length         = PCIO_SIZE,
 182                 .type           = MT_DEVICE,
 183         },
 184 #endif
 185 };
 186
 187 void __init footbridge_map_io(void)
 188 {
 189         /*
 190          * Set up the common mapping first; we need this to
 191          * determine whether we're in host mode or not.
 192          */
 193         iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc));
 194
 195         /*
 196          * Now, work out what we've got to map in addition on this
 197          * platform.
 198          */
 199         if (footbridge_cfn_mode())
 200                 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
 201 }
 202
 203 void footbridge_restart(char mode, const char *cmd)
 204 {
 205         if (mode == 's') {
 206                 /* Jump into the ROM */
 207                 soft_restart(0x41000000);
 208         } else {
 209                 /*
 210                  * Force the watchdog to do a CPU reset.
 211                  *
 212                  * After making sure that the watchdog is disabled
 213                  * (so we can change the timer registers) we first
 214                  * enable the timer to autoreload itself.  Next, the
 215                  * timer interval is set really short and any
 216                  * current interrupt request is cleared (so we can
 217                  * see an edge transition).  Finally, TIMER4 is
 218                  * enabled as the watchdog.
 219                  */
 220                 *CSR_SA110_CNTL &= ~(1 << 13);
 221                 *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
 222                                    TIMER_CNTL_AUTORELOAD |
 223                                    TIMER_CNTL_DIV16;
 224                 *CSR_TIMER4_LOAD = 0x2;
 225                 *CSR_TIMER4_CLR  = 0;
 226                 *CSR_SA110_CNTL |= (1 << 13);
 227         }
 228 }
 229
 230 #ifdef CONFIG_FOOTBRIDGE_ADDIN
 231
 232 static inline unsigned long fb_bus_sdram_offset(void)
 233 {
 234         return *CSR_PCISDRAMBASE & 0xfffffff0;
 235 }
 236
 237 /*
 238  * These two functions convert virtual addresses to PCI addresses and PCI
 239  * addresses to virtual addresses.  Note that it is only legal to use these
 240  * on memory obtained via get_zeroed_page or kmalloc.
 241  */
 242 unsigned long __virt_to_bus(unsigned long res)
 243 {
 244         WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
 245
 246         return res + (fb_bus_sdram_offset() - PAGE_OFFSET);
 247 }
 248 EXPORT_SYMBOL(__virt_to_bus);
 249
 250 unsigned long __bus_to_virt(unsigned long res)
 251 {
 252         res = res - (fb_bus_sdram_offset() - PAGE_OFFSET);
 253
 254         WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
 255
 256         return res;
 257 }
 258 EXPORT_SYMBOL(__bus_to_virt);
 259
 260 unsigned long __pfn_to_bus(unsigned long pfn)
 261 {
 262         return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
 263 }
 264 EXPORT_SYMBOL(__pfn_to_bus);
 265
 266 unsigned long __bus_to_pfn(unsigned long bus)
 267 {
 268         return __phys_to_pfn(bus - (fb_bus_sdram_offset() - PHYS_OFFSET));
 269 }
 270 EXPORT_SYMBOL(__bus_to_pfn);
 271
 272 #endif