1 /* linux/arch/arm/mach-exynos4/mach-armlex4210.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/gpio.h>
13 #include <linux/mmc/host.h>
14 #include <linux/platform_device.h>
15 #include <linux/serial_core.h>
16 #include <linux/smsc911x.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach-types.h>
22 #include <plat/devs.h>
23 #include <plat/gpio-cfg.h>
24 #include <plat/regs-serial.h>
25 #include <plat/regs-srom.h>
26 #include <plat/sdhci.h>
32 /* Following are default values for UCON, ULCON and UFCON UART registers */
33 #define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
34 S3C2410_UCON_RXILEVEL | \
35 S3C2410_UCON_TXIRQMODE | \
36 S3C2410_UCON_RXIRQMODE | \
37 S3C2410_UCON_RXFIFO_TOI | \
38 S3C2443_UCON_RXERR_IRQEN)
40 #define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
42 #define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
43 S5PV210_UFCON_TXTRIG4 | \
44 S5PV210_UFCON_RXTRIG4)
46 static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
50 .ucon = ARMLEX4210_UCON_DEFAULT,
51 .ulcon = ARMLEX4210_ULCON_DEFAULT,
52 .ufcon = ARMLEX4210_UFCON_DEFAULT,
57 .ucon = ARMLEX4210_UCON_DEFAULT,
58 .ulcon = ARMLEX4210_ULCON_DEFAULT,
59 .ufcon = ARMLEX4210_UFCON_DEFAULT,
64 .ucon = ARMLEX4210_UCON_DEFAULT,
65 .ulcon = ARMLEX4210_ULCON_DEFAULT,
66 .ufcon = ARMLEX4210_UFCON_DEFAULT,
71 .ucon = ARMLEX4210_UCON_DEFAULT,
72 .ulcon = ARMLEX4210_ULCON_DEFAULT,
73 .ufcon = ARMLEX4210_UFCON_DEFAULT,
77 static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
78 .cd_type = S3C_SDHCI_CD_PERMANENT,
79 #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
81 .host_caps = MMC_CAP_8_BIT_DATA,
85 static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
86 .cd_type = S3C_SDHCI_CD_GPIO,
87 .ext_cd_gpio = EXYNOS4_GPX2(5),
88 .ext_cd_gpio_invert = 1,
92 static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
93 .cd_type = S3C_SDHCI_CD_PERMANENT,
97 static void __init armlex4210_sdhci_init(void)
99 s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
100 s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
101 s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
104 static void __init armlex4210_wlan_init(void)
107 s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
108 s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
111 s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
112 s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
115 s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
116 s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
119 static struct resource armlex4210_smsc911x_resources[] = {
120 [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K),
121 [1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \
122 | IRQF_TRIGGER_HIGH),
125 static struct smsc911x_platform_config smsc9215_config = {
126 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
127 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
128 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
129 .phy_interface = PHY_INTERFACE_MODE_MII,
130 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
133 static struct platform_device armlex4210_smsc911x = {
136 .num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
137 .resource = armlex4210_smsc911x_resources,
139 .platform_data = &smsc9215_config,
143 static struct platform_device *armlex4210_devices[] __initdata = {
149 &armlex4210_smsc911x,
150 &exynos4_device_ahci,
153 static void __init armlex4210_smsc911x_init(void)
157 /* configure nCS1 width to 16 bits */
158 cs1 = __raw_readl(S5P_SROM_BW) &
159 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
160 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
161 (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
162 (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
163 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
164 S5P_SROM_BW__NCS1__SHIFT;
165 __raw_writel(cs1, S5P_SROM_BW);
167 /* set timing for nCS1 suitable for ethernet chip */
168 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
169 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
170 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
171 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
172 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
173 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
174 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
177 static void __init armlex4210_map_io(void)
179 exynos_init_io(NULL, 0);
180 s3c24xx_init_clocks(24000000);
181 s3c24xx_init_uarts(armlex4210_uartcfgs,
182 ARRAY_SIZE(armlex4210_uartcfgs));
185 static void __init armlex4210_machine_init(void)
187 armlex4210_smsc911x_init();
189 armlex4210_sdhci_init();
191 armlex4210_wlan_init();
193 platform_add_devices(armlex4210_devices,
194 ARRAY_SIZE(armlex4210_devices));
197 MACHINE_START(ARMLEX4210, "ARMLEX4210")
198 /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
199 .atag_offset = 0x100,
200 .smp = smp_ops(exynos_smp_ops),
201 .init_irq = exynos4_init_irq,
202 .map_io = armlex4210_map_io,
203 .init_machine = armlex4210_machine_init,
204 .init_late = exynos_init_late,
205 .init_time = exynos4_timer_init,
206 .restart = exynos4_restart,