Pileus Git - ~andy/linux/blob - arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/io.h>
  17 #include <linux/device.h>
  18 #include <linux/gpio.h>
  19 #include <linux/sched.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/of.h>
  22 #include <linux/of_fdt.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/export.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/irqchip.h>
  27 #include <linux/of_address.h>
  28 #include <linux/irqchip/arm-gic.h>
  29 #include <linux/irqchip/chained_irq.h>
  30
  31 #include <asm/proc-fns.h>
  32 #include <asm/exception.h>
  33 #include <asm/hardware/cache-l2x0.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/cacheflush.h>
  37
  38 #include <mach/regs-irq.h>
  39 #include <mach/regs-pmu.h>
  40 #include <mach/regs-gpio.h>
  41
  42 #include <plat/cpu.h>
  43 #include <plat/clock.h>
  44 #include <plat/devs.h>
  45 #include <plat/pm.h>
  46 #include <plat/sdhci.h>
  47 #include <plat/gpio-cfg.h>
  48 #include <plat/adc-core.h>
  49 #include <plat/fb-core.h>
  50 #include <plat/fimc-core.h>
  51 #include <plat/iic-core.h>
  52 #include <plat/tv-core.h>
  53 #include <plat/spi-core.h>
  54 #include <plat/regs-serial.h>
  55
  56 #include "common.h"
  57 #define L2_AUX_VAL 0x7C470001
  58 #define L2_AUX_MASK 0xC200ffff
  59
  60 static const char name_exynos4210[] = "EXYNOS4210";
  61 static const char name_exynos4212[] = "EXYNOS4212";
  62 static const char name_exynos4412[] = "EXYNOS4412";
  63 static const char name_exynos5250[] = "EXYNOS5250";
  64 static const char name_exynos5440[] = "EXYNOS5440";
  65
  66 static void exynos4_map_io(void);
  67 static void exynos5_map_io(void);
  68 static void exynos5440_map_io(void);
  69 static void exynos4_init_clocks(int xtal);
  70 static void exynos5_init_clocks(int xtal);
  71 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  72 static int exynos_init(void);
  73
  74 static struct cpu_table cpu_ids[] __initdata = {
  75         {
  76                 .idcode         = EXYNOS4210_CPU_ID,
  77                 .idmask         = EXYNOS4_CPU_MASK,
  78                 .map_io         = exynos4_map_io,
  79                 .init_clocks    = exynos4_init_clocks,
  80                 .init_uarts     = exynos4_init_uarts,
  81                 .init           = exynos_init,
  82                 .name           = name_exynos4210,
  83         }, {
  84                 .idcode         = EXYNOS4212_CPU_ID,
  85                 .idmask         = EXYNOS4_CPU_MASK,
  86                 .map_io         = exynos4_map_io,
  87                 .init_clocks    = exynos4_init_clocks,
  88                 .init_uarts     = exynos4_init_uarts,
  89                 .init           = exynos_init,
  90                 .name           = name_exynos4212,
  91         }, {
  92                 .idcode         = EXYNOS4412_CPU_ID,
  93                 .idmask         = EXYNOS4_CPU_MASK,
  94                 .map_io         = exynos4_map_io,
  95                 .init_clocks    = exynos4_init_clocks,
  96                 .init_uarts     = exynos4_init_uarts,
  97                 .init           = exynos_init,
  98                 .name           = name_exynos4412,
  99         }, {
 100                 .idcode         = EXYNOS5250_SOC_ID,
 101                 .idmask         = EXYNOS5_SOC_MASK,
 102                 .map_io         = exynos5_map_io,
 103                 .init_clocks    = exynos5_init_clocks,
 104                 .init           = exynos_init,
 105                 .name           = name_exynos5250,
 106         }, {
 107                 .idcode         = EXYNOS5440_SOC_ID,
 108                 .idmask         = EXYNOS5_SOC_MASK,
 109                 .map_io         = exynos5440_map_io,
 110                 .init           = exynos_init,
 111                 .name           = name_exynos5440,
 112         },
 113 };
 114
 115 /* Initial IO mappings */
 116
 117 static struct map_desc exynos_iodesc[] __initdata = {
 118         {
 119                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 120                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 121                 .length         = SZ_4K,
 122                 .type           = MT_DEVICE,
 123         },
 124 };
 125
 126 #ifdef CONFIG_ARCH_EXYNOS5
 127 static struct map_desc exynos5440_iodesc[] __initdata = {
 128         {
 129                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 130                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
 131                 .length         = SZ_4K,
 132                 .type           = MT_DEVICE,
 133         },
 134 };
 135 #endif
 136
 137 static struct map_desc exynos4_iodesc[] __initdata = {
 138         {
 139                 .virtual        = (unsigned long)S3C_VA_SYS,
 140                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 141                 .length         = SZ_64K,
 142                 .type           = MT_DEVICE,
 143         }, {
 144                 .virtual        = (unsigned long)S3C_VA_TIMER,
 145                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 146                 .length         = SZ_16K,
 147                 .type           = MT_DEVICE,
 148         }, {
 149                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 150                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 151                 .length         = SZ_4K,
 152                 .type           = MT_DEVICE,
 153         }, {
 154                 .virtual        = (unsigned long)S5P_VA_SROMC,
 155                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 156                 .length         = SZ_4K,
 157                 .type           = MT_DEVICE,
 158         }, {
 159                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 160                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 161                 .length         = SZ_4K,
 162                 .type           = MT_DEVICE,
 163         }, {
 164                 .virtual        = (unsigned long)S5P_VA_PMU,
 165                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 166                 .length         = SZ_64K,
 167                 .type           = MT_DEVICE,
 168         }, {
 169                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 170                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 171                 .length         = SZ_4K,
 172                 .type           = MT_DEVICE,
 173         }, {
 174                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 175                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 176                 .length         = SZ_64K,
 177                 .type           = MT_DEVICE,
 178         }, {
 179                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 180                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 181                 .length         = SZ_64K,
 182                 .type           = MT_DEVICE,
 183         }, {
 184                 .virtual        = (unsigned long)S3C_VA_UART,
 185                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 186                 .length         = SZ_512K,
 187                 .type           = MT_DEVICE,
 188         }, {
 189                 .virtual        = (unsigned long)S5P_VA_CMU,
 190                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 191                 .length         = SZ_128K,
 192                 .type           = MT_DEVICE,
 193         }, {
 194                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 195                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 196                 .length         = SZ_8K,
 197                 .type           = MT_DEVICE,
 198         }, {
 199                 .virtual        = (unsigned long)S5P_VA_L2CC,
 200                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 201                 .length         = SZ_4K,
 202                 .type           = MT_DEVICE,
 203         }, {
 204                 .virtual        = (unsigned long)S5P_VA_DMC0,
 205                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 206                 .length         = SZ_64K,
 207                 .type           = MT_DEVICE,
 208         }, {
 209                 .virtual        = (unsigned long)S5P_VA_DMC1,
 210                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 211                 .length         = SZ_64K,
 212                 .type           = MT_DEVICE,
 213         }, {
 214                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 215                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 216                 .length         = SZ_4K,
 217                 .type           = MT_DEVICE,
 218         },
 219 };
 220
 221 static struct map_desc exynos4_iodesc0[] __initdata = {
 222         {
 223                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 224                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 225                 .length         = SZ_4K,
 226                 .type           = MT_DEVICE,
 227         },
 228 };
 229
 230 static struct map_desc exynos4_iodesc1[] __initdata = {
 231         {
 232                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 233                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 234                 .length         = SZ_4K,
 235                 .type           = MT_DEVICE,
 236         },
 237 };
 238
 239 static struct map_desc exynos5_iodesc[] __initdata = {
 240         {
 241                 .virtual        = (unsigned long)S3C_VA_SYS,
 242                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 243                 .length         = SZ_64K,
 244                 .type           = MT_DEVICE,
 245         }, {
 246                 .virtual        = (unsigned long)S3C_VA_TIMER,
 247                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 248                 .length         = SZ_16K,
 249                 .type           = MT_DEVICE,
 250         }, {
 251                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 252                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 253                 .length         = SZ_4K,
 254                 .type           = MT_DEVICE,
 255         }, {
 256                 .virtual        = (unsigned long)S5P_VA_SROMC,
 257                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 258                 .length         = SZ_4K,
 259                 .type           = MT_DEVICE,
 260         }, {
 261                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 262                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
 263                 .length         = SZ_4K,
 264                 .type           = MT_DEVICE,
 265         }, {
 266                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 267                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 268                 .length         = SZ_4K,
 269                 .type           = MT_DEVICE,
 270         }, {
 271                 .virtual        = (unsigned long)S5P_VA_CMU,
 272                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 273                 .length         = 144 * SZ_1K,
 274                 .type           = MT_DEVICE,
 275         }, {
 276                 .virtual        = (unsigned long)S5P_VA_PMU,
 277                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 278                 .length         = SZ_64K,
 279                 .type           = MT_DEVICE,
 280         }, {
 281                 .virtual        = (unsigned long)S3C_VA_UART,
 282                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 283                 .length         = SZ_512K,
 284                 .type           = MT_DEVICE,
 285         },
 286 };
 287
 288 static struct map_desc exynos5440_iodesc0[] __initdata = {
 289         {
 290                 .virtual        = (unsigned long)S3C_VA_UART,
 291                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 292                 .length         = SZ_512K,
 293                 .type           = MT_DEVICE,
 294         },
 295 };
 296
 297 void exynos4_restart(char mode, const char *cmd)
 298 {
 299         __raw_writel(0x1, S5P_SWRESET);
 300 }
 301
 302 void exynos5_restart(char mode, const char *cmd)
 303 {
 304         struct device_node *np;
 305         u32 val;
 306         void __iomem *addr;
 307
 308         if (of_machine_is_compatible("samsung,exynos5250")) {
 309                 val = 0x1;
 310                 addr = EXYNOS_SWRESET;
 311         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 312                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 313                 addr = of_iomap(np, 0) + 0xcc;
 314                 val = (0xfff << 20) | (0x1 << 16);
 315         } else {
 316                 pr_err("%s: cannot support non-DT\n", __func__);
 317                 return;
 318         }
 319
 320         __raw_writel(val, addr);
 321 }
 322
 323 void __init exynos_init_late(void)
 324 {
 325         if (of_machine_is_compatible("samsung,exynos5440"))
 326                 /* to be supported later */
 327                 return;
 328
 329         exynos_pm_late_initcall();
 330 }
 331
 332 /*
 333  * exynos_map_io
 334  *
 335  * register the standard cpu IO areas
 336  */
 337
 338 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 339 {
 340         struct map_desc *iodesc = exynos_iodesc;
 341         int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
 342 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
 343         unsigned long root = of_get_flat_dt_root();
 344
 345         /* initialize the io descriptors we need for initialization */
 346         if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
 347                 iodesc = exynos5440_iodesc;
 348                 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
 349         }
 350 #endif
 351
 352         iotable_init(iodesc, iodesc_sz);
 353
 354         if (mach_desc)
 355                 iotable_init(mach_desc, size);
 356
 357         /* detect cpu id and rev. */
 358         s5p_init_cpu(S5P_VA_CHIPID);
 359
 360         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 361 }
 362
 363 static void __init exynos4_map_io(void)
 364 {
 365         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 366
 367         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 368                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 369         else
 370                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 371
 372         /* initialize device information early */
 373         exynos4_default_sdhci0();
 374         exynos4_default_sdhci1();
 375         exynos4_default_sdhci2();
 376         exynos4_default_sdhci3();
 377
 378         s3c_adc_setname("samsung-adc-v3");
 379
 380         s3c_fimc_setname(0, "exynos4-fimc");
 381         s3c_fimc_setname(1, "exynos4-fimc");
 382         s3c_fimc_setname(2, "exynos4-fimc");
 383         s3c_fimc_setname(3, "exynos4-fimc");
 384
 385         s3c_sdhci_setname(0, "exynos4-sdhci");
 386         s3c_sdhci_setname(1, "exynos4-sdhci");
 387         s3c_sdhci_setname(2, "exynos4-sdhci");
 388         s3c_sdhci_setname(3, "exynos4-sdhci");
 389
 390         /* The I2C bus controllers are directly compatible with s3c2440 */
 391         s3c_i2c0_setname("s3c2440-i2c");
 392         s3c_i2c1_setname("s3c2440-i2c");
 393         s3c_i2c2_setname("s3c2440-i2c");
 394
 395         s5p_fb_setname(0, "exynos4-fb");
 396         s5p_hdmi_setname("exynos4-hdmi");
 397
 398         s3c64xx_spi_setname("exynos4210-spi");
 399 }
 400
 401 static void __init exynos5_map_io(void)
 402 {
 403         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 404 }
 405
 406 static void __init exynos4_init_clocks(int xtal)
 407 {
 408         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 409
 410         s3c24xx_register_baseclocks(xtal);
 411         s5p_register_clocks(xtal);
 412
 413         if (soc_is_exynos4210())
 414                 exynos4210_register_clocks();
 415         else if (soc_is_exynos4212() || soc_is_exynos4412())
 416                 exynos4212_register_clocks();
 417
 418         exynos4_register_clocks();
 419         exynos4_setup_clocks();
 420 }
 421
 422 static void __init exynos5440_map_io(void)
 423 {
 424         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 425 }
 426
 427 static void __init exynos5_init_clocks(int xtal)
 428 {
 429         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 430
 431         /* EXYNOS5440 can support only common clock framework */
 432
 433         if (soc_is_exynos5440())
 434                 return;
 435
 436 #ifdef CONFIG_SOC_EXYNOS5250
 437         s3c24xx_register_baseclocks(xtal);
 438         s5p_register_clocks(xtal);
 439
 440         exynos5_register_clocks();
 441         exynos5_setup_clocks();
 442 #endif
 443 }
 444
 445 void __init exynos4_init_irq(void)
 446 {
 447         unsigned int gic_bank_offset;
 448
 449         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 450
 451         if (!of_have_populated_dt())
 452                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 453 #ifdef CONFIG_OF
 454         else
 455                 irqchip_init();
 456 #endif
 457
 458         if (!of_have_populated_dt())
 459                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 460
 461         /*
 462          * The parameters of s5p_init_irq() are for VIC init.
 463          * Theses parameters should be NULL and 0 because EXYNOS4
 464          * uses GIC instead of VIC.
 465          */
 466         s5p_init_irq(NULL, 0);
 467 }
 468
 469 void __init exynos5_init_irq(void)
 470 {
 471 #ifdef CONFIG_OF
 472         irqchip_init();
 473 #endif
 474         /*
 475          * The parameters of s5p_init_irq() are for VIC init.
 476          * Theses parameters should be NULL and 0 because EXYNOS4
 477          * uses GIC instead of VIC.
 478          */
 479         if (!of_machine_is_compatible("samsung,exynos5440"))
 480                 s5p_init_irq(NULL, 0);
 481
 482         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 483 }
 484
 485 struct bus_type exynos_subsys = {
 486         .name           = "exynos-core",
 487         .dev_name       = "exynos-core",
 488 };
 489
 490 static struct device exynos4_dev = {
 491         .bus    = &exynos_subsys,
 492 };
 493
 494 static int __init exynos_core_init(void)
 495 {
 496         return subsys_system_register(&exynos_subsys, NULL);
 497 }
 498 core_initcall(exynos_core_init);
 499
 500 #ifdef CONFIG_CACHE_L2X0
 501 static int __init exynos4_l2x0_cache_init(void)
 502 {
 503         int ret;
 504
 505         if (soc_is_exynos5250() || soc_is_exynos5440())
 506                 return 0;
 507
 508         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 509         if (!ret) {
 510                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 511                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 512                 return 0;
 513         }
 514
 515         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 516                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 517                 /* TAG, Data Latency Control: 2 cycles */
 518                 l2x0_saved_regs.tag_latency = 0x110;
 519
 520                 if (soc_is_exynos4212() || soc_is_exynos4412())
 521                         l2x0_saved_regs.data_latency = 0x120;
 522                 else
 523                         l2x0_saved_regs.data_latency = 0x110;
 524
 525                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 526                 l2x0_saved_regs.pwr_ctrl =
 527                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 528
 529                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 530
 531                 __raw_writel(l2x0_saved_regs.tag_latency,
 532                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 533                 __raw_writel(l2x0_saved_regs.data_latency,
 534                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 535
 536                 /* L2X0 Prefetch Control */
 537                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 538                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 539
 540                 /* L2X0 Power Control */
 541                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 542                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 543
 544                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 545                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 546         }
 547
 548         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 549         return 0;
 550 }
 551 early_initcall(exynos4_l2x0_cache_init);
 552 #endif
 553
 554 static int __init exynos_init(void)
 555 {
 556         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 557
 558         return device_register(&exynos4_dev);
 559 }
 560
 561 /* uart registration process */
 562
 563 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 564 {
 565         struct s3c2410_uartcfg *tcfg = cfg;
 566         u32 ucnt;
 567
 568         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 569                 tcfg->has_fracval = 1;
 570
 571         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 572 }
 573
 574 static void __iomem *exynos_eint_base;
 575
 576 static DEFINE_SPINLOCK(eint_lock);
 577
 578 static unsigned int eint0_15_data[16];
 579
 580 static inline int exynos4_irq_to_gpio(unsigned int irq)
 581 {
 582         if (irq < IRQ_EINT(0))
 583                 return -EINVAL;
 584
 585         irq -= IRQ_EINT(0);
 586         if (irq < 8)
 587                 return EXYNOS4_GPX0(irq);
 588
 589         irq -= 8;
 590         if (irq < 8)
 591                 return EXYNOS4_GPX1(irq);
 592
 593         irq -= 8;
 594         if (irq < 8)
 595                 return EXYNOS4_GPX2(irq);
 596
 597         irq -= 8;
 598         if (irq < 8)
 599                 return EXYNOS4_GPX3(irq);
 600
 601         return -EINVAL;
 602 }
 603
 604 static inline int exynos5_irq_to_gpio(unsigned int irq)
 605 {
 606         if (irq < IRQ_EINT(0))
 607                 return -EINVAL;
 608
 609         irq -= IRQ_EINT(0);
 610         if (irq < 8)
 611                 return EXYNOS5_GPX0(irq);
 612
 613         irq -= 8;
 614         if (irq < 8)
 615                 return EXYNOS5_GPX1(irq);
 616
 617         irq -= 8;
 618         if (irq < 8)
 619                 return EXYNOS5_GPX2(irq);
 620
 621         irq -= 8;
 622         if (irq < 8)
 623                 return EXYNOS5_GPX3(irq);
 624
 625         return -EINVAL;
 626 }
 627
 628 static unsigned int exynos4_eint0_15_src_int[16] = {
 629         EXYNOS4_IRQ_EINT0,
 630         EXYNOS4_IRQ_EINT1,
 631         EXYNOS4_IRQ_EINT2,
 632         EXYNOS4_IRQ_EINT3,
 633         EXYNOS4_IRQ_EINT4,
 634         EXYNOS4_IRQ_EINT5,
 635         EXYNOS4_IRQ_EINT6,
 636         EXYNOS4_IRQ_EINT7,
 637         EXYNOS4_IRQ_EINT8,
 638         EXYNOS4_IRQ_EINT9,
 639         EXYNOS4_IRQ_EINT10,
 640         EXYNOS4_IRQ_EINT11,
 641         EXYNOS4_IRQ_EINT12,
 642         EXYNOS4_IRQ_EINT13,
 643         EXYNOS4_IRQ_EINT14,
 644         EXYNOS4_IRQ_EINT15,
 645 };
 646
 647 static unsigned int exynos5_eint0_15_src_int[16] = {
 648         EXYNOS5_IRQ_EINT0,
 649         EXYNOS5_IRQ_EINT1,
 650         EXYNOS5_IRQ_EINT2,
 651         EXYNOS5_IRQ_EINT3,
 652         EXYNOS5_IRQ_EINT4,
 653         EXYNOS5_IRQ_EINT5,
 654         EXYNOS5_IRQ_EINT6,
 655         EXYNOS5_IRQ_EINT7,
 656         EXYNOS5_IRQ_EINT8,
 657         EXYNOS5_IRQ_EINT9,
 658         EXYNOS5_IRQ_EINT10,
 659         EXYNOS5_IRQ_EINT11,
 660         EXYNOS5_IRQ_EINT12,
 661         EXYNOS5_IRQ_EINT13,
 662         EXYNOS5_IRQ_EINT14,
 663         EXYNOS5_IRQ_EINT15,
 664 };
 665 static inline void exynos_irq_eint_mask(struct irq_data *data)
 666 {
 667         u32 mask;
 668
 669         spin_lock(&eint_lock);
 670         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 671         mask |= EINT_OFFSET_BIT(data->irq);
 672         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 673         spin_unlock(&eint_lock);
 674 }
 675
 676 static void exynos_irq_eint_unmask(struct irq_data *data)
 677 {
 678         u32 mask;
 679
 680         spin_lock(&eint_lock);
 681         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 682         mask &= ~(EINT_OFFSET_BIT(data->irq));
 683         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 684         spin_unlock(&eint_lock);
 685 }
 686
 687 static inline void exynos_irq_eint_ack(struct irq_data *data)
 688 {
 689         __raw_writel(EINT_OFFSET_BIT(data->irq),
 690                      EINT_PEND(exynos_eint_base, data->irq));
 691 }
 692
 693 static void exynos_irq_eint_maskack(struct irq_data *data)
 694 {
 695         exynos_irq_eint_mask(data);
 696         exynos_irq_eint_ack(data);
 697 }
 698
 699 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 700 {
 701         int offs = EINT_OFFSET(data->irq);
 702         int shift;
 703         u32 ctrl, mask;
 704         u32 newvalue = 0;
 705
 706         switch (type) {
 707         case IRQ_TYPE_EDGE_RISING:
 708                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 709                 break;
 710
 711         case IRQ_TYPE_EDGE_FALLING:
 712                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 713                 break;
 714
 715         case IRQ_TYPE_EDGE_BOTH:
 716                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 717                 break;
 718
 719         case IRQ_TYPE_LEVEL_LOW:
 720                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 721                 break;
 722
 723         case IRQ_TYPE_LEVEL_HIGH:
 724                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 725                 break;
 726
 727         default:
 728                 printk(KERN_ERR "No such irq type %d", type);
 729                 return -EINVAL;
 730         }
 731
 732         shift = (offs & 0x7) * 4;
 733         mask = 0x7 << shift;
 734
 735         spin_lock(&eint_lock);
 736         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 737         ctrl &= ~mask;
 738         ctrl |= newvalue << shift;
 739         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 740         spin_unlock(&eint_lock);
 741
 742         if (soc_is_exynos5250())
 743                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 744         else
 745                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 746
 747         return 0;
 748 }
 749
 750 static struct irq_chip exynos_irq_eint = {
 751         .name           = "exynos-eint",
 752         .irq_mask       = exynos_irq_eint_mask,
 753         .irq_unmask     = exynos_irq_eint_unmask,
 754         .irq_mask_ack   = exynos_irq_eint_maskack,
 755         .irq_ack        = exynos_irq_eint_ack,
 756         .irq_set_type   = exynos_irq_eint_set_type,
 757 #ifdef CONFIG_PM
 758         .irq_set_wake   = s3c_irqext_wake,
 759 #endif
 760 };
 761
 762 /*
 763  * exynos4_irq_demux_eint
 764  *
 765  * This function demuxes the IRQ from from EINTs 16 to 31.
 766  * It is designed to be inlined into the specific handler
 767  * s5p_irq_demux_eintX_Y.
 768  *
 769  * Each EINT pend/mask registers handle eight of them.
 770  */
 771 static inline void exynos_irq_demux_eint(unsigned int start)
 772 {
 773         unsigned int irq;
 774
 775         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 776         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 777
 778         status &= ~mask;
 779         status &= 0xff;
 780
 781         while (status) {
 782                 irq = fls(status) - 1;
 783                 generic_handle_irq(irq + start);
 784                 status &= ~(1 << irq);
 785         }
 786 }
 787
 788 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 789 {
 790         struct irq_chip *chip = irq_get_chip(irq);
 791         chained_irq_enter(chip, desc);
 792         exynos_irq_demux_eint(IRQ_EINT(16));
 793         exynos_irq_demux_eint(IRQ_EINT(24));
 794         chained_irq_exit(chip, desc);
 795 }
 796
 797 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 798 {
 799         u32 *irq_data = irq_get_handler_data(irq);
 800         struct irq_chip *chip = irq_get_chip(irq);
 801
 802         chained_irq_enter(chip, desc);
 803         generic_handle_irq(*irq_data);
 804         chained_irq_exit(chip, desc);
 805 }
 806
 807 static int __init exynos_init_irq_eint(void)
 808 {
 809         int irq;
 810
 811 #ifdef CONFIG_PINCTRL_SAMSUNG
 812         /*
 813          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 814          * functionality along with support for external gpio and wakeup
 815          * interrupts. If the samsung pinctrl driver is enabled and includes
 816          * the wakeup interrupt support, then the setting up external wakeup
 817          * interrupts here can be skipped. This check here is temporary to
 818          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 819          * co-exist with platforms that do. When all of the Samsung Exynos4
 820          * platforms switch over to using the pinctrl driver, the wakeup
 821          * interrupt support code here can be completely removed.
 822          */
 823         static const struct of_device_id exynos_pinctrl_ids[] = {
 824                 { .compatible = "samsung,exynos4210-pinctrl", },
 825                 { .compatible = "samsung,exynos4x12-pinctrl", },
 826         };
 827         struct device_node *pctrl_np, *wkup_np;
 828         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 829
 830         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 831                 if (of_device_is_available(pctrl_np)) {
 832                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 833                                                         wkup_compat);
 834                         if (wkup_np)
 835                                 return -ENODEV;
 836                 }
 837         }
 838 #endif
 839         if (soc_is_exynos5440())
 840                 return 0;
 841
 842         if (soc_is_exynos5250())
 843                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 844         else
 845                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 846
 847         if (exynos_eint_base == NULL) {
 848                 pr_err("unable to ioremap for EINT base address\n");
 849                 return -ENOMEM;
 850         }
 851
 852         for (irq = 0 ; irq <= 31 ; irq++) {
 853                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 854                                          handle_level_irq);
 855                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 856         }
 857
 858         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 859
 860         for (irq = 0 ; irq <= 15 ; irq++) {
 861                 eint0_15_data[irq] = IRQ_EINT(irq);
 862
 863                 if (soc_is_exynos5250()) {
 864                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 865                                              &eint0_15_data[irq]);
 866                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 867                                                 exynos_irq_eint0_15);
 868                 } else {
 869                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 870                                              &eint0_15_data[irq]);
 871                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 872                                                 exynos_irq_eint0_15);
 873                 }
 874         }
 875
 876         return 0;
 877 }
 878 arch_initcall(exynos_init_irq_eint);