Pileus Git - ~andy/linux/blob - arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/bitops.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqchip.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/gpio.h>
  20 #include <clocksource/samsung_pwm.h>
  21 #include <linux/sched.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/of.h>
  24 #include <linux/of_fdt.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/export.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/of_address.h>
  29 #include <linux/clocksource.h>
  30 #include <linux/clk-provider.h>
  31 #include <linux/irqchip/arm-gic.h>
  32 #include <linux/irqchip/chained_irq.h>
  33
  34 #include <asm/proc-fns.h>
  35 #include <asm/exception.h>
  36 #include <asm/hardware/cache-l2x0.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/irq.h>
  39 #include <asm/cacheflush.h>
  40
  41 #include <mach/regs-irq.h>
  42 #include <mach/regs-pmu.h>
  43 #include <mach/regs-gpio.h>
  44 #include <mach/irqs.h>
  45
  46 #include <plat/cpu.h>
  47 #include <plat/devs.h>
  48 #include <plat/pm.h>
  49 #include <plat/sdhci.h>
  50 #include <plat/gpio-cfg.h>
  51 #include <plat/adc-core.h>
  52 #include <plat/fb-core.h>
  53 #include <plat/fimc-core.h>
  54 #include <plat/iic-core.h>
  55 #include <plat/tv-core.h>
  56 #include <plat/spi-core.h>
  57 #include <plat/regs-serial.h>
  58
  59 #include "common.h"
  60 #define L2_AUX_VAL 0x7C470001
  61 #define L2_AUX_MASK 0xC200ffff
  62
  63 static const char name_exynos4210[] = "EXYNOS4210";
  64 static const char name_exynos4212[] = "EXYNOS4212";
  65 static const char name_exynos4412[] = "EXYNOS4412";
  66 static const char name_exynos5250[] = "EXYNOS5250";
  67 static const char name_exynos5440[] = "EXYNOS5440";
  68
  69 static void exynos4_map_io(void);
  70 static void exynos5_map_io(void);
  71 static void exynos5440_map_io(void);
  72 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  73 static int exynos_init(void);
  74
  75 unsigned long xxti_f = 0, xusbxti_f = 0;
  76
  77 static struct cpu_table cpu_ids[] __initdata = {
  78         {
  79                 .idcode         = EXYNOS4210_CPU_ID,
  80                 .idmask         = EXYNOS4_CPU_MASK,
  81                 .map_io         = exynos4_map_io,
  82                 .init_uarts     = exynos4_init_uarts,
  83                 .init           = exynos_init,
  84                 .name           = name_exynos4210,
  85         }, {
  86                 .idcode         = EXYNOS4212_CPU_ID,
  87                 .idmask         = EXYNOS4_CPU_MASK,
  88                 .map_io         = exynos4_map_io,
  89                 .init_uarts     = exynos4_init_uarts,
  90                 .init           = exynos_init,
  91                 .name           = name_exynos4212,
  92         }, {
  93                 .idcode         = EXYNOS4412_CPU_ID,
  94                 .idmask         = EXYNOS4_CPU_MASK,
  95                 .map_io         = exynos4_map_io,
  96                 .init_uarts     = exynos4_init_uarts,
  97                 .init           = exynos_init,
  98                 .name           = name_exynos4412,
  99         }, {
 100                 .idcode         = EXYNOS5250_SOC_ID,
 101                 .idmask         = EXYNOS5_SOC_MASK,
 102                 .map_io         = exynos5_map_io,
 103                 .init           = exynos_init,
 104                 .name           = name_exynos5250,
 105         }, {
 106                 .idcode         = EXYNOS5440_SOC_ID,
 107                 .idmask         = EXYNOS5_SOC_MASK,
 108                 .map_io         = exynos5440_map_io,
 109                 .init           = exynos_init,
 110                 .name           = name_exynos5440,
 111         },
 112 };
 113
 114 /* Initial IO mappings */
 115
 116 static struct map_desc exynos_iodesc[] __initdata = {
 117         {
 118                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 119                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 120                 .length         = SZ_4K,
 121                 .type           = MT_DEVICE,
 122         },
 123 };
 124
 125 static struct map_desc exynos4_iodesc[] __initdata = {
 126         {
 127                 .virtual        = (unsigned long)S3C_VA_SYS,
 128                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 129                 .length         = SZ_64K,
 130                 .type           = MT_DEVICE,
 131         }, {
 132                 .virtual        = (unsigned long)S3C_VA_TIMER,
 133                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 134                 .length         = SZ_16K,
 135                 .type           = MT_DEVICE,
 136         }, {
 137                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 138                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 139                 .length         = SZ_4K,
 140                 .type           = MT_DEVICE,
 141         }, {
 142                 .virtual        = (unsigned long)S5P_VA_SROMC,
 143                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 144                 .length         = SZ_4K,
 145                 .type           = MT_DEVICE,
 146         }, {
 147                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 148                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 149                 .length         = SZ_4K,
 150                 .type           = MT_DEVICE,
 151         }, {
 152                 .virtual        = (unsigned long)S5P_VA_PMU,
 153                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 154                 .length         = SZ_64K,
 155                 .type           = MT_DEVICE,
 156         }, {
 157                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 158                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 159                 .length         = SZ_4K,
 160                 .type           = MT_DEVICE,
 161         }, {
 162                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 163                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 164                 .length         = SZ_64K,
 165                 .type           = MT_DEVICE,
 166         }, {
 167                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 168                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 169                 .length         = SZ_64K,
 170                 .type           = MT_DEVICE,
 171         }, {
 172                 .virtual        = (unsigned long)S3C_VA_UART,
 173                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 174                 .length         = SZ_512K,
 175                 .type           = MT_DEVICE,
 176         }, {
 177                 .virtual        = (unsigned long)S5P_VA_CMU,
 178                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 179                 .length         = SZ_128K,
 180                 .type           = MT_DEVICE,
 181         }, {
 182                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 183                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 184                 .length         = SZ_8K,
 185                 .type           = MT_DEVICE,
 186         }, {
 187                 .virtual        = (unsigned long)S5P_VA_L2CC,
 188                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 189                 .length         = SZ_4K,
 190                 .type           = MT_DEVICE,
 191         }, {
 192                 .virtual        = (unsigned long)S5P_VA_DMC0,
 193                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 194                 .length         = SZ_64K,
 195                 .type           = MT_DEVICE,
 196         }, {
 197                 .virtual        = (unsigned long)S5P_VA_DMC1,
 198                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 199                 .length         = SZ_64K,
 200                 .type           = MT_DEVICE,
 201         }, {
 202                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 203                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 204                 .length         = SZ_4K,
 205                 .type           = MT_DEVICE,
 206         },
 207 };
 208
 209 static struct map_desc exynos4_iodesc0[] __initdata = {
 210         {
 211                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 212                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 213                 .length         = SZ_4K,
 214                 .type           = MT_DEVICE,
 215         },
 216 };
 217
 218 static struct map_desc exynos4_iodesc1[] __initdata = {
 219         {
 220                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 221                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 222                 .length         = SZ_4K,
 223                 .type           = MT_DEVICE,
 224         },
 225 };
 226
 227 static struct map_desc exynos4210_iodesc[] __initdata = {
 228         {
 229                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 230                 .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
 231                 .length         = SZ_4K,
 232                 .type           = MT_DEVICE,
 233         },
 234 };
 235
 236 static struct map_desc exynos4x12_iodesc[] __initdata = {
 237         {
 238                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 239                 .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
 240                 .length         = SZ_4K,
 241                 .type           = MT_DEVICE,
 242         },
 243 };
 244
 245 static struct map_desc exynos5250_iodesc[] __initdata = {
 246         {
 247                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 248                 .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
 249                 .length         = SZ_4K,
 250                 .type           = MT_DEVICE,
 251         },
 252 };
 253
 254 static struct map_desc exynos5_iodesc[] __initdata = {
 255         {
 256                 .virtual        = (unsigned long)S3C_VA_SYS,
 257                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 258                 .length         = SZ_64K,
 259                 .type           = MT_DEVICE,
 260         }, {
 261                 .virtual        = (unsigned long)S3C_VA_TIMER,
 262                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 263                 .length         = SZ_16K,
 264                 .type           = MT_DEVICE,
 265         }, {
 266                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 267                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 268                 .length         = SZ_4K,
 269                 .type           = MT_DEVICE,
 270         }, {
 271                 .virtual        = (unsigned long)S5P_VA_SROMC,
 272                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 273                 .length         = SZ_4K,
 274                 .type           = MT_DEVICE,
 275         }, {
 276                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 277                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 278                 .length         = SZ_4K,
 279                 .type           = MT_DEVICE,
 280         }, {
 281                 .virtual        = (unsigned long)S5P_VA_CMU,
 282                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 283                 .length         = 144 * SZ_1K,
 284                 .type           = MT_DEVICE,
 285         }, {
 286                 .virtual        = (unsigned long)S5P_VA_PMU,
 287                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 288                 .length         = SZ_64K,
 289                 .type           = MT_DEVICE,
 290         }, {
 291                 .virtual        = (unsigned long)S3C_VA_UART,
 292                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 293                 .length         = SZ_512K,
 294                 .type           = MT_DEVICE,
 295         },
 296 };
 297
 298 static struct map_desc exynos5440_iodesc0[] __initdata = {
 299         {
 300                 .virtual        = (unsigned long)S3C_VA_UART,
 301                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 302                 .length         = SZ_512K,
 303                 .type           = MT_DEVICE,
 304         },
 305 };
 306
 307 static struct samsung_pwm_variant exynos4_pwm_variant = {
 308         .bits           = 32,
 309         .div_base       = 0,
 310         .has_tint_cstat = true,
 311         .tclk_mask      = 0,
 312 };
 313
 314 void exynos4_restart(char mode, const char *cmd)
 315 {
 316         __raw_writel(0x1, S5P_SWRESET);
 317 }
 318
 319 void exynos5_restart(char mode, const char *cmd)
 320 {
 321         struct device_node *np;
 322         u32 val;
 323         void __iomem *addr;
 324
 325         if (of_machine_is_compatible("samsung,exynos5250")) {
 326                 val = 0x1;
 327                 addr = EXYNOS_SWRESET;
 328         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 329                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 330                 addr = of_iomap(np, 0) + 0xcc;
 331                 val = (0xfff << 20) | (0x1 << 16);
 332         } else {
 333                 pr_err("%s: cannot support non-DT\n", __func__);
 334                 return;
 335         }
 336
 337         __raw_writel(val, addr);
 338 }
 339
 340 void __init exynos_init_late(void)
 341 {
 342         if (of_machine_is_compatible("samsung,exynos5440"))
 343                 /* to be supported later */
 344                 return;
 345
 346         exynos_pm_late_initcall();
 347 }
 348
 349 #ifdef CONFIG_OF
 350 int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 351                                         int depth, void *data)
 352 {
 353         struct map_desc iodesc;
 354         __be32 *reg;
 355         unsigned long len;
 356
 357         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 358                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 359                 return 0;
 360
 361         reg = of_get_flat_dt_prop(node, "reg", &len);
 362         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 363                 return 0;
 364
 365         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 366         iodesc.length = be32_to_cpu(reg[1]) - 1;
 367         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 368         iodesc.type = MT_DEVICE;
 369         iotable_init(&iodesc, 1);
 370         return 1;
 371 }
 372 #endif
 373
 374 /*
 375  * exynos_map_io
 376  *
 377  * register the standard cpu IO areas
 378  */
 379
 380 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 381 {
 382 #ifdef CONFIG_OF
 383         if (initial_boot_params)
 384                 of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 385         else
 386 #endif
 387                 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 388
 389         if (mach_desc)
 390                 iotable_init(mach_desc, size);
 391
 392         /* detect cpu id and rev. */
 393         s5p_init_cpu(S5P_VA_CHIPID);
 394
 395         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 396 }
 397
 398 static void __init exynos4_map_io(void)
 399 {
 400         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 401
 402         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 403                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 404         else
 405                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 406
 407         if (soc_is_exynos4210())
 408                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
 409         if (soc_is_exynos4212() || soc_is_exynos4412())
 410                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
 411
 412         /* initialize device information early */
 413         exynos4_default_sdhci0();
 414         exynos4_default_sdhci1();
 415         exynos4_default_sdhci2();
 416         exynos4_default_sdhci3();
 417
 418         s3c_adc_setname("samsung-adc-v3");
 419
 420         s3c_fimc_setname(0, "exynos4-fimc");
 421         s3c_fimc_setname(1, "exynos4-fimc");
 422         s3c_fimc_setname(2, "exynos4-fimc");
 423         s3c_fimc_setname(3, "exynos4-fimc");
 424
 425         s3c_sdhci_setname(0, "exynos4-sdhci");
 426         s3c_sdhci_setname(1, "exynos4-sdhci");
 427         s3c_sdhci_setname(2, "exynos4-sdhci");
 428         s3c_sdhci_setname(3, "exynos4-sdhci");
 429
 430         /* The I2C bus controllers are directly compatible with s3c2440 */
 431         s3c_i2c0_setname("s3c2440-i2c");
 432         s3c_i2c1_setname("s3c2440-i2c");
 433         s3c_i2c2_setname("s3c2440-i2c");
 434
 435         s5p_fb_setname(0, "exynos4-fb");
 436         s5p_hdmi_setname("exynos4-hdmi");
 437
 438         s3c64xx_spi_setname("exynos4210-spi");
 439 }
 440
 441 static void __init exynos5_map_io(void)
 442 {
 443         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 444
 445         if (soc_is_exynos5250())
 446                 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 447 }
 448
 449 static void __init exynos5440_map_io(void)
 450 {
 451         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 452 }
 453
 454 void __init exynos_set_timer_source(u8 channels)
 455 {
 456         exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 457         exynos4_pwm_variant.output_mask &= ~channels;
 458 }
 459
 460 void __init exynos_init_time(void)
 461 {
 462         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 463                 EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC,
 464                 EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
 465                 EXYNOS4_IRQ_TIMER4_VIC,
 466         };
 467
 468         if (of_have_populated_dt()) {
 469 #ifdef CONFIG_OF
 470                 of_clk_init(NULL);
 471                 clocksource_of_init();
 472 #endif
 473         } else {
 474                 /* todo: remove after migrating legacy E4 platforms to dt */
 475 #ifdef CONFIG_ARCH_EXYNOS4
 476                 exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
 477                 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 478 #endif
 479 #ifdef CONFIG_CLKSRC_SAMSUNG_PWM
 480                 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 481                         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 482                                         timer_irqs, &exynos4_pwm_variant);
 483                 else
 484 #endif
 485                         mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
 486                                         EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
 487         }
 488 }
 489
 490 static unsigned int max_combiner_nr(void)
 491 {
 492         if (soc_is_exynos5250())
 493                 return EXYNOS5_MAX_COMBINER_NR;
 494         else if (soc_is_exynos4412())
 495                 return EXYNOS4412_MAX_COMBINER_NR;
 496         else if (soc_is_exynos4212())
 497                 return EXYNOS4212_MAX_COMBINER_NR;
 498         else
 499                 return EXYNOS4210_MAX_COMBINER_NR;
 500 }
 501
 502
 503 void __init exynos4_init_irq(void)
 504 {
 505         unsigned int gic_bank_offset;
 506
 507         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 508
 509         if (!of_have_populated_dt())
 510                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 511 #ifdef CONFIG_OF
 512         else
 513                 irqchip_init();
 514 #endif
 515
 516         if (!of_have_populated_dt())
 517                 combiner_init(S5P_VA_COMBINER_BASE, NULL,
 518                               max_combiner_nr(), COMBINER_IRQ(0, 0));
 519
 520         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 521 }
 522
 523 void __init exynos5_init_irq(void)
 524 {
 525 #ifdef CONFIG_OF
 526         irqchip_init();
 527 #endif
 528         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 529 }
 530
 531 struct bus_type exynos_subsys = {
 532         .name           = "exynos-core",
 533         .dev_name       = "exynos-core",
 534 };
 535
 536 static struct device exynos4_dev = {
 537         .bus    = &exynos_subsys,
 538 };
 539
 540 static int __init exynos_core_init(void)
 541 {
 542         return subsys_system_register(&exynos_subsys, NULL);
 543 }
 544 core_initcall(exynos_core_init);
 545
 546 #ifdef CONFIG_CACHE_L2X0
 547 static int __init exynos4_l2x0_cache_init(void)
 548 {
 549         int ret;
 550
 551         if (soc_is_exynos5250() || soc_is_exynos5440())
 552                 return 0;
 553
 554         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 555         if (!ret) {
 556                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 557                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 558                 return 0;
 559         }
 560
 561         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 562                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 563                 /* TAG, Data Latency Control: 2 cycles */
 564                 l2x0_saved_regs.tag_latency = 0x110;
 565
 566                 if (soc_is_exynos4212() || soc_is_exynos4412())
 567                         l2x0_saved_regs.data_latency = 0x120;
 568                 else
 569                         l2x0_saved_regs.data_latency = 0x110;
 570
 571                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 572                 l2x0_saved_regs.pwr_ctrl =
 573                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 574
 575                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 576
 577                 __raw_writel(l2x0_saved_regs.tag_latency,
 578                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 579                 __raw_writel(l2x0_saved_regs.data_latency,
 580                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 581
 582                 /* L2X0 Prefetch Control */
 583                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 584                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 585
 586                 /* L2X0 Power Control */
 587                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 588                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 589
 590                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 591                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 592         }
 593
 594         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 595         return 0;
 596 }
 597 early_initcall(exynos4_l2x0_cache_init);
 598 #endif
 599
 600 static int __init exynos_init(void)
 601 {
 602         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 603
 604         return device_register(&exynos4_dev);
 605 }
 606
 607 /* uart registration process */
 608
 609 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 610 {
 611         struct s3c2410_uartcfg *tcfg = cfg;
 612         u32 ucnt;
 613
 614         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 615                 tcfg->has_fracval = 1;
 616
 617         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 618 }
 619
 620 static void __iomem *exynos_eint_base;
 621
 622 static DEFINE_SPINLOCK(eint_lock);
 623
 624 static unsigned int eint0_15_data[16];
 625
 626 static inline int exynos4_irq_to_gpio(unsigned int irq)
 627 {
 628         if (irq < IRQ_EINT(0))
 629                 return -EINVAL;
 630
 631         irq -= IRQ_EINT(0);
 632         if (irq < 8)
 633                 return EXYNOS4_GPX0(irq);
 634
 635         irq -= 8;
 636         if (irq < 8)
 637                 return EXYNOS4_GPX1(irq);
 638
 639         irq -= 8;
 640         if (irq < 8)
 641                 return EXYNOS4_GPX2(irq);
 642
 643         irq -= 8;
 644         if (irq < 8)
 645                 return EXYNOS4_GPX3(irq);
 646
 647         return -EINVAL;
 648 }
 649
 650 static inline int exynos5_irq_to_gpio(unsigned int irq)
 651 {
 652         if (irq < IRQ_EINT(0))
 653                 return -EINVAL;
 654
 655         irq -= IRQ_EINT(0);
 656         if (irq < 8)
 657                 return EXYNOS5_GPX0(irq);
 658
 659         irq -= 8;
 660         if (irq < 8)
 661                 return EXYNOS5_GPX1(irq);
 662
 663         irq -= 8;
 664         if (irq < 8)
 665                 return EXYNOS5_GPX2(irq);
 666
 667         irq -= 8;
 668         if (irq < 8)
 669                 return EXYNOS5_GPX3(irq);
 670
 671         return -EINVAL;
 672 }
 673
 674 static unsigned int exynos4_eint0_15_src_int[16] = {
 675         EXYNOS4_IRQ_EINT0,
 676         EXYNOS4_IRQ_EINT1,
 677         EXYNOS4_IRQ_EINT2,
 678         EXYNOS4_IRQ_EINT3,
 679         EXYNOS4_IRQ_EINT4,
 680         EXYNOS4_IRQ_EINT5,
 681         EXYNOS4_IRQ_EINT6,
 682         EXYNOS4_IRQ_EINT7,
 683         EXYNOS4_IRQ_EINT8,
 684         EXYNOS4_IRQ_EINT9,
 685         EXYNOS4_IRQ_EINT10,
 686         EXYNOS4_IRQ_EINT11,
 687         EXYNOS4_IRQ_EINT12,
 688         EXYNOS4_IRQ_EINT13,
 689         EXYNOS4_IRQ_EINT14,
 690         EXYNOS4_IRQ_EINT15,
 691 };
 692
 693 static unsigned int exynos5_eint0_15_src_int[16] = {
 694         EXYNOS5_IRQ_EINT0,
 695         EXYNOS5_IRQ_EINT1,
 696         EXYNOS5_IRQ_EINT2,
 697         EXYNOS5_IRQ_EINT3,
 698         EXYNOS5_IRQ_EINT4,
 699         EXYNOS5_IRQ_EINT5,
 700         EXYNOS5_IRQ_EINT6,
 701         EXYNOS5_IRQ_EINT7,
 702         EXYNOS5_IRQ_EINT8,
 703         EXYNOS5_IRQ_EINT9,
 704         EXYNOS5_IRQ_EINT10,
 705         EXYNOS5_IRQ_EINT11,
 706         EXYNOS5_IRQ_EINT12,
 707         EXYNOS5_IRQ_EINT13,
 708         EXYNOS5_IRQ_EINT14,
 709         EXYNOS5_IRQ_EINT15,
 710 };
 711 static inline void exynos_irq_eint_mask(struct irq_data *data)
 712 {
 713         u32 mask;
 714
 715         spin_lock(&eint_lock);
 716         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 717         mask |= EINT_OFFSET_BIT(data->irq);
 718         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 719         spin_unlock(&eint_lock);
 720 }
 721
 722 static void exynos_irq_eint_unmask(struct irq_data *data)
 723 {
 724         u32 mask;
 725
 726         spin_lock(&eint_lock);
 727         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 728         mask &= ~(EINT_OFFSET_BIT(data->irq));
 729         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 730         spin_unlock(&eint_lock);
 731 }
 732
 733 static inline void exynos_irq_eint_ack(struct irq_data *data)
 734 {
 735         __raw_writel(EINT_OFFSET_BIT(data->irq),
 736                      EINT_PEND(exynos_eint_base, data->irq));
 737 }
 738
 739 static void exynos_irq_eint_maskack(struct irq_data *data)
 740 {
 741         exynos_irq_eint_mask(data);
 742         exynos_irq_eint_ack(data);
 743 }
 744
 745 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 746 {
 747         int offs = EINT_OFFSET(data->irq);
 748         int shift;
 749         u32 ctrl, mask;
 750         u32 newvalue = 0;
 751
 752         switch (type) {
 753         case IRQ_TYPE_EDGE_RISING:
 754                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 755                 break;
 756
 757         case IRQ_TYPE_EDGE_FALLING:
 758                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 759                 break;
 760
 761         case IRQ_TYPE_EDGE_BOTH:
 762                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 763                 break;
 764
 765         case IRQ_TYPE_LEVEL_LOW:
 766                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 767                 break;
 768
 769         case IRQ_TYPE_LEVEL_HIGH:
 770                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 771                 break;
 772
 773         default:
 774                 printk(KERN_ERR "No such irq type %d", type);
 775                 return -EINVAL;
 776         }
 777
 778         shift = (offs & 0x7) * 4;
 779         mask = 0x7 << shift;
 780
 781         spin_lock(&eint_lock);
 782         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 783         ctrl &= ~mask;
 784         ctrl |= newvalue << shift;
 785         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 786         spin_unlock(&eint_lock);
 787
 788         if (soc_is_exynos5250())
 789                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 790         else
 791                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 792
 793         return 0;
 794 }
 795
 796 static struct irq_chip exynos_irq_eint = {
 797         .name           = "exynos-eint",
 798         .irq_mask       = exynos_irq_eint_mask,
 799         .irq_unmask     = exynos_irq_eint_unmask,
 800         .irq_mask_ack   = exynos_irq_eint_maskack,
 801         .irq_ack        = exynos_irq_eint_ack,
 802         .irq_set_type   = exynos_irq_eint_set_type,
 803 #ifdef CONFIG_PM
 804         .irq_set_wake   = s3c_irqext_wake,
 805 #endif
 806 };
 807
 808 /*
 809  * exynos4_irq_demux_eint
 810  *
 811  * This function demuxes the IRQ from from EINTs 16 to 31.
 812  * It is designed to be inlined into the specific handler
 813  * s5p_irq_demux_eintX_Y.
 814  *
 815  * Each EINT pend/mask registers handle eight of them.
 816  */
 817 static inline void exynos_irq_demux_eint(unsigned int start)
 818 {
 819         unsigned int irq;
 820
 821         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 822         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 823
 824         status &= ~mask;
 825         status &= 0xff;
 826
 827         while (status) {
 828                 irq = fls(status) - 1;
 829                 generic_handle_irq(irq + start);
 830                 status &= ~(1 << irq);
 831         }
 832 }
 833
 834 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 835 {
 836         struct irq_chip *chip = irq_get_chip(irq);
 837         chained_irq_enter(chip, desc);
 838         exynos_irq_demux_eint(IRQ_EINT(16));
 839         exynos_irq_demux_eint(IRQ_EINT(24));
 840         chained_irq_exit(chip, desc);
 841 }
 842
 843 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 844 {
 845         u32 *irq_data = irq_get_handler_data(irq);
 846         struct irq_chip *chip = irq_get_chip(irq);
 847
 848         chained_irq_enter(chip, desc);
 849         generic_handle_irq(*irq_data);
 850         chained_irq_exit(chip, desc);
 851 }
 852
 853 static int __init exynos_init_irq_eint(void)
 854 {
 855         int irq;
 856
 857 #ifdef CONFIG_PINCTRL_SAMSUNG
 858         /*
 859          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 860          * functionality along with support for external gpio and wakeup
 861          * interrupts. If the samsung pinctrl driver is enabled and includes
 862          * the wakeup interrupt support, then the setting up external wakeup
 863          * interrupts here can be skipped. This check here is temporary to
 864          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 865          * co-exist with platforms that do. When all of the Samsung Exynos4
 866          * platforms switch over to using the pinctrl driver, the wakeup
 867          * interrupt support code here can be completely removed.
 868          */
 869         static const struct of_device_id exynos_pinctrl_ids[] = {
 870                 { .compatible = "samsung,exynos4210-pinctrl", },
 871                 { .compatible = "samsung,exynos4x12-pinctrl", },
 872                 { .compatible = "samsung,exynos5250-pinctrl", },
 873         };
 874         struct device_node *pctrl_np, *wkup_np;
 875         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 876
 877         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 878                 if (of_device_is_available(pctrl_np)) {
 879                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 880                                                         wkup_compat);
 881                         if (wkup_np)
 882                                 return -ENODEV;
 883                 }
 884         }
 885 #endif
 886         if (soc_is_exynos5440())
 887                 return 0;
 888
 889         if (soc_is_exynos5250())
 890                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 891         else
 892                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 893
 894         if (exynos_eint_base == NULL) {
 895                 pr_err("unable to ioremap for EINT base address\n");
 896                 return -ENOMEM;
 897         }
 898
 899         for (irq = 0 ; irq <= 31 ; irq++) {
 900                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 901                                          handle_level_irq);
 902                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 903         }
 904
 905         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 906
 907         for (irq = 0 ; irq <= 15 ; irq++) {
 908                 eint0_15_data[irq] = IRQ_EINT(irq);
 909
 910                 if (soc_is_exynos5250()) {
 911                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 912                                              &eint0_15_data[irq]);
 913                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 914                                                 exynos_irq_eint0_15);
 915                 } else {
 916                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 917                                              &eint0_15_data[irq]);
 918                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 919                                                 exynos_irq_eint0_15);
 920                 }
 921         }
 922
 923         return 0;
 924 }
 925 arch_initcall(exynos_init_irq_eint);
 926
 927 static struct resource exynos4_pmu_resource[] = {
 928         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
 929         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
 930 #if defined(CONFIG_SOC_EXYNOS4412)
 931         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
 932         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
 933 #endif
 934 };
 935
 936 static struct platform_device exynos4_device_pmu = {
 937         .name           = "arm-pmu",
 938         .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
 939         .resource       = exynos4_pmu_resource,
 940 };
 941
 942 static int __init exynos_armpmu_init(void)
 943 {
 944         if (!of_have_populated_dt()) {
 945                 if (soc_is_exynos4210() || soc_is_exynos4212())
 946                         exynos4_device_pmu.num_resources = 2;
 947                 platform_device_register(&exynos4_device_pmu);
 948         }
 949
 950         return 0;
 951 }
 952 arch_initcall(exynos_armpmu_init);