Pileus Git - ~andy/linux/blob - arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/sched.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/export.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/of_address.h>
  25
  26 #include <asm/proc-fns.h>
  27 #include <asm/exception.h>
  28 #include <asm/hardware/cache-l2x0.h>
  29 #include <asm/hardware/gic.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/irq.h>
  32 #include <asm/cacheflush.h>
  33
  34 #include <mach/regs-irq.h>
  35 #include <mach/regs-pmu.h>
  36 #include <mach/regs-gpio.h>
  37 #include <mach/pmu.h>
  38
  39 #include <plat/cpu.h>
  40 #include <plat/clock.h>
  41 #include <plat/devs.h>
  42 #include <plat/pm.h>
  43 #include <plat/sdhci.h>
  44 #include <plat/gpio-cfg.h>
  45 #include <plat/adc-core.h>
  46 #include <plat/fb-core.h>
  47 #include <plat/fimc-core.h>
  48 #include <plat/iic-core.h>
  49 #include <plat/tv-core.h>
  50 #include <plat/spi-core.h>
  51 #include <plat/regs-serial.h>
  52
  53 #include "common.h"
  54 #define L2_AUX_VAL 0x7C470001
  55 #define L2_AUX_MASK 0xC200ffff
  56
  57 static const char name_exynos4210[] = "EXYNOS4210";
  58 static const char name_exynos4212[] = "EXYNOS4212";
  59 static const char name_exynos4412[] = "EXYNOS4412";
  60 static const char name_exynos5250[] = "EXYNOS5250";
  61
  62 static void exynos4_map_io(void);
  63 static void exynos5_map_io(void);
  64 static void exynos4_init_clocks(int xtal);
  65 static void exynos5_init_clocks(int xtal);
  66 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  67 static int exynos_init(void);
  68
  69 static struct cpu_table cpu_ids[] __initdata = {
  70         {
  71                 .idcode         = EXYNOS4210_CPU_ID,
  72                 .idmask         = EXYNOS4_CPU_MASK,
  73                 .map_io         = exynos4_map_io,
  74                 .init_clocks    = exynos4_init_clocks,
  75                 .init_uarts     = exynos4_init_uarts,
  76                 .init           = exynos_init,
  77                 .name           = name_exynos4210,
  78         }, {
  79                 .idcode         = EXYNOS4212_CPU_ID,
  80                 .idmask         = EXYNOS4_CPU_MASK,
  81                 .map_io         = exynos4_map_io,
  82                 .init_clocks    = exynos4_init_clocks,
  83                 .init_uarts     = exynos4_init_uarts,
  84                 .init           = exynos_init,
  85                 .name           = name_exynos4212,
  86         }, {
  87                 .idcode         = EXYNOS4412_CPU_ID,
  88                 .idmask         = EXYNOS4_CPU_MASK,
  89                 .map_io         = exynos4_map_io,
  90                 .init_clocks    = exynos4_init_clocks,
  91                 .init_uarts     = exynos4_init_uarts,
  92                 .init           = exynos_init,
  93                 .name           = name_exynos4412,
  94         }, {
  95                 .idcode         = EXYNOS5250_SOC_ID,
  96                 .idmask         = EXYNOS5_SOC_MASK,
  97                 .map_io         = exynos5_map_io,
  98                 .init_clocks    = exynos5_init_clocks,
  99                 .init           = exynos_init,
 100                 .name           = name_exynos5250,
 101         },
 102 };
 103
 104 /* Initial IO mappings */
 105
 106 static struct map_desc exynos_iodesc[] __initdata = {
 107         {
 108                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 109                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 110                 .length         = SZ_4K,
 111                 .type           = MT_DEVICE,
 112         },
 113 };
 114
 115 static struct map_desc exynos4_iodesc[] __initdata = {
 116         {
 117                 .virtual        = (unsigned long)S3C_VA_SYS,
 118                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 119                 .length         = SZ_64K,
 120                 .type           = MT_DEVICE,
 121         }, {
 122                 .virtual        = (unsigned long)S3C_VA_TIMER,
 123                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 124                 .length         = SZ_16K,
 125                 .type           = MT_DEVICE,
 126         }, {
 127                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 128                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 129                 .length         = SZ_4K,
 130                 .type           = MT_DEVICE,
 131         }, {
 132                 .virtual        = (unsigned long)S5P_VA_SROMC,
 133                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 134                 .length         = SZ_4K,
 135                 .type           = MT_DEVICE,
 136         }, {
 137                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 138                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 139                 .length         = SZ_4K,
 140                 .type           = MT_DEVICE,
 141         }, {
 142                 .virtual        = (unsigned long)S5P_VA_PMU,
 143                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 144                 .length         = SZ_64K,
 145                 .type           = MT_DEVICE,
 146         }, {
 147                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 148                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 149                 .length         = SZ_4K,
 150                 .type           = MT_DEVICE,
 151         }, {
 152                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 153                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 154                 .length         = SZ_64K,
 155                 .type           = MT_DEVICE,
 156         }, {
 157                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 158                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 159                 .length         = SZ_64K,
 160                 .type           = MT_DEVICE,
 161         }, {
 162                 .virtual        = (unsigned long)S3C_VA_UART,
 163                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 164                 .length         = SZ_512K,
 165                 .type           = MT_DEVICE,
 166         }, {
 167                 .virtual        = (unsigned long)S5P_VA_CMU,
 168                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 169                 .length         = SZ_128K,
 170                 .type           = MT_DEVICE,
 171         }, {
 172                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 173                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 174                 .length         = SZ_8K,
 175                 .type           = MT_DEVICE,
 176         }, {
 177                 .virtual        = (unsigned long)S5P_VA_L2CC,
 178                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 179                 .length         = SZ_4K,
 180                 .type           = MT_DEVICE,
 181         }, {
 182                 .virtual        = (unsigned long)S5P_VA_DMC0,
 183                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 184                 .length         = SZ_64K,
 185                 .type           = MT_DEVICE,
 186         }, {
 187                 .virtual        = (unsigned long)S5P_VA_DMC1,
 188                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 189                 .length         = SZ_64K,
 190                 .type           = MT_DEVICE,
 191         }, {
 192                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 193                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 194                 .length         = SZ_4K,
 195                 .type           = MT_DEVICE,
 196         },
 197 };
 198
 199 static struct map_desc exynos4_iodesc0[] __initdata = {
 200         {
 201                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 202                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 203                 .length         = SZ_4K,
 204                 .type           = MT_DEVICE,
 205         },
 206 };
 207
 208 static struct map_desc exynos4_iodesc1[] __initdata = {
 209         {
 210                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 211                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 212                 .length         = SZ_4K,
 213                 .type           = MT_DEVICE,
 214         },
 215 };
 216
 217 static struct map_desc exynos5_iodesc[] __initdata = {
 218         {
 219                 .virtual        = (unsigned long)S3C_VA_SYS,
 220                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 221                 .length         = SZ_64K,
 222                 .type           = MT_DEVICE,
 223         }, {
 224                 .virtual        = (unsigned long)S3C_VA_TIMER,
 225                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 226                 .length         = SZ_16K,
 227                 .type           = MT_DEVICE,
 228         }, {
 229                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 230                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 231                 .length         = SZ_4K,
 232                 .type           = MT_DEVICE,
 233         }, {
 234                 .virtual        = (unsigned long)S5P_VA_SROMC,
 235                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 236                 .length         = SZ_4K,
 237                 .type           = MT_DEVICE,
 238         }, {
 239                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 240                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
 241                 .length         = SZ_4K,
 242                 .type           = MT_DEVICE,
 243         }, {
 244                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 245                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 246                 .length         = SZ_4K,
 247                 .type           = MT_DEVICE,
 248         }, {
 249                 .virtual        = (unsigned long)S5P_VA_CMU,
 250                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 251                 .length         = 144 * SZ_1K,
 252                 .type           = MT_DEVICE,
 253         }, {
 254                 .virtual        = (unsigned long)S5P_VA_PMU,
 255                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 256                 .length         = SZ_64K,
 257                 .type           = MT_DEVICE,
 258         }, {
 259                 .virtual        = (unsigned long)S3C_VA_UART,
 260                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 261                 .length         = SZ_512K,
 262                 .type           = MT_DEVICE,
 263         },
 264 };
 265
 266 void exynos4_restart(char mode, const char *cmd)
 267 {
 268         __raw_writel(0x1, S5P_SWRESET);
 269 }
 270
 271 void exynos5_restart(char mode, const char *cmd)
 272 {
 273         __raw_writel(0x1, EXYNOS_SWRESET);
 274 }
 275
 276 void __init exynos_init_late(void)
 277 {
 278         exynos_pm_late_initcall();
 279 }
 280
 281 /*
 282  * exynos_map_io
 283  *
 284  * register the standard cpu IO areas
 285  */
 286
 287 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 288 {
 289         /* initialize the io descriptors we need for initialization */
 290         iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 291         if (mach_desc)
 292                 iotable_init(mach_desc, size);
 293
 294         /* detect cpu id and rev. */
 295         s5p_init_cpu(S5P_VA_CHIPID);
 296
 297         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 298 }
 299
 300 static void __init exynos4_map_io(void)
 301 {
 302         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 303
 304         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 305                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 306         else
 307                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 308
 309         /* initialize device information early */
 310         exynos4_default_sdhci0();
 311         exynos4_default_sdhci1();
 312         exynos4_default_sdhci2();
 313         exynos4_default_sdhci3();
 314
 315         s3c_adc_setname("samsung-adc-v3");
 316
 317         s3c_fimc_setname(0, "exynos4-fimc");
 318         s3c_fimc_setname(1, "exynos4-fimc");
 319         s3c_fimc_setname(2, "exynos4-fimc");
 320         s3c_fimc_setname(3, "exynos4-fimc");
 321
 322         s3c_sdhci_setname(0, "exynos4-sdhci");
 323         s3c_sdhci_setname(1, "exynos4-sdhci");
 324         s3c_sdhci_setname(2, "exynos4-sdhci");
 325         s3c_sdhci_setname(3, "exynos4-sdhci");
 326
 327         /* The I2C bus controllers are directly compatible with s3c2440 */
 328         s3c_i2c0_setname("s3c2440-i2c");
 329         s3c_i2c1_setname("s3c2440-i2c");
 330         s3c_i2c2_setname("s3c2440-i2c");
 331
 332         s5p_fb_setname(0, "exynos4-fb");
 333         s5p_hdmi_setname("exynos4-hdmi");
 334
 335         s3c64xx_spi_setname("exynos4210-spi");
 336 }
 337
 338 static void __init exynos5_map_io(void)
 339 {
 340         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 341 }
 342
 343 static void __init exynos4_init_clocks(int xtal)
 344 {
 345         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 346
 347         s3c24xx_register_baseclocks(xtal);
 348         s5p_register_clocks(xtal);
 349
 350         if (soc_is_exynos4210())
 351                 exynos4210_register_clocks();
 352         else if (soc_is_exynos4212() || soc_is_exynos4412())
 353                 exynos4212_register_clocks();
 354
 355         exynos4_register_clocks();
 356         exynos4_setup_clocks();
 357 }
 358
 359 static void __init exynos5_init_clocks(int xtal)
 360 {
 361         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 362
 363         s3c24xx_register_baseclocks(xtal);
 364         s5p_register_clocks(xtal);
 365
 366         exynos5_register_clocks();
 367         exynos5_setup_clocks();
 368 }
 369
 370 #define COMBINER_ENABLE_SET     0x0
 371 #define COMBINER_ENABLE_CLEAR   0x4
 372 #define COMBINER_INT_STATUS     0xC
 373
 374 static DEFINE_SPINLOCK(irq_controller_lock);
 375
 376 struct combiner_chip_data {
 377         unsigned int irq_offset;
 378         unsigned int irq_mask;
 379         void __iomem *base;
 380 };
 381
 382 static struct irq_domain *combiner_irq_domain;
 383 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 384
 385 static inline void __iomem *combiner_base(struct irq_data *data)
 386 {
 387         struct combiner_chip_data *combiner_data =
 388                 irq_data_get_irq_chip_data(data);
 389
 390         return combiner_data->base;
 391 }
 392
 393 static void combiner_mask_irq(struct irq_data *data)
 394 {
 395         u32 mask = 1 << (data->hwirq % 32);
 396
 397         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 398 }
 399
 400 static void combiner_unmask_irq(struct irq_data *data)
 401 {
 402         u32 mask = 1 << (data->hwirq % 32);
 403
 404         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 405 }
 406
 407 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 408 {
 409         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
 410         struct irq_chip *chip = irq_get_chip(irq);
 411         unsigned int cascade_irq, combiner_irq;
 412         unsigned long status;
 413
 414         chained_irq_enter(chip, desc);
 415
 416         spin_lock(&irq_controller_lock);
 417         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
 418         spin_unlock(&irq_controller_lock);
 419         status &= chip_data->irq_mask;
 420
 421         if (status == 0)
 422                 goto out;
 423
 424         combiner_irq = __ffs(status);
 425
 426         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
 427         if (unlikely(cascade_irq >= NR_IRQS))
 428                 do_bad_IRQ(cascade_irq, desc);
 429         else
 430                 generic_handle_irq(cascade_irq);
 431
 432  out:
 433         chained_irq_exit(chip, desc);
 434 }
 435
 436 static struct irq_chip combiner_chip = {
 437         .name           = "COMBINER",
 438         .irq_mask       = combiner_mask_irq,
 439         .irq_unmask     = combiner_unmask_irq,
 440 };
 441
 442 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 443 {
 444         unsigned int max_nr;
 445
 446         if (soc_is_exynos5250())
 447                 max_nr = EXYNOS5_MAX_COMBINER_NR;
 448         else
 449                 max_nr = EXYNOS4_MAX_COMBINER_NR;
 450
 451         if (combiner_nr >= max_nr)
 452                 BUG();
 453         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 454                 BUG();
 455         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 456 }
 457
 458 static void __init combiner_init_one(unsigned int combiner_nr,
 459                                      void __iomem *base)
 460 {
 461         combiner_data[combiner_nr].base = base;
 462         combiner_data[combiner_nr].irq_offset = irq_find_mapping(
 463                 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 464         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 465
 466         /* Disable all interrupts */
 467         __raw_writel(combiner_data[combiner_nr].irq_mask,
 468                      base + COMBINER_ENABLE_CLEAR);
 469 }
 470
 471 #ifdef CONFIG_OF
 472 static int combiner_irq_domain_xlate(struct irq_domain *d,
 473                                      struct device_node *controller,
 474                                      const u32 *intspec, unsigned int intsize,
 475                                      unsigned long *out_hwirq,
 476                                      unsigned int *out_type)
 477 {
 478         if (d->of_node != controller)
 479                 return -EINVAL;
 480
 481         if (intsize < 2)
 482                 return -EINVAL;
 483
 484         *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
 485         *out_type = 0;
 486
 487         return 0;
 488 }
 489 #else
 490 static int combiner_irq_domain_xlate(struct irq_domain *d,
 491                                      struct device_node *controller,
 492                                      const u32 *intspec, unsigned int intsize,
 493                                      unsigned long *out_hwirq,
 494                                      unsigned int *out_type)
 495 {
 496         return -EINVAL;
 497 }
 498 #endif
 499
 500 static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
 501                                    irq_hw_number_t hw)
 502 {
 503         irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
 504         irq_set_chip_data(irq, &combiner_data[hw >> 3]);
 505         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 506
 507         return 0;
 508 }
 509
 510 static struct irq_domain_ops combiner_irq_domain_ops = {
 511         .xlate  = combiner_irq_domain_xlate,
 512         .map    = combiner_irq_domain_map,
 513 };
 514
 515 static void __init combiner_init(void __iomem *combiner_base,
 516                                  struct device_node *np)
 517 {
 518         int i, irq, irq_base;
 519         unsigned int max_nr, nr_irq;
 520
 521         if (np) {
 522                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
 523                         pr_warning("%s: number of combiners not specified, "
 524                                 "setting default as %d.\n",
 525                                 __func__, EXYNOS4_MAX_COMBINER_NR);
 526                         max_nr = EXYNOS4_MAX_COMBINER_NR;
 527                 }
 528         } else {
 529                 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
 530                                                 EXYNOS4_MAX_COMBINER_NR;
 531         }
 532         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 533
 534         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
 535         if (IS_ERR_VALUE(irq_base)) {
 536                 irq_base = COMBINER_IRQ(0, 0);
 537                 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
 538         }
 539
 540         combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
 541                                 &combiner_irq_domain_ops, &combiner_data);
 542         if (WARN_ON(!combiner_irq_domain)) {
 543                 pr_warning("%s: irq domain init failed\n", __func__);
 544                 return;
 545         }
 546
 547         for (i = 0; i < max_nr; i++) {
 548                 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
 549                 irq = IRQ_SPI(i);
 550 #ifdef CONFIG_OF
 551                 if (np)
 552                         irq = irq_of_parse_and_map(np, i);
 553 #endif
 554                 combiner_cascade_irq(i, irq);
 555         }
 556 }
 557
 558 #ifdef CONFIG_OF
 559 static int __init combiner_of_init(struct device_node *np,
 560                                    struct device_node *parent)
 561 {
 562         void __iomem *combiner_base;
 563
 564         combiner_base = of_iomap(np, 0);
 565         if (!combiner_base) {
 566                 pr_err("%s: failed to map combiner registers\n", __func__);
 567                 return -ENXIO;
 568         }
 569
 570         combiner_init(combiner_base, np);
 571
 572         return 0;
 573 }
 574
 575 static const struct of_device_id exynos4_dt_irq_match[] = {
 576         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 577         { .compatible = "samsung,exynos4210-combiner",
 578                         .data = combiner_of_init, },
 579         {},
 580 };
 581 #endif
 582
 583 void __init exynos4_init_irq(void)
 584 {
 585         unsigned int gic_bank_offset;
 586
 587         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 588
 589         if (!of_have_populated_dt())
 590                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 591 #ifdef CONFIG_OF
 592         else
 593                 of_irq_init(exynos4_dt_irq_match);
 594 #endif
 595
 596         if (!of_have_populated_dt())
 597                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 598
 599         /*
 600          * The parameters of s5p_init_irq() are for VIC init.
 601          * Theses parameters should be NULL and 0 because EXYNOS4
 602          * uses GIC instead of VIC.
 603          */
 604         s5p_init_irq(NULL, 0);
 605 }
 606
 607 void __init exynos5_init_irq(void)
 608 {
 609 #ifdef CONFIG_OF
 610         of_irq_init(exynos4_dt_irq_match);
 611 #endif
 612         /*
 613          * The parameters of s5p_init_irq() are for VIC init.
 614          * Theses parameters should be NULL and 0 because EXYNOS4
 615          * uses GIC instead of VIC.
 616          */
 617         s5p_init_irq(NULL, 0);
 618
 619         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 620 }
 621
 622 struct bus_type exynos_subsys = {
 623         .name           = "exynos-core",
 624         .dev_name       = "exynos-core",
 625 };
 626
 627 static struct device exynos4_dev = {
 628         .bus    = &exynos_subsys,
 629 };
 630
 631 static int __init exynos_core_init(void)
 632 {
 633         return subsys_system_register(&exynos_subsys, NULL);
 634 }
 635 core_initcall(exynos_core_init);
 636
 637 #ifdef CONFIG_CACHE_L2X0
 638 static int __init exynos4_l2x0_cache_init(void)
 639 {
 640         int ret;
 641
 642         if (soc_is_exynos5250())
 643                 return 0;
 644
 645         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 646         if (!ret) {
 647                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 648                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 649                 return 0;
 650         }
 651
 652         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 653                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 654                 /* TAG, Data Latency Control: 2 cycles */
 655                 l2x0_saved_regs.tag_latency = 0x110;
 656
 657                 if (soc_is_exynos4212() || soc_is_exynos4412())
 658                         l2x0_saved_regs.data_latency = 0x120;
 659                 else
 660                         l2x0_saved_regs.data_latency = 0x110;
 661
 662                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 663                 l2x0_saved_regs.pwr_ctrl =
 664                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 665
 666                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 667
 668                 __raw_writel(l2x0_saved_regs.tag_latency,
 669                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 670                 __raw_writel(l2x0_saved_regs.data_latency,
 671                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 672
 673                 /* L2X0 Prefetch Control */
 674                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 675                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 676
 677                 /* L2X0 Power Control */
 678                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 679                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 680
 681                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 682                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 683         }
 684
 685         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 686         return 0;
 687 }
 688 early_initcall(exynos4_l2x0_cache_init);
 689 #endif
 690
 691 static int __init exynos_init(void)
 692 {
 693         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 694
 695         return device_register(&exynos4_dev);
 696 }
 697
 698 /* uart registration process */
 699
 700 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 701 {
 702         struct s3c2410_uartcfg *tcfg = cfg;
 703         u32 ucnt;
 704
 705         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 706                 tcfg->has_fracval = 1;
 707
 708         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 709 }
 710
 711 static void __iomem *exynos_eint_base;
 712
 713 static DEFINE_SPINLOCK(eint_lock);
 714
 715 static unsigned int eint0_15_data[16];
 716
 717 static inline int exynos4_irq_to_gpio(unsigned int irq)
 718 {
 719         if (irq < IRQ_EINT(0))
 720                 return -EINVAL;
 721
 722         irq -= IRQ_EINT(0);
 723         if (irq < 8)
 724                 return EXYNOS4_GPX0(irq);
 725
 726         irq -= 8;
 727         if (irq < 8)
 728                 return EXYNOS4_GPX1(irq);
 729
 730         irq -= 8;
 731         if (irq < 8)
 732                 return EXYNOS4_GPX2(irq);
 733
 734         irq -= 8;
 735         if (irq < 8)
 736                 return EXYNOS4_GPX3(irq);
 737
 738         return -EINVAL;
 739 }
 740
 741 static inline int exynos5_irq_to_gpio(unsigned int irq)
 742 {
 743         if (irq < IRQ_EINT(0))
 744                 return -EINVAL;
 745
 746         irq -= IRQ_EINT(0);
 747         if (irq < 8)
 748                 return EXYNOS5_GPX0(irq);
 749
 750         irq -= 8;
 751         if (irq < 8)
 752                 return EXYNOS5_GPX1(irq);
 753
 754         irq -= 8;
 755         if (irq < 8)
 756                 return EXYNOS5_GPX2(irq);
 757
 758         irq -= 8;
 759         if (irq < 8)
 760                 return EXYNOS5_GPX3(irq);
 761
 762         return -EINVAL;
 763 }
 764
 765 static unsigned int exynos4_eint0_15_src_int[16] = {
 766         EXYNOS4_IRQ_EINT0,
 767         EXYNOS4_IRQ_EINT1,
 768         EXYNOS4_IRQ_EINT2,
 769         EXYNOS4_IRQ_EINT3,
 770         EXYNOS4_IRQ_EINT4,
 771         EXYNOS4_IRQ_EINT5,
 772         EXYNOS4_IRQ_EINT6,
 773         EXYNOS4_IRQ_EINT7,
 774         EXYNOS4_IRQ_EINT8,
 775         EXYNOS4_IRQ_EINT9,
 776         EXYNOS4_IRQ_EINT10,
 777         EXYNOS4_IRQ_EINT11,
 778         EXYNOS4_IRQ_EINT12,
 779         EXYNOS4_IRQ_EINT13,
 780         EXYNOS4_IRQ_EINT14,
 781         EXYNOS4_IRQ_EINT15,
 782 };
 783
 784 static unsigned int exynos5_eint0_15_src_int[16] = {
 785         EXYNOS5_IRQ_EINT0,
 786         EXYNOS5_IRQ_EINT1,
 787         EXYNOS5_IRQ_EINT2,
 788         EXYNOS5_IRQ_EINT3,
 789         EXYNOS5_IRQ_EINT4,
 790         EXYNOS5_IRQ_EINT5,
 791         EXYNOS5_IRQ_EINT6,
 792         EXYNOS5_IRQ_EINT7,
 793         EXYNOS5_IRQ_EINT8,
 794         EXYNOS5_IRQ_EINT9,
 795         EXYNOS5_IRQ_EINT10,
 796         EXYNOS5_IRQ_EINT11,
 797         EXYNOS5_IRQ_EINT12,
 798         EXYNOS5_IRQ_EINT13,
 799         EXYNOS5_IRQ_EINT14,
 800         EXYNOS5_IRQ_EINT15,
 801 };
 802 static inline void exynos_irq_eint_mask(struct irq_data *data)
 803 {
 804         u32 mask;
 805
 806         spin_lock(&eint_lock);
 807         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 808         mask |= EINT_OFFSET_BIT(data->irq);
 809         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 810         spin_unlock(&eint_lock);
 811 }
 812
 813 static void exynos_irq_eint_unmask(struct irq_data *data)
 814 {
 815         u32 mask;
 816
 817         spin_lock(&eint_lock);
 818         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 819         mask &= ~(EINT_OFFSET_BIT(data->irq));
 820         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 821         spin_unlock(&eint_lock);
 822 }
 823
 824 static inline void exynos_irq_eint_ack(struct irq_data *data)
 825 {
 826         __raw_writel(EINT_OFFSET_BIT(data->irq),
 827                      EINT_PEND(exynos_eint_base, data->irq));
 828 }
 829
 830 static void exynos_irq_eint_maskack(struct irq_data *data)
 831 {
 832         exynos_irq_eint_mask(data);
 833         exynos_irq_eint_ack(data);
 834 }
 835
 836 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 837 {
 838         int offs = EINT_OFFSET(data->irq);
 839         int shift;
 840         u32 ctrl, mask;
 841         u32 newvalue = 0;
 842
 843         switch (type) {
 844         case IRQ_TYPE_EDGE_RISING:
 845                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 846                 break;
 847
 848         case IRQ_TYPE_EDGE_FALLING:
 849                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 850                 break;
 851
 852         case IRQ_TYPE_EDGE_BOTH:
 853                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 854                 break;
 855
 856         case IRQ_TYPE_LEVEL_LOW:
 857                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 858                 break;
 859
 860         case IRQ_TYPE_LEVEL_HIGH:
 861                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 862                 break;
 863
 864         default:
 865                 printk(KERN_ERR "No such irq type %d", type);
 866                 return -EINVAL;
 867         }
 868
 869         shift = (offs & 0x7) * 4;
 870         mask = 0x7 << shift;
 871
 872         spin_lock(&eint_lock);
 873         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 874         ctrl &= ~mask;
 875         ctrl |= newvalue << shift;
 876         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 877         spin_unlock(&eint_lock);
 878
 879         if (soc_is_exynos5250())
 880                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 881         else
 882                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 883
 884         return 0;
 885 }
 886
 887 static struct irq_chip exynos_irq_eint = {
 888         .name           = "exynos-eint",
 889         .irq_mask       = exynos_irq_eint_mask,
 890         .irq_unmask     = exynos_irq_eint_unmask,
 891         .irq_mask_ack   = exynos_irq_eint_maskack,
 892         .irq_ack        = exynos_irq_eint_ack,
 893         .irq_set_type   = exynos_irq_eint_set_type,
 894 #ifdef CONFIG_PM
 895         .irq_set_wake   = s3c_irqext_wake,
 896 #endif
 897 };
 898
 899 /*
 900  * exynos4_irq_demux_eint
 901  *
 902  * This function demuxes the IRQ from from EINTs 16 to 31.
 903  * It is designed to be inlined into the specific handler
 904  * s5p_irq_demux_eintX_Y.
 905  *
 906  * Each EINT pend/mask registers handle eight of them.
 907  */
 908 static inline void exynos_irq_demux_eint(unsigned int start)
 909 {
 910         unsigned int irq;
 911
 912         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 913         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 914
 915         status &= ~mask;
 916         status &= 0xff;
 917
 918         while (status) {
 919                 irq = fls(status) - 1;
 920                 generic_handle_irq(irq + start);
 921                 status &= ~(1 << irq);
 922         }
 923 }
 924
 925 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 926 {
 927         struct irq_chip *chip = irq_get_chip(irq);
 928         chained_irq_enter(chip, desc);
 929         exynos_irq_demux_eint(IRQ_EINT(16));
 930         exynos_irq_demux_eint(IRQ_EINT(24));
 931         chained_irq_exit(chip, desc);
 932 }
 933
 934 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 935 {
 936         u32 *irq_data = irq_get_handler_data(irq);
 937         struct irq_chip *chip = irq_get_chip(irq);
 938
 939         chained_irq_enter(chip, desc);
 940         generic_handle_irq(*irq_data);
 941         chained_irq_exit(chip, desc);
 942 }
 943
 944 static int __init exynos_init_irq_eint(void)
 945 {
 946         int irq;
 947
 948 #ifdef CONFIG_PINCTRL_SAMSUNG
 949         /*
 950          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 951          * functionality along with support for external gpio and wakeup
 952          * interrupts. If the samsung pinctrl driver is enabled and includes
 953          * the wakeup interrupt support, then the setting up external wakeup
 954          * interrupts here can be skipped. This check here is temporary to
 955          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 956          * co-exist with platforms that do. When all of the Samsung Exynos4
 957          * platforms switch over to using the pinctrl driver, the wakeup
 958          * interrupt support code here can be completely removed.
 959          */
 960         static const struct of_device_id exynos_pinctrl_ids[] = {
 961                 { .compatible = "samsung,pinctrl-exynos4210", },
 962                 { .compatible = "samsung,pinctrl-exynos4x12", },
 963         };
 964         struct device_node *pctrl_np, *wkup_np;
 965         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 966
 967         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 968                 if (of_device_is_available(pctrl_np)) {
 969                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 970                                                         wkup_compat);
 971                         if (wkup_np)
 972                                 return -ENODEV;
 973                 }
 974         }
 975 #endif
 976
 977         if (soc_is_exynos5250())
 978                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 979         else
 980                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 981
 982         if (exynos_eint_base == NULL) {
 983                 pr_err("unable to ioremap for EINT base address\n");
 984                 return -ENOMEM;
 985         }
 986
 987         for (irq = 0 ; irq <= 31 ; irq++) {
 988                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 989                                          handle_level_irq);
 990                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 991         }
 992
 993         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 994
 995         for (irq = 0 ; irq <= 15 ; irq++) {
 996                 eint0_15_data[irq] = IRQ_EINT(irq);
 997
 998                 if (soc_is_exynos5250()) {
 999                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
1000                                              &eint0_15_data[irq]);
1001                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
1002                                                 exynos_irq_eint0_15);
1003                 } else {
1004                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
1005                                              &eint0_15_data[irq]);
1006                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
1007                                                 exynos_irq_eint0_15);
1008                 }
1009         }
1010
1011         return 0;
1012 }
1013 arch_initcall(exynos_init_irq_eint);