Pileus Git - ~andy/linux/blob - arch/arm/mach-exynos/clock.c

   1 /* linux/arch/arm/mach-exynos4/clock.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/syscore_ops.h>
  17
  18 #include <plat/cpu-freq.h>
  19 #include <plat/clock.h>
  20 #include <plat/cpu.h>
  21 #include <plat/pll.h>
  22 #include <plat/s5p-clock.h>
  23 #include <plat/clock-clksrc.h>
  24 #include <plat/exynos4.h>
  25 #include <plat/pm.h>
  26
  27 #include <mach/map.h>
  28 #include <mach/regs-clock.h>
  29 #include <mach/sysmmu.h>
  30 #include <mach/exynos4-clock.h>
  31
  32 static struct sleep_save exynos4_clock_save[] = {
  33         SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
  34         SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
  35         SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
  36         SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
  37         SAVE_ITEM(S5P_CLKSRC_TOP0),
  38         SAVE_ITEM(S5P_CLKSRC_TOP1),
  39         SAVE_ITEM(S5P_CLKSRC_CAM),
  40         SAVE_ITEM(S5P_CLKSRC_TV),
  41         SAVE_ITEM(S5P_CLKSRC_MFC),
  42         SAVE_ITEM(S5P_CLKSRC_G3D),
  43         SAVE_ITEM(S5P_CLKSRC_LCD0),
  44         SAVE_ITEM(S5P_CLKSRC_MAUDIO),
  45         SAVE_ITEM(S5P_CLKSRC_FSYS),
  46         SAVE_ITEM(S5P_CLKSRC_PERIL0),
  47         SAVE_ITEM(S5P_CLKSRC_PERIL1),
  48         SAVE_ITEM(S5P_CLKDIV_CAM),
  49         SAVE_ITEM(S5P_CLKDIV_TV),
  50         SAVE_ITEM(S5P_CLKDIV_MFC),
  51         SAVE_ITEM(S5P_CLKDIV_G3D),
  52         SAVE_ITEM(S5P_CLKDIV_LCD0),
  53         SAVE_ITEM(S5P_CLKDIV_MAUDIO),
  54         SAVE_ITEM(S5P_CLKDIV_FSYS0),
  55         SAVE_ITEM(S5P_CLKDIV_FSYS1),
  56         SAVE_ITEM(S5P_CLKDIV_FSYS2),
  57         SAVE_ITEM(S5P_CLKDIV_FSYS3),
  58         SAVE_ITEM(S5P_CLKDIV_PERIL0),
  59         SAVE_ITEM(S5P_CLKDIV_PERIL1),
  60         SAVE_ITEM(S5P_CLKDIV_PERIL2),
  61         SAVE_ITEM(S5P_CLKDIV_PERIL3),
  62         SAVE_ITEM(S5P_CLKDIV_PERIL4),
  63         SAVE_ITEM(S5P_CLKDIV_PERIL5),
  64         SAVE_ITEM(S5P_CLKDIV_TOP),
  65         SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
  66         SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
  67         SAVE_ITEM(S5P_CLKSRC_MASK_TV),
  68         SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
  69         SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
  70         SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
  71         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
  72         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
  73         SAVE_ITEM(S5P_CLKDIV2_RATIO),
  74         SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
  75         SAVE_ITEM(S5P_CLKGATE_IP_CAM),
  76         SAVE_ITEM(S5P_CLKGATE_IP_TV),
  77         SAVE_ITEM(S5P_CLKGATE_IP_MFC),
  78         SAVE_ITEM(S5P_CLKGATE_IP_G3D),
  79         SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
  80         SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
  81         SAVE_ITEM(S5P_CLKGATE_IP_GPS),
  82         SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
  83         SAVE_ITEM(S5P_CLKGATE_BLOCK),
  84         SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
  85         SAVE_ITEM(S5P_CLKSRC_DMC),
  86         SAVE_ITEM(S5P_CLKDIV_DMC0),
  87         SAVE_ITEM(S5P_CLKDIV_DMC1),
  88         SAVE_ITEM(S5P_CLKGATE_IP_DMC),
  89         SAVE_ITEM(S5P_CLKSRC_CPU),
  90         SAVE_ITEM(S5P_CLKDIV_CPU),
  91         SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
  92         SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
  93         SAVE_ITEM(S5P_CLKGATE_IP_CPU),
  94 };
  95
  96 struct clk clk_sclk_hdmi27m = {
  97         .name           = "sclk_hdmi27m",
  98         .rate           = 27000000,
  99 };
 100
 101 struct clk clk_sclk_hdmiphy = {
 102         .name           = "sclk_hdmiphy",
 103 };
 104
 105 struct clk clk_sclk_usbphy0 = {
 106         .name           = "sclk_usbphy0",
 107         .rate           = 27000000,
 108 };
 109
 110 struct clk clk_sclk_usbphy1 = {
 111         .name           = "sclk_usbphy1",
 112 };
 113
 114 static struct clk dummy_apb_pclk = {
 115         .name           = "apb_pclk",
 116         .id             = -1,
 117 };
 118
 119 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 120 {
 121         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
 122 }
 123
 124 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 125 {
 126         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
 127 }
 128
 129 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 130 {
 131         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
 132 }
 133
 134 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 135 {
 136         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
 137 }
 138
 139 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 140 {
 141         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
 142 }
 143
 144 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 145 {
 146         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
 147 }
 148
 149 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 150 {
 151         return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
 152 }
 153
 154 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 155 {
 156         return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
 157 }
 158
 159 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 160 {
 161         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
 162 }
 163
 164 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 165 {
 166         return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
 167 }
 168
 169 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 170 {
 171         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
 172 }
 173
 174 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 175 {
 176         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 177 }
 178
 179 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 180 {
 181         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 182 }
 183
 184 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 185 {
 186         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 187 }
 188
 189 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 190 {
 191         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 192 }
 193
 194 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 195 {
 196         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 197 }
 198
 199 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 200 {
 201         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 202 }
 203
 204 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 205 {
 206         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
 207 }
 208
 209 /* Core list of CMU_CPU side */
 210
 211 static struct clksrc_clk clk_mout_apll = {
 212         .clk    = {
 213                 .name           = "mout_apll",
 214         },
 215         .sources        = &clk_src_apll,
 216         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 217 };
 218
 219 struct clksrc_clk clk_sclk_apll = {
 220         .clk    = {
 221                 .name           = "sclk_apll",
 222                 .parent         = &clk_mout_apll.clk,
 223         },
 224         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 225 };
 226
 227 struct clksrc_clk clk_mout_epll = {
 228         .clk    = {
 229                 .name           = "mout_epll",
 230         },
 231         .sources        = &clk_src_epll,
 232         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 233 };
 234
 235 struct clksrc_clk clk_mout_mpll = {
 236         .clk = {
 237                 .name           = "mout_mpll",
 238         },
 239         .sources        = &clk_src_mpll,
 240
 241         /* reg_src will be added in each SoCs' clock */
 242 };
 243
 244 static struct clk *clkset_moutcore_list[] = {
 245         [0] = &clk_mout_apll.clk,
 246         [1] = &clk_mout_mpll.clk,
 247 };
 248
 249 static struct clksrc_sources clkset_moutcore = {
 250         .sources        = clkset_moutcore_list,
 251         .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
 252 };
 253
 254 static struct clksrc_clk clk_moutcore = {
 255         .clk    = {
 256                 .name           = "moutcore",
 257         },
 258         .sources        = &clkset_moutcore,
 259         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
 260 };
 261
 262 static struct clksrc_clk clk_coreclk = {
 263         .clk    = {
 264                 .name           = "core_clk",
 265                 .parent         = &clk_moutcore.clk,
 266         },
 267         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
 268 };
 269
 270 static struct clksrc_clk clk_armclk = {
 271         .clk    = {
 272                 .name           = "armclk",
 273                 .parent         = &clk_coreclk.clk,
 274         },
 275 };
 276
 277 static struct clksrc_clk clk_aclk_corem0 = {
 278         .clk    = {
 279                 .name           = "aclk_corem0",
 280                 .parent         = &clk_coreclk.clk,
 281         },
 282         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 283 };
 284
 285 static struct clksrc_clk clk_aclk_cores = {
 286         .clk    = {
 287                 .name           = "aclk_cores",
 288                 .parent         = &clk_coreclk.clk,
 289         },
 290         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 291 };
 292
 293 static struct clksrc_clk clk_aclk_corem1 = {
 294         .clk    = {
 295                 .name           = "aclk_corem1",
 296                 .parent         = &clk_coreclk.clk,
 297         },
 298         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
 299 };
 300
 301 static struct clksrc_clk clk_periphclk = {
 302         .clk    = {
 303                 .name           = "periphclk",
 304                 .parent         = &clk_coreclk.clk,
 305         },
 306         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 307 };
 308
 309 /* Core list of CMU_CORE side */
 310
 311 struct clk *clkset_corebus_list[] = {
 312         [0] = &clk_mout_mpll.clk,
 313         [1] = &clk_sclk_apll.clk,
 314 };
 315
 316 struct clksrc_sources clkset_mout_corebus = {
 317         .sources        = clkset_corebus_list,
 318         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 319 };
 320
 321 static struct clksrc_clk clk_mout_corebus = {
 322         .clk    = {
 323                 .name           = "mout_corebus",
 324         },
 325         .sources        = &clkset_mout_corebus,
 326         .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
 327 };
 328
 329 static struct clksrc_clk clk_sclk_dmc = {
 330         .clk    = {
 331                 .name           = "sclk_dmc",
 332                 .parent         = &clk_mout_corebus.clk,
 333         },
 334         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
 335 };
 336
 337 static struct clksrc_clk clk_aclk_cored = {
 338         .clk    = {
 339                 .name           = "aclk_cored",
 340                 .parent         = &clk_sclk_dmc.clk,
 341         },
 342         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
 343 };
 344
 345 static struct clksrc_clk clk_aclk_corep = {
 346         .clk    = {
 347                 .name           = "aclk_corep",
 348                 .parent         = &clk_aclk_cored.clk,
 349         },
 350         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
 351 };
 352
 353 static struct clksrc_clk clk_aclk_acp = {
 354         .clk    = {
 355                 .name           = "aclk_acp",
 356                 .parent         = &clk_mout_corebus.clk,
 357         },
 358         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
 359 };
 360
 361 static struct clksrc_clk clk_pclk_acp = {
 362         .clk    = {
 363                 .name           = "pclk_acp",
 364                 .parent         = &clk_aclk_acp.clk,
 365         },
 366         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
 367 };
 368
 369 /* Core list of CMU_TOP side */
 370
 371 struct clk *clkset_aclk_top_list[] = {
 372         [0] = &clk_mout_mpll.clk,
 373         [1] = &clk_sclk_apll.clk,
 374 };
 375
 376 struct clksrc_sources clkset_aclk = {
 377         .sources        = clkset_aclk_top_list,
 378         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 379 };
 380
 381 static struct clksrc_clk clk_aclk_200 = {
 382         .clk    = {
 383                 .name           = "aclk_200",
 384         },
 385         .sources        = &clkset_aclk,
 386         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
 387         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 388 };
 389
 390 static struct clksrc_clk clk_aclk_100 = {
 391         .clk    = {
 392                 .name           = "aclk_100",
 393         },
 394         .sources        = &clkset_aclk,
 395         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
 396         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 397 };
 398
 399 static struct clksrc_clk clk_aclk_160 = {
 400         .clk    = {
 401                 .name           = "aclk_160",
 402         },
 403         .sources        = &clkset_aclk,
 404         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
 405         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 406 };
 407
 408 struct clksrc_clk clk_aclk_133 = {
 409         .clk    = {
 410                 .name           = "aclk_133",
 411         },
 412         .sources        = &clkset_aclk,
 413         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
 414         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 415 };
 416
 417 static struct clk *clkset_vpllsrc_list[] = {
 418         [0] = &clk_fin_vpll,
 419         [1] = &clk_sclk_hdmi27m,
 420 };
 421
 422 static struct clksrc_sources clkset_vpllsrc = {
 423         .sources        = clkset_vpllsrc_list,
 424         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 425 };
 426
 427 static struct clksrc_clk clk_vpllsrc = {
 428         .clk    = {
 429                 .name           = "vpll_src",
 430                 .enable         = exynos4_clksrc_mask_top_ctrl,
 431                 .ctrlbit        = (1 << 0),
 432         },
 433         .sources        = &clkset_vpllsrc,
 434         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
 435 };
 436
 437 static struct clk *clkset_sclk_vpll_list[] = {
 438         [0] = &clk_vpllsrc.clk,
 439         [1] = &clk_fout_vpll,
 440 };
 441
 442 static struct clksrc_sources clkset_sclk_vpll = {
 443         .sources        = clkset_sclk_vpll_list,
 444         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 445 };
 446
 447 struct clksrc_clk clk_sclk_vpll = {
 448         .clk    = {
 449                 .name           = "sclk_vpll",
 450         },
 451         .sources        = &clkset_sclk_vpll,
 452         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 453 };
 454
 455 static struct clk init_clocks_off[] = {
 456         {
 457                 .name           = "timers",
 458                 .parent         = &clk_aclk_100.clk,
 459                 .enable         = exynos4_clk_ip_peril_ctrl,
 460                 .ctrlbit        = (1<<24),
 461         }, {
 462                 .name           = "csis",
 463                 .devname        = "s5p-mipi-csis.0",
 464                 .enable         = exynos4_clk_ip_cam_ctrl,
 465                 .ctrlbit        = (1 << 4),
 466         }, {
 467                 .name           = "csis",
 468                 .devname        = "s5p-mipi-csis.1",
 469                 .enable         = exynos4_clk_ip_cam_ctrl,
 470                 .ctrlbit        = (1 << 5),
 471         }, {
 472                 .name           = "fimc",
 473                 .devname        = "exynos4-fimc.0",
 474                 .enable         = exynos4_clk_ip_cam_ctrl,
 475                 .ctrlbit        = (1 << 0),
 476         }, {
 477                 .name           = "fimc",
 478                 .devname        = "exynos4-fimc.1",
 479                 .enable         = exynos4_clk_ip_cam_ctrl,
 480                 .ctrlbit        = (1 << 1),
 481         }, {
 482                 .name           = "fimc",
 483                 .devname        = "exynos4-fimc.2",
 484                 .enable         = exynos4_clk_ip_cam_ctrl,
 485                 .ctrlbit        = (1 << 2),
 486         }, {
 487                 .name           = "fimc",
 488                 .devname        = "exynos4-fimc.3",
 489                 .enable         = exynos4_clk_ip_cam_ctrl,
 490                 .ctrlbit        = (1 << 3),
 491         }, {
 492                 .name           = "fimd",
 493                 .devname        = "exynos4-fb.0",
 494                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 495                 .ctrlbit        = (1 << 0),
 496         }, {
 497                 .name           = "hsmmc",
 498                 .devname        = "s3c-sdhci.0",
 499                 .parent         = &clk_aclk_133.clk,
 500                 .enable         = exynos4_clk_ip_fsys_ctrl,
 501                 .ctrlbit        = (1 << 5),
 502         }, {
 503                 .name           = "hsmmc",
 504                 .devname        = "s3c-sdhci.1",
 505                 .parent         = &clk_aclk_133.clk,
 506                 .enable         = exynos4_clk_ip_fsys_ctrl,
 507                 .ctrlbit        = (1 << 6),
 508         }, {
 509                 .name           = "hsmmc",
 510                 .devname        = "s3c-sdhci.2",
 511                 .parent         = &clk_aclk_133.clk,
 512                 .enable         = exynos4_clk_ip_fsys_ctrl,
 513                 .ctrlbit        = (1 << 7),
 514         }, {
 515                 .name           = "hsmmc",
 516                 .devname        = "s3c-sdhci.3",
 517                 .parent         = &clk_aclk_133.clk,
 518                 .enable         = exynos4_clk_ip_fsys_ctrl,
 519                 .ctrlbit        = (1 << 8),
 520         }, {
 521                 .name           = "dwmmc",
 522                 .parent         = &clk_aclk_133.clk,
 523                 .enable         = exynos4_clk_ip_fsys_ctrl,
 524                 .ctrlbit        = (1 << 9),
 525         }, {
 526                 .name           = "dac",
 527                 .devname        = "s5p-sdo",
 528                 .enable         = exynos4_clk_ip_tv_ctrl,
 529                 .ctrlbit        = (1 << 2),
 530         }, {
 531                 .name           = "mixer",
 532                 .devname        = "s5p-mixer",
 533                 .enable         = exynos4_clk_ip_tv_ctrl,
 534                 .ctrlbit        = (1 << 1),
 535         }, {
 536                 .name           = "vp",
 537                 .devname        = "s5p-mixer",
 538                 .enable         = exynos4_clk_ip_tv_ctrl,
 539                 .ctrlbit        = (1 << 0),
 540         }, {
 541                 .name           = "hdmi",
 542                 .devname        = "exynos4-hdmi",
 543                 .enable         = exynos4_clk_ip_tv_ctrl,
 544                 .ctrlbit        = (1 << 3),
 545         }, {
 546                 .name           = "hdmiphy",
 547                 .devname        = "exynos4-hdmi",
 548                 .enable         = exynos4_clk_hdmiphy_ctrl,
 549                 .ctrlbit        = (1 << 0),
 550         }, {
 551                 .name           = "dacphy",
 552                 .devname        = "s5p-sdo",
 553                 .enable         = exynos4_clk_dac_ctrl,
 554                 .ctrlbit        = (1 << 0),
 555         }, {
 556                 .name           = "adc",
 557                 .enable         = exynos4_clk_ip_peril_ctrl,
 558                 .ctrlbit        = (1 << 15),
 559         }, {
 560                 .name           = "keypad",
 561                 .enable         = exynos4_clk_ip_perir_ctrl,
 562                 .ctrlbit        = (1 << 16),
 563         }, {
 564                 .name           = "rtc",
 565                 .enable         = exynos4_clk_ip_perir_ctrl,
 566                 .ctrlbit        = (1 << 15),
 567         }, {
 568                 .name           = "watchdog",
 569                 .parent         = &clk_aclk_100.clk,
 570                 .enable         = exynos4_clk_ip_perir_ctrl,
 571                 .ctrlbit        = (1 << 14),
 572         }, {
 573                 .name           = "usbhost",
 574                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 575                 .ctrlbit        = (1 << 12),
 576         }, {
 577                 .name           = "otg",
 578                 .enable         = exynos4_clk_ip_fsys_ctrl,
 579                 .ctrlbit        = (1 << 13),
 580         }, {
 581                 .name           = "spi",
 582                 .devname        = "s3c64xx-spi.0",
 583                 .enable         = exynos4_clk_ip_peril_ctrl,
 584                 .ctrlbit        = (1 << 16),
 585         }, {
 586                 .name           = "spi",
 587                 .devname        = "s3c64xx-spi.1",
 588                 .enable         = exynos4_clk_ip_peril_ctrl,
 589                 .ctrlbit        = (1 << 17),
 590         }, {
 591                 .name           = "spi",
 592                 .devname        = "s3c64xx-spi.2",
 593                 .enable         = exynos4_clk_ip_peril_ctrl,
 594                 .ctrlbit        = (1 << 18),
 595         }, {
 596                 .name           = "iis",
 597                 .devname        = "samsung-i2s.0",
 598                 .enable         = exynos4_clk_ip_peril_ctrl,
 599                 .ctrlbit        = (1 << 19),
 600         }, {
 601                 .name           = "iis",
 602                 .devname        = "samsung-i2s.1",
 603                 .enable         = exynos4_clk_ip_peril_ctrl,
 604                 .ctrlbit        = (1 << 20),
 605         }, {
 606                 .name           = "iis",
 607                 .devname        = "samsung-i2s.2",
 608                 .enable         = exynos4_clk_ip_peril_ctrl,
 609                 .ctrlbit        = (1 << 21),
 610         }, {
 611                 .name           = "ac97",
 612                 .devname        = "samsung-ac97",
 613                 .enable         = exynos4_clk_ip_peril_ctrl,
 614                 .ctrlbit        = (1 << 27),
 615         }, {
 616                 .name           = "fimg2d",
 617                 .enable         = exynos4_clk_ip_image_ctrl,
 618                 .ctrlbit        = (1 << 0),
 619         }, {
 620                 .name           = "mfc",
 621                 .devname        = "s5p-mfc",
 622                 .enable         = exynos4_clk_ip_mfc_ctrl,
 623                 .ctrlbit        = (1 << 0),
 624         }, {
 625                 .name           = "i2c",
 626                 .devname        = "s3c2440-i2c.0",
 627                 .parent         = &clk_aclk_100.clk,
 628                 .enable         = exynos4_clk_ip_peril_ctrl,
 629                 .ctrlbit        = (1 << 6),
 630         }, {
 631                 .name           = "i2c",
 632                 .devname        = "s3c2440-i2c.1",
 633                 .parent         = &clk_aclk_100.clk,
 634                 .enable         = exynos4_clk_ip_peril_ctrl,
 635                 .ctrlbit        = (1 << 7),
 636         }, {
 637                 .name           = "i2c",
 638                 .devname        = "s3c2440-i2c.2",
 639                 .parent         = &clk_aclk_100.clk,
 640                 .enable         = exynos4_clk_ip_peril_ctrl,
 641                 .ctrlbit        = (1 << 8),
 642         }, {
 643                 .name           = "i2c",
 644                 .devname        = "s3c2440-i2c.3",
 645                 .parent         = &clk_aclk_100.clk,
 646                 .enable         = exynos4_clk_ip_peril_ctrl,
 647                 .ctrlbit        = (1 << 9),
 648         }, {
 649                 .name           = "i2c",
 650                 .devname        = "s3c2440-i2c.4",
 651                 .parent         = &clk_aclk_100.clk,
 652                 .enable         = exynos4_clk_ip_peril_ctrl,
 653                 .ctrlbit        = (1 << 10),
 654         }, {
 655                 .name           = "i2c",
 656                 .devname        = "s3c2440-i2c.5",
 657                 .parent         = &clk_aclk_100.clk,
 658                 .enable         = exynos4_clk_ip_peril_ctrl,
 659                 .ctrlbit        = (1 << 11),
 660         }, {
 661                 .name           = "i2c",
 662                 .devname        = "s3c2440-i2c.6",
 663                 .parent         = &clk_aclk_100.clk,
 664                 .enable         = exynos4_clk_ip_peril_ctrl,
 665                 .ctrlbit        = (1 << 12),
 666         }, {
 667                 .name           = "i2c",
 668                 .devname        = "s3c2440-i2c.7",
 669                 .parent         = &clk_aclk_100.clk,
 670                 .enable         = exynos4_clk_ip_peril_ctrl,
 671                 .ctrlbit        = (1 << 13),
 672         }, {
 673                 .name           = "i2c",
 674                 .devname        = "s3c2440-hdmiphy-i2c",
 675                 .parent         = &clk_aclk_100.clk,
 676                 .enable         = exynos4_clk_ip_peril_ctrl,
 677                 .ctrlbit        = (1 << 14),
 678         }, {
 679                 .name           = "SYSMMU_MDMA",
 680                 .enable         = exynos4_clk_ip_image_ctrl,
 681                 .ctrlbit        = (1 << 5),
 682         }, {
 683                 .name           = "SYSMMU_FIMC0",
 684                 .enable         = exynos4_clk_ip_cam_ctrl,
 685                 .ctrlbit        = (1 << 7),
 686         }, {
 687                 .name           = "SYSMMU_FIMC1",
 688                 .enable         = exynos4_clk_ip_cam_ctrl,
 689                 .ctrlbit        = (1 << 8),
 690         }, {
 691                 .name           = "SYSMMU_FIMC2",
 692                 .enable         = exynos4_clk_ip_cam_ctrl,
 693                 .ctrlbit        = (1 << 9),
 694         }, {
 695                 .name           = "SYSMMU_FIMC3",
 696                 .enable         = exynos4_clk_ip_cam_ctrl,
 697                 .ctrlbit        = (1 << 10),
 698         }, {
 699                 .name           = "SYSMMU_JPEG",
 700                 .enable         = exynos4_clk_ip_cam_ctrl,
 701                 .ctrlbit        = (1 << 11),
 702         }, {
 703                 .name           = "SYSMMU_FIMD0",
 704                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 705                 .ctrlbit        = (1 << 4),
 706         }, {
 707                 .name           = "SYSMMU_FIMD1",
 708                 .enable         = exynos4_clk_ip_lcd1_ctrl,
 709                 .ctrlbit        = (1 << 4),
 710         }, {
 711                 .name           = "SYSMMU_PCIe",
 712                 .enable         = exynos4_clk_ip_fsys_ctrl,
 713                 .ctrlbit        = (1 << 18),
 714         }, {
 715                 .name           = "SYSMMU_G2D",
 716                 .enable         = exynos4_clk_ip_image_ctrl,
 717                 .ctrlbit        = (1 << 3),
 718         }, {
 719                 .name           = "SYSMMU_ROTATOR",
 720                 .enable         = exynos4_clk_ip_image_ctrl,
 721                 .ctrlbit        = (1 << 4),
 722         }, {
 723                 .name           = "SYSMMU_TV",
 724                 .enable         = exynos4_clk_ip_tv_ctrl,
 725                 .ctrlbit        = (1 << 4),
 726         }, {
 727                 .name           = "SYSMMU_MFC_L",
 728                 .enable         = exynos4_clk_ip_mfc_ctrl,
 729                 .ctrlbit        = (1 << 1),
 730         }, {
 731                 .name           = "SYSMMU_MFC_R",
 732                 .enable         = exynos4_clk_ip_mfc_ctrl,
 733                 .ctrlbit        = (1 << 2),
 734         }
 735 };
 736
 737 static struct clk init_clocks[] = {
 738         {
 739                 .name           = "uart",
 740                 .devname        = "s5pv210-uart.0",
 741                 .enable         = exynos4_clk_ip_peril_ctrl,
 742                 .ctrlbit        = (1 << 0),
 743         }, {
 744                 .name           = "uart",
 745                 .devname        = "s5pv210-uart.1",
 746                 .enable         = exynos4_clk_ip_peril_ctrl,
 747                 .ctrlbit        = (1 << 1),
 748         }, {
 749                 .name           = "uart",
 750                 .devname        = "s5pv210-uart.2",
 751                 .enable         = exynos4_clk_ip_peril_ctrl,
 752                 .ctrlbit        = (1 << 2),
 753         }, {
 754                 .name           = "uart",
 755                 .devname        = "s5pv210-uart.3",
 756                 .enable         = exynos4_clk_ip_peril_ctrl,
 757                 .ctrlbit        = (1 << 3),
 758         }, {
 759                 .name           = "uart",
 760                 .devname        = "s5pv210-uart.4",
 761                 .enable         = exynos4_clk_ip_peril_ctrl,
 762                 .ctrlbit        = (1 << 4),
 763         }, {
 764                 .name           = "uart",
 765                 .devname        = "s5pv210-uart.5",
 766                 .enable         = exynos4_clk_ip_peril_ctrl,
 767                 .ctrlbit        = (1 << 5),
 768         }
 769 };
 770
 771 static struct clk clk_pdma0 = {
 772         .name           = "dma",
 773         .devname        = "dma-pl330.0",
 774         .enable         = exynos4_clk_ip_fsys_ctrl,
 775         .ctrlbit        = (1 << 0),
 776 };
 777
 778 static struct clk clk_pdma1 = {
 779         .name           = "dma",
 780         .devname        = "dma-pl330.1",
 781         .enable         = exynos4_clk_ip_fsys_ctrl,
 782         .ctrlbit        = (1 << 1),
 783 };
 784
 785 struct clk *clkset_group_list[] = {
 786         [0] = &clk_ext_xtal_mux,
 787         [1] = &clk_xusbxti,
 788         [2] = &clk_sclk_hdmi27m,
 789         [3] = &clk_sclk_usbphy0,
 790         [4] = &clk_sclk_usbphy1,
 791         [5] = &clk_sclk_hdmiphy,
 792         [6] = &clk_mout_mpll.clk,
 793         [7] = &clk_mout_epll.clk,
 794         [8] = &clk_sclk_vpll.clk,
 795 };
 796
 797 struct clksrc_sources clkset_group = {
 798         .sources        = clkset_group_list,
 799         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 800 };
 801
 802 static struct clk *clkset_mout_g2d0_list[] = {
 803         [0] = &clk_mout_mpll.clk,
 804         [1] = &clk_sclk_apll.clk,
 805 };
 806
 807 static struct clksrc_sources clkset_mout_g2d0 = {
 808         .sources        = clkset_mout_g2d0_list,
 809         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
 810 };
 811
 812 static struct clksrc_clk clk_mout_g2d0 = {
 813         .clk    = {
 814                 .name           = "mout_g2d0",
 815         },
 816         .sources        = &clkset_mout_g2d0,
 817         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 818 };
 819
 820 static struct clk *clkset_mout_g2d1_list[] = {
 821         [0] = &clk_mout_epll.clk,
 822         [1] = &clk_sclk_vpll.clk,
 823 };
 824
 825 static struct clksrc_sources clkset_mout_g2d1 = {
 826         .sources        = clkset_mout_g2d1_list,
 827         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
 828 };
 829
 830 static struct clksrc_clk clk_mout_g2d1 = {
 831         .clk    = {
 832                 .name           = "mout_g2d1",
 833         },
 834         .sources        = &clkset_mout_g2d1,
 835         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 836 };
 837
 838 static struct clk *clkset_mout_g2d_list[] = {
 839         [0] = &clk_mout_g2d0.clk,
 840         [1] = &clk_mout_g2d1.clk,
 841 };
 842
 843 static struct clksrc_sources clkset_mout_g2d = {
 844         .sources        = clkset_mout_g2d_list,
 845         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
 846 };
 847
 848 static struct clk *clkset_mout_mfc0_list[] = {
 849         [0] = &clk_mout_mpll.clk,
 850         [1] = &clk_sclk_apll.clk,
 851 };
 852
 853 static struct clksrc_sources clkset_mout_mfc0 = {
 854         .sources        = clkset_mout_mfc0_list,
 855         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
 856 };
 857
 858 static struct clksrc_clk clk_mout_mfc0 = {
 859         .clk    = {
 860                 .name           = "mout_mfc0",
 861         },
 862         .sources        = &clkset_mout_mfc0,
 863         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
 864 };
 865
 866 static struct clk *clkset_mout_mfc1_list[] = {
 867         [0] = &clk_mout_epll.clk,
 868         [1] = &clk_sclk_vpll.clk,
 869 };
 870
 871 static struct clksrc_sources clkset_mout_mfc1 = {
 872         .sources        = clkset_mout_mfc1_list,
 873         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
 874 };
 875
 876 static struct clksrc_clk clk_mout_mfc1 = {
 877         .clk    = {
 878                 .name           = "mout_mfc1",
 879         },
 880         .sources        = &clkset_mout_mfc1,
 881         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
 882 };
 883
 884 static struct clk *clkset_mout_mfc_list[] = {
 885         [0] = &clk_mout_mfc0.clk,
 886         [1] = &clk_mout_mfc1.clk,
 887 };
 888
 889 static struct clksrc_sources clkset_mout_mfc = {
 890         .sources        = clkset_mout_mfc_list,
 891         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
 892 };
 893
 894 static struct clk *clkset_sclk_dac_list[] = {
 895         [0] = &clk_sclk_vpll.clk,
 896         [1] = &clk_sclk_hdmiphy,
 897 };
 898
 899 static struct clksrc_sources clkset_sclk_dac = {
 900         .sources        = clkset_sclk_dac_list,
 901         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 902 };
 903
 904 static struct clksrc_clk clk_sclk_dac = {
 905         .clk            = {
 906                 .name           = "sclk_dac",
 907                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 908                 .ctrlbit        = (1 << 8),
 909         },
 910         .sources = &clkset_sclk_dac,
 911         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
 912 };
 913
 914 static struct clksrc_clk clk_sclk_pixel = {
 915         .clk            = {
 916                 .name           = "sclk_pixel",
 917                 .parent = &clk_sclk_vpll.clk,
 918         },
 919         .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
 920 };
 921
 922 static struct clk *clkset_sclk_hdmi_list[] = {
 923         [0] = &clk_sclk_pixel.clk,
 924         [1] = &clk_sclk_hdmiphy,
 925 };
 926
 927 static struct clksrc_sources clkset_sclk_hdmi = {
 928         .sources        = clkset_sclk_hdmi_list,
 929         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 930 };
 931
 932 static struct clksrc_clk clk_sclk_hdmi = {
 933         .clk            = {
 934                 .name           = "sclk_hdmi",
 935                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 936                 .ctrlbit        = (1 << 0),
 937         },
 938         .sources = &clkset_sclk_hdmi,
 939         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
 940 };
 941
 942 static struct clk *clkset_sclk_mixer_list[] = {
 943         [0] = &clk_sclk_dac.clk,
 944         [1] = &clk_sclk_hdmi.clk,
 945 };
 946
 947 static struct clksrc_sources clkset_sclk_mixer = {
 948         .sources        = clkset_sclk_mixer_list,
 949         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 950 };
 951
 952 static struct clksrc_clk clk_sclk_mixer = {
 953         .clk            = {
 954                 .name           = "sclk_mixer",
 955                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 956                 .ctrlbit        = (1 << 4),
 957         },
 958         .sources = &clkset_sclk_mixer,
 959         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
 960 };
 961
 962 static struct clksrc_clk *sclk_tv[] = {
 963         &clk_sclk_dac,
 964         &clk_sclk_pixel,
 965         &clk_sclk_hdmi,
 966         &clk_sclk_mixer,
 967 };
 968
 969 static struct clksrc_clk clk_dout_mmc0 = {
 970         .clk            = {
 971                 .name           = "dout_mmc0",
 972         },
 973         .sources = &clkset_group,
 974         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
 975         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 976 };
 977
 978 static struct clksrc_clk clk_dout_mmc1 = {
 979         .clk            = {
 980                 .name           = "dout_mmc1",
 981         },
 982         .sources = &clkset_group,
 983         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
 984         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 985 };
 986
 987 static struct clksrc_clk clk_dout_mmc2 = {
 988         .clk            = {
 989                 .name           = "dout_mmc2",
 990         },
 991         .sources = &clkset_group,
 992         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
 993         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 994 };
 995
 996 static struct clksrc_clk clk_dout_mmc3 = {
 997         .clk            = {
 998                 .name           = "dout_mmc3",
 999         },
1000         .sources = &clkset_group,
1001         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
1002         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1003 };
1004
1005 static struct clksrc_clk clk_dout_mmc4 = {
1006         .clk            = {
1007                 .name           = "dout_mmc4",
1008         },
1009         .sources = &clkset_group,
1010         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1011         .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1012 };
1013
1014 static struct clksrc_clk clksrcs[] = {
1015         {
1016                 .clk            = {
1017                         .name           = "sclk_pwm",
1018                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1019                         .ctrlbit        = (1 << 24),
1020                 },
1021                 .sources = &clkset_group,
1022                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1023                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1024         }, {
1025                 .clk            = {
1026                         .name           = "sclk_csis",
1027                         .devname        = "s5p-mipi-csis.0",
1028                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1029                         .ctrlbit        = (1 << 24),
1030                 },
1031                 .sources = &clkset_group,
1032                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1033                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1034         }, {
1035                 .clk            = {
1036                         .name           = "sclk_csis",
1037                         .devname        = "s5p-mipi-csis.1",
1038                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1039                         .ctrlbit        = (1 << 28),
1040                 },
1041                 .sources = &clkset_group,
1042                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1043                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1044         }, {
1045                 .clk            = {
1046                         .name           = "sclk_cam0",
1047                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1048                         .ctrlbit        = (1 << 16),
1049                 },
1050                 .sources = &clkset_group,
1051                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1052                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1053         }, {
1054                 .clk            = {
1055                         .name           = "sclk_cam1",
1056                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1057                         .ctrlbit        = (1 << 20),
1058                 },
1059                 .sources = &clkset_group,
1060                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1061                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1062         }, {
1063                 .clk            = {
1064                         .name           = "sclk_fimc",
1065                         .devname        = "exynos4-fimc.0",
1066                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1067                         .ctrlbit        = (1 << 0),
1068                 },
1069                 .sources = &clkset_group,
1070                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1071                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1072         }, {
1073                 .clk            = {
1074                         .name           = "sclk_fimc",
1075                         .devname        = "exynos4-fimc.1",
1076                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1077                         .ctrlbit        = (1 << 4),
1078                 },
1079                 .sources = &clkset_group,
1080                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1081                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1082         }, {
1083                 .clk            = {
1084                         .name           = "sclk_fimc",
1085                         .devname        = "exynos4-fimc.2",
1086                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1087                         .ctrlbit        = (1 << 8),
1088                 },
1089                 .sources = &clkset_group,
1090                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1091                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1092         }, {
1093                 .clk            = {
1094                         .name           = "sclk_fimc",
1095                         .devname        = "exynos4-fimc.3",
1096                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1097                         .ctrlbit        = (1 << 12),
1098                 },
1099                 .sources = &clkset_group,
1100                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1101                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1102         }, {
1103                 .clk            = {
1104                         .name           = "sclk_fimd",
1105                         .devname        = "exynos4-fb.0",
1106                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1107                         .ctrlbit        = (1 << 0),
1108                 },
1109                 .sources = &clkset_group,
1110                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1111                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1112         }, {
1113                 .clk            = {
1114                         .name           = "sclk_fimg2d",
1115                 },
1116                 .sources = &clkset_mout_g2d,
1117                 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1118                 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1119         }, {
1120                 .clk            = {
1121                         .name           = "sclk_mfc",
1122                         .devname        = "s5p-mfc",
1123                 },
1124                 .sources = &clkset_mout_mfc,
1125                 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1126                 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1127         }, {
1128                 .clk            = {
1129                         .name           = "sclk_dwmmc",
1130                         .parent         = &clk_dout_mmc4.clk,
1131                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1132                         .ctrlbit        = (1 << 16),
1133                 },
1134                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1135         }
1136 };
1137
1138 static struct clksrc_clk clk_sclk_uart0 = {
1139         .clk    = {
1140                 .name           = "uclk1",
1141                 .devname        = "exynos4210-uart.0",
1142                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1143                 .ctrlbit        = (1 << 0),
1144         },
1145         .sources = &clkset_group,
1146         .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1147         .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1148 };
1149
1150 static struct clksrc_clk clk_sclk_uart1 = {
1151         .clk            = {
1152                 .name           = "uclk1",
1153                 .devname        = "exynos4210-uart.1",
1154                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1155                 .ctrlbit        = (1 << 4),
1156         },
1157         .sources = &clkset_group,
1158         .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1159         .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1160 };
1161
1162 static struct clksrc_clk clk_sclk_uart2 = {
1163         .clk            = {
1164                 .name           = "uclk1",
1165                 .devname        = "exynos4210-uart.2",
1166                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1167                 .ctrlbit        = (1 << 8),
1168         },
1169         .sources = &clkset_group,
1170         .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1171         .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1172 };
1173
1174 static struct clksrc_clk clk_sclk_uart3 = {
1175         .clk            = {
1176                 .name           = "uclk1",
1177                 .devname        = "exynos4210-uart.3",
1178                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1179                 .ctrlbit        = (1 << 12),
1180         },
1181         .sources = &clkset_group,
1182         .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1183         .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1184 };
1185
1186 static struct clksrc_clk clk_sclk_mmc0 = {
1187         .clk            = {
1188                 .name           = "sclk_mmc",
1189                 .devname        = "s3c-sdhci.0",
1190                 .parent         = &clk_dout_mmc0.clk,
1191                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1192                 .ctrlbit        = (1 << 0),
1193         },
1194         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1195 };
1196
1197 static struct clksrc_clk clk_sclk_mmc1 = {
1198         .clk            = {
1199                 .name           = "sclk_mmc",
1200                 .devname        = "s3c-sdhci.1",
1201                 .parent         = &clk_dout_mmc1.clk,
1202                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1203                 .ctrlbit        = (1 << 4),
1204         },
1205         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1206 };
1207
1208 static struct clksrc_clk clk_sclk_mmc2 = {
1209         .clk            = {
1210                 .name           = "sclk_mmc",
1211                 .devname        = "s3c-sdhci.2",
1212                 .parent         = &clk_dout_mmc2.clk,
1213                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1214                 .ctrlbit        = (1 << 8),
1215         },
1216         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1217 };
1218
1219 static struct clksrc_clk clk_sclk_mmc3 = {
1220         .clk            = {
1221                 .name           = "sclk_mmc",
1222                 .devname        = "s3c-sdhci.3",
1223                 .parent         = &clk_dout_mmc3.clk,
1224                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1225                 .ctrlbit        = (1 << 12),
1226         },
1227         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1228 };
1229
1230 static struct clksrc_clk clk_sclk_spi0 = {
1231         .clk            = {
1232                 .name           = "sclk_spi",
1233                 .devname                = "s3c64xx-spi.0",
1234                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1235                 .ctrlbit                = (1 << 16),
1236         },
1237         .sources = &clkset_group,
1238         .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1239         .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1240 };
1241
1242 static struct clksrc_clk clk_sclk_spi1 = {
1243         .clk            = {
1244                 .name           = "sclk_spi",
1245                 .devname                = "s3c64xx-spi.1",
1246                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1247                 .ctrlbit                = (1 << 20),
1248         },
1249         .sources = &clkset_group,
1250         .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1251         .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1252 };
1253
1254 static struct clksrc_clk clk_sclk_spi2 = {
1255         .clk            = {
1256                 .name           = "sclk_spi",
1257                 .devname                = "s3c64xx-spi.2",
1258                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1259                 .ctrlbit                = (1 << 24),
1260         },
1261         .sources = &clkset_group,
1262         .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1263         .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1264 };
1265
1266 /* Clock initialization code */
1267 static struct clksrc_clk *sysclks[] = {
1268         &clk_mout_apll,
1269         &clk_sclk_apll,
1270         &clk_mout_epll,
1271         &clk_mout_mpll,
1272         &clk_moutcore,
1273         &clk_coreclk,
1274         &clk_armclk,
1275         &clk_aclk_corem0,
1276         &clk_aclk_cores,
1277         &clk_aclk_corem1,
1278         &clk_periphclk,
1279         &clk_mout_corebus,
1280         &clk_sclk_dmc,
1281         &clk_aclk_cored,
1282         &clk_aclk_corep,
1283         &clk_aclk_acp,
1284         &clk_pclk_acp,
1285         &clk_vpllsrc,
1286         &clk_sclk_vpll,
1287         &clk_aclk_200,
1288         &clk_aclk_100,
1289         &clk_aclk_160,
1290         &clk_aclk_133,
1291         &clk_dout_mmc0,
1292         &clk_dout_mmc1,
1293         &clk_dout_mmc2,
1294         &clk_dout_mmc3,
1295         &clk_dout_mmc4,
1296         &clk_mout_mfc0,
1297         &clk_mout_mfc1,
1298 };
1299
1300 static struct clk *clk_cdev[] = {
1301         &clk_pdma0,
1302         &clk_pdma1,
1303 };
1304
1305 static struct clksrc_clk *clksrc_cdev[] = {
1306         &clk_sclk_uart0,
1307         &clk_sclk_uart1,
1308         &clk_sclk_uart2,
1309         &clk_sclk_uart3,
1310         &clk_sclk_mmc0,
1311         &clk_sclk_mmc1,
1312         &clk_sclk_mmc2,
1313         &clk_sclk_mmc3,
1314         &clk_sclk_spi0,
1315         &clk_sclk_spi1,
1316         &clk_sclk_spi2,
1317
1318 };
1319
1320 static struct clk_lookup exynos4_clk_lookup[] = {
1321         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1322         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1323         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1324         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1325         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1326         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1327         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1328         CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1329         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1330         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1331         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
1332         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
1333         CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
1334 };
1335
1336 static int xtal_rate;
1337
1338 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1339 {
1340         if (soc_is_exynos4210())
1341                 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1342                                         pll_4508);
1343         else if (soc_is_exynos4212() || soc_is_exynos4412())
1344                 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1345         else
1346                 return 0;
1347 }
1348
1349 static struct clk_ops exynos4_fout_apll_ops = {
1350         .get_rate = exynos4_fout_apll_get_rate,
1351 };
1352
1353 static u32 vpll_div[][8] = {
1354         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
1355         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1356 };
1357
1358 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1359 {
1360         return clk->rate;
1361 }
1362
1363 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1364 {
1365         unsigned int vpll_con0, vpll_con1 = 0;
1366         unsigned int i;
1367
1368         /* Return if nothing changed */
1369         if (clk->rate == rate)
1370                 return 0;
1371
1372         vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1373         vpll_con0 &= ~(0x1 << 27 |                                      \
1374                         PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
1375                         PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
1376                         PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1377
1378         vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1379         vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
1380                         PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1381                         PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1382
1383         for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1384                 if (vpll_div[i][0] == rate) {
1385                         vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1386                         vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1387                         vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1388                         vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1389                         vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1390                         vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1391                         vpll_con0 |= vpll_div[i][7] << 27;
1392                         break;
1393                 }
1394         }
1395
1396         if (i == ARRAY_SIZE(vpll_div)) {
1397                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1398                                 __func__);
1399                 return -EINVAL;
1400         }
1401
1402         __raw_writel(vpll_con0, S5P_VPLL_CON0);
1403         __raw_writel(vpll_con1, S5P_VPLL_CON1);
1404
1405         /* Wait for VPLL lock */
1406         while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1407                 continue;
1408
1409         clk->rate = rate;
1410         return 0;
1411 }
1412
1413 static struct clk_ops exynos4_vpll_ops = {
1414         .get_rate = exynos4_vpll_get_rate,
1415         .set_rate = exynos4_vpll_set_rate,
1416 };
1417
1418 void __init_or_cpufreq exynos4_setup_clocks(void)
1419 {
1420         struct clk *xtal_clk;
1421         unsigned long apll = 0;
1422         unsigned long mpll = 0;
1423         unsigned long epll = 0;
1424         unsigned long vpll = 0;
1425         unsigned long vpllsrc;
1426         unsigned long xtal;
1427         unsigned long armclk;
1428         unsigned long sclk_dmc;
1429         unsigned long aclk_200;
1430         unsigned long aclk_100;
1431         unsigned long aclk_160;
1432         unsigned long aclk_133;
1433         unsigned int ptr;
1434
1435         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1436
1437         xtal_clk = clk_get(NULL, "xtal");
1438         BUG_ON(IS_ERR(xtal_clk));
1439
1440         xtal = clk_get_rate(xtal_clk);
1441
1442         xtal_rate = xtal;
1443
1444         clk_put(xtal_clk);
1445
1446         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1447
1448         if (soc_is_exynos4210()) {
1449                 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1450                                         pll_4508);
1451                 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1452                                         pll_4508);
1453                 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1454                                         __raw_readl(S5P_EPLL_CON1), pll_4600);
1455
1456                 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1457                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1458                                         __raw_readl(S5P_VPLL_CON1), pll_4650c);
1459         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1460                 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1461                 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1462                 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1463                                         __raw_readl(S5P_EPLL_CON1));
1464
1465                 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1466                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1467                                         __raw_readl(S5P_VPLL_CON1));
1468         } else {
1469                 /* nothing */
1470         }
1471
1472         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1473         clk_fout_mpll.rate = mpll;
1474         clk_fout_epll.rate = epll;
1475         clk_fout_vpll.ops = &exynos4_vpll_ops;
1476         clk_fout_vpll.rate = vpll;
1477
1478         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1479                         apll, mpll, epll, vpll);
1480
1481         armclk = clk_get_rate(&clk_armclk.clk);
1482         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1483
1484         aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1485         aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1486         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1487         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1488
1489         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1490                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1491                         armclk, sclk_dmc, aclk_200,
1492                         aclk_100, aclk_160, aclk_133);
1493
1494         clk_f.rate = armclk;
1495         clk_h.rate = sclk_dmc;
1496         clk_p.rate = aclk_100;
1497
1498         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1499                 s3c_set_clksrc(&clksrcs[ptr], true);
1500 }
1501
1502 static struct clk *clks[] __initdata = {
1503         &clk_sclk_hdmi27m,
1504         &clk_sclk_hdmiphy,
1505         &clk_sclk_usbphy0,
1506         &clk_sclk_usbphy1,
1507 };
1508
1509 #ifdef CONFIG_PM_SLEEP
1510 static int exynos4_clock_suspend(void)
1511 {
1512         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1513         return 0;
1514 }
1515
1516 static void exynos4_clock_resume(void)
1517 {
1518         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1519 }
1520
1521 #else
1522 #define exynos4_clock_suspend NULL
1523 #define exynos4_clock_resume NULL
1524 #endif
1525
1526 struct syscore_ops exynos4_clock_syscore_ops = {
1527         .suspend        = exynos4_clock_suspend,
1528         .resume         = exynos4_clock_resume,
1529 };
1530
1531 void __init exynos4_register_clocks(void)
1532 {
1533         int ptr;
1534
1535         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1536
1537         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1538                 s3c_register_clksrc(sysclks[ptr], 1);
1539
1540         for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1541                 s3c_register_clksrc(sclk_tv[ptr], 1);
1542
1543         for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1544                 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1545
1546         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1547         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1548
1549         s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1550         for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1551                 s3c_disable_clocks(clk_cdev[ptr], 1);
1552
1553         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1554         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1555         clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1556
1557         register_syscore_ops(&exynos4_clock_syscore_ops);
1558         s3c24xx_register_clock(&dummy_apb_pclk);
1559
1560         s3c_pwmclk_init();
1561 }