Pileus Git - ~andy/linux/blob - arch/arm/mach-exynos/clock.c

   1 /* linux/arch/arm/mach-exynos4/clock.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/syscore_ops.h>
  17
  18 #include <plat/cpu-freq.h>
  19 #include <plat/clock.h>
  20 #include <plat/cpu.h>
  21 #include <plat/pll.h>
  22 #include <plat/s5p-clock.h>
  23 #include <plat/clock-clksrc.h>
  24 #include <plat/pm.h>
  25
  26 #include <mach/map.h>
  27 #include <mach/regs-clock.h>
  28 #include <mach/sysmmu.h>
  29 #include <mach/exynos4-clock.h>
  30
  31 #include "common.h"
  32
  33 static struct sleep_save exynos4_clock_save[] = {
  34         SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
  35         SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
  36         SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
  37         SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
  38         SAVE_ITEM(S5P_CLKSRC_TOP0),
  39         SAVE_ITEM(S5P_CLKSRC_TOP1),
  40         SAVE_ITEM(S5P_CLKSRC_CAM),
  41         SAVE_ITEM(S5P_CLKSRC_TV),
  42         SAVE_ITEM(S5P_CLKSRC_MFC),
  43         SAVE_ITEM(S5P_CLKSRC_G3D),
  44         SAVE_ITEM(S5P_CLKSRC_LCD0),
  45         SAVE_ITEM(S5P_CLKSRC_MAUDIO),
  46         SAVE_ITEM(S5P_CLKSRC_FSYS),
  47         SAVE_ITEM(S5P_CLKSRC_PERIL0),
  48         SAVE_ITEM(S5P_CLKSRC_PERIL1),
  49         SAVE_ITEM(S5P_CLKDIV_CAM),
  50         SAVE_ITEM(S5P_CLKDIV_TV),
  51         SAVE_ITEM(S5P_CLKDIV_MFC),
  52         SAVE_ITEM(S5P_CLKDIV_G3D),
  53         SAVE_ITEM(S5P_CLKDIV_LCD0),
  54         SAVE_ITEM(S5P_CLKDIV_MAUDIO),
  55         SAVE_ITEM(S5P_CLKDIV_FSYS0),
  56         SAVE_ITEM(S5P_CLKDIV_FSYS1),
  57         SAVE_ITEM(S5P_CLKDIV_FSYS2),
  58         SAVE_ITEM(S5P_CLKDIV_FSYS3),
  59         SAVE_ITEM(S5P_CLKDIV_PERIL0),
  60         SAVE_ITEM(S5P_CLKDIV_PERIL1),
  61         SAVE_ITEM(S5P_CLKDIV_PERIL2),
  62         SAVE_ITEM(S5P_CLKDIV_PERIL3),
  63         SAVE_ITEM(S5P_CLKDIV_PERIL4),
  64         SAVE_ITEM(S5P_CLKDIV_PERIL5),
  65         SAVE_ITEM(S5P_CLKDIV_TOP),
  66         SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
  67         SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
  68         SAVE_ITEM(S5P_CLKSRC_MASK_TV),
  69         SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
  70         SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
  71         SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
  72         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
  73         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
  74         SAVE_ITEM(S5P_CLKDIV2_RATIO),
  75         SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
  76         SAVE_ITEM(S5P_CLKGATE_IP_CAM),
  77         SAVE_ITEM(S5P_CLKGATE_IP_TV),
  78         SAVE_ITEM(S5P_CLKGATE_IP_MFC),
  79         SAVE_ITEM(S5P_CLKGATE_IP_G3D),
  80         SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
  81         SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
  82         SAVE_ITEM(S5P_CLKGATE_IP_GPS),
  83         SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
  84         SAVE_ITEM(S5P_CLKGATE_BLOCK),
  85         SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
  86         SAVE_ITEM(S5P_CLKSRC_DMC),
  87         SAVE_ITEM(S5P_CLKDIV_DMC0),
  88         SAVE_ITEM(S5P_CLKDIV_DMC1),
  89         SAVE_ITEM(S5P_CLKGATE_IP_DMC),
  90         SAVE_ITEM(S5P_CLKSRC_CPU),
  91         SAVE_ITEM(S5P_CLKDIV_CPU),
  92         SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
  93         SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
  94         SAVE_ITEM(S5P_CLKGATE_IP_CPU),
  95 };
  96
  97 struct clk clk_sclk_hdmi27m = {
  98         .name           = "sclk_hdmi27m",
  99         .rate           = 27000000,
 100 };
 101
 102 struct clk clk_sclk_hdmiphy = {
 103         .name           = "sclk_hdmiphy",
 104 };
 105
 106 struct clk clk_sclk_usbphy0 = {
 107         .name           = "sclk_usbphy0",
 108         .rate           = 27000000,
 109 };
 110
 111 struct clk clk_sclk_usbphy1 = {
 112         .name           = "sclk_usbphy1",
 113 };
 114
 115 static struct clk dummy_apb_pclk = {
 116         .name           = "apb_pclk",
 117         .id             = -1,
 118 };
 119
 120 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 121 {
 122         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
 123 }
 124
 125 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 126 {
 127         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
 128 }
 129
 130 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 131 {
 132         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
 133 }
 134
 135 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 136 {
 137         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
 138 }
 139
 140 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 141 {
 142         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
 143 }
 144
 145 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 146 {
 147         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
 148 }
 149
 150 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 151 {
 152         return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
 153 }
 154
 155 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 156 {
 157         return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
 158 }
 159
 160 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 161 {
 162         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
 163 }
 164
 165 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 166 {
 167         return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
 168 }
 169
 170 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 171 {
 172         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
 173 }
 174
 175 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 176 {
 177         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 178 }
 179
 180 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 181 {
 182         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 183 }
 184
 185 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 186 {
 187         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 188 }
 189
 190 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 191 {
 192         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 193 }
 194
 195 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 196 {
 197         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 198 }
 199
 200 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 201 {
 202         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 203 }
 204
 205 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 206 {
 207         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
 208 }
 209
 210 /* Core list of CMU_CPU side */
 211
 212 static struct clksrc_clk clk_mout_apll = {
 213         .clk    = {
 214                 .name           = "mout_apll",
 215         },
 216         .sources        = &clk_src_apll,
 217         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 218 };
 219
 220 struct clksrc_clk clk_sclk_apll = {
 221         .clk    = {
 222                 .name           = "sclk_apll",
 223                 .parent         = &clk_mout_apll.clk,
 224         },
 225         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 226 };
 227
 228 struct clksrc_clk clk_mout_epll = {
 229         .clk    = {
 230                 .name           = "mout_epll",
 231         },
 232         .sources        = &clk_src_epll,
 233         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 234 };
 235
 236 struct clksrc_clk clk_mout_mpll = {
 237         .clk = {
 238                 .name           = "mout_mpll",
 239         },
 240         .sources        = &clk_src_mpll,
 241
 242         /* reg_src will be added in each SoCs' clock */
 243 };
 244
 245 static struct clk *clkset_moutcore_list[] = {
 246         [0] = &clk_mout_apll.clk,
 247         [1] = &clk_mout_mpll.clk,
 248 };
 249
 250 static struct clksrc_sources clkset_moutcore = {
 251         .sources        = clkset_moutcore_list,
 252         .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
 253 };
 254
 255 static struct clksrc_clk clk_moutcore = {
 256         .clk    = {
 257                 .name           = "moutcore",
 258         },
 259         .sources        = &clkset_moutcore,
 260         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
 261 };
 262
 263 static struct clksrc_clk clk_coreclk = {
 264         .clk    = {
 265                 .name           = "core_clk",
 266                 .parent         = &clk_moutcore.clk,
 267         },
 268         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
 269 };
 270
 271 static struct clksrc_clk clk_armclk = {
 272         .clk    = {
 273                 .name           = "armclk",
 274                 .parent         = &clk_coreclk.clk,
 275         },
 276 };
 277
 278 static struct clksrc_clk clk_aclk_corem0 = {
 279         .clk    = {
 280                 .name           = "aclk_corem0",
 281                 .parent         = &clk_coreclk.clk,
 282         },
 283         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 284 };
 285
 286 static struct clksrc_clk clk_aclk_cores = {
 287         .clk    = {
 288                 .name           = "aclk_cores",
 289                 .parent         = &clk_coreclk.clk,
 290         },
 291         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 292 };
 293
 294 static struct clksrc_clk clk_aclk_corem1 = {
 295         .clk    = {
 296                 .name           = "aclk_corem1",
 297                 .parent         = &clk_coreclk.clk,
 298         },
 299         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
 300 };
 301
 302 static struct clksrc_clk clk_periphclk = {
 303         .clk    = {
 304                 .name           = "periphclk",
 305                 .parent         = &clk_coreclk.clk,
 306         },
 307         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 308 };
 309
 310 /* Core list of CMU_CORE side */
 311
 312 struct clk *clkset_corebus_list[] = {
 313         [0] = &clk_mout_mpll.clk,
 314         [1] = &clk_sclk_apll.clk,
 315 };
 316
 317 struct clksrc_sources clkset_mout_corebus = {
 318         .sources        = clkset_corebus_list,
 319         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 320 };
 321
 322 static struct clksrc_clk clk_mout_corebus = {
 323         .clk    = {
 324                 .name           = "mout_corebus",
 325         },
 326         .sources        = &clkset_mout_corebus,
 327         .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
 328 };
 329
 330 static struct clksrc_clk clk_sclk_dmc = {
 331         .clk    = {
 332                 .name           = "sclk_dmc",
 333                 .parent         = &clk_mout_corebus.clk,
 334         },
 335         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
 336 };
 337
 338 static struct clksrc_clk clk_aclk_cored = {
 339         .clk    = {
 340                 .name           = "aclk_cored",
 341                 .parent         = &clk_sclk_dmc.clk,
 342         },
 343         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
 344 };
 345
 346 static struct clksrc_clk clk_aclk_corep = {
 347         .clk    = {
 348                 .name           = "aclk_corep",
 349                 .parent         = &clk_aclk_cored.clk,
 350         },
 351         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
 352 };
 353
 354 static struct clksrc_clk clk_aclk_acp = {
 355         .clk    = {
 356                 .name           = "aclk_acp",
 357                 .parent         = &clk_mout_corebus.clk,
 358         },
 359         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
 360 };
 361
 362 static struct clksrc_clk clk_pclk_acp = {
 363         .clk    = {
 364                 .name           = "pclk_acp",
 365                 .parent         = &clk_aclk_acp.clk,
 366         },
 367         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
 368 };
 369
 370 /* Core list of CMU_TOP side */
 371
 372 struct clk *clkset_aclk_top_list[] = {
 373         [0] = &clk_mout_mpll.clk,
 374         [1] = &clk_sclk_apll.clk,
 375 };
 376
 377 struct clksrc_sources clkset_aclk = {
 378         .sources        = clkset_aclk_top_list,
 379         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 380 };
 381
 382 static struct clksrc_clk clk_aclk_200 = {
 383         .clk    = {
 384                 .name           = "aclk_200",
 385         },
 386         .sources        = &clkset_aclk,
 387         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
 388         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 389 };
 390
 391 static struct clksrc_clk clk_aclk_100 = {
 392         .clk    = {
 393                 .name           = "aclk_100",
 394         },
 395         .sources        = &clkset_aclk,
 396         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
 397         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 398 };
 399
 400 static struct clksrc_clk clk_aclk_160 = {
 401         .clk    = {
 402                 .name           = "aclk_160",
 403         },
 404         .sources        = &clkset_aclk,
 405         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
 406         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 407 };
 408
 409 struct clksrc_clk clk_aclk_133 = {
 410         .clk    = {
 411                 .name           = "aclk_133",
 412         },
 413         .sources        = &clkset_aclk,
 414         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
 415         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 416 };
 417
 418 static struct clk *clkset_vpllsrc_list[] = {
 419         [0] = &clk_fin_vpll,
 420         [1] = &clk_sclk_hdmi27m,
 421 };
 422
 423 static struct clksrc_sources clkset_vpllsrc = {
 424         .sources        = clkset_vpllsrc_list,
 425         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 426 };
 427
 428 static struct clksrc_clk clk_vpllsrc = {
 429         .clk    = {
 430                 .name           = "vpll_src",
 431                 .enable         = exynos4_clksrc_mask_top_ctrl,
 432                 .ctrlbit        = (1 << 0),
 433         },
 434         .sources        = &clkset_vpllsrc,
 435         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
 436 };
 437
 438 static struct clk *clkset_sclk_vpll_list[] = {
 439         [0] = &clk_vpllsrc.clk,
 440         [1] = &clk_fout_vpll,
 441 };
 442
 443 static struct clksrc_sources clkset_sclk_vpll = {
 444         .sources        = clkset_sclk_vpll_list,
 445         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 446 };
 447
 448 struct clksrc_clk clk_sclk_vpll = {
 449         .clk    = {
 450                 .name           = "sclk_vpll",
 451         },
 452         .sources        = &clkset_sclk_vpll,
 453         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 454 };
 455
 456 static struct clk init_clocks_off[] = {
 457         {
 458                 .name           = "timers",
 459                 .parent         = &clk_aclk_100.clk,
 460                 .enable         = exynos4_clk_ip_peril_ctrl,
 461                 .ctrlbit        = (1<<24),
 462         }, {
 463                 .name           = "csis",
 464                 .devname        = "s5p-mipi-csis.0",
 465                 .enable         = exynos4_clk_ip_cam_ctrl,
 466                 .ctrlbit        = (1 << 4),
 467         }, {
 468                 .name           = "csis",
 469                 .devname        = "s5p-mipi-csis.1",
 470                 .enable         = exynos4_clk_ip_cam_ctrl,
 471                 .ctrlbit        = (1 << 5),
 472         }, {
 473                 .name           = "fimc",
 474                 .devname        = "exynos4-fimc.0",
 475                 .enable         = exynos4_clk_ip_cam_ctrl,
 476                 .ctrlbit        = (1 << 0),
 477         }, {
 478                 .name           = "fimc",
 479                 .devname        = "exynos4-fimc.1",
 480                 .enable         = exynos4_clk_ip_cam_ctrl,
 481                 .ctrlbit        = (1 << 1),
 482         }, {
 483                 .name           = "fimc",
 484                 .devname        = "exynos4-fimc.2",
 485                 .enable         = exynos4_clk_ip_cam_ctrl,
 486                 .ctrlbit        = (1 << 2),
 487         }, {
 488                 .name           = "fimc",
 489                 .devname        = "exynos4-fimc.3",
 490                 .enable         = exynos4_clk_ip_cam_ctrl,
 491                 .ctrlbit        = (1 << 3),
 492         }, {
 493                 .name           = "fimd",
 494                 .devname        = "exynos4-fb.0",
 495                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 496                 .ctrlbit        = (1 << 0),
 497         }, {
 498                 .name           = "hsmmc",
 499                 .devname        = "s3c-sdhci.0",
 500                 .parent         = &clk_aclk_133.clk,
 501                 .enable         = exynos4_clk_ip_fsys_ctrl,
 502                 .ctrlbit        = (1 << 5),
 503         }, {
 504                 .name           = "hsmmc",
 505                 .devname        = "s3c-sdhci.1",
 506                 .parent         = &clk_aclk_133.clk,
 507                 .enable         = exynos4_clk_ip_fsys_ctrl,
 508                 .ctrlbit        = (1 << 6),
 509         }, {
 510                 .name           = "hsmmc",
 511                 .devname        = "s3c-sdhci.2",
 512                 .parent         = &clk_aclk_133.clk,
 513                 .enable         = exynos4_clk_ip_fsys_ctrl,
 514                 .ctrlbit        = (1 << 7),
 515         }, {
 516                 .name           = "hsmmc",
 517                 .devname        = "s3c-sdhci.3",
 518                 .parent         = &clk_aclk_133.clk,
 519                 .enable         = exynos4_clk_ip_fsys_ctrl,
 520                 .ctrlbit        = (1 << 8),
 521         }, {
 522                 .name           = "dwmmc",
 523                 .parent         = &clk_aclk_133.clk,
 524                 .enable         = exynos4_clk_ip_fsys_ctrl,
 525                 .ctrlbit        = (1 << 9),
 526         }, {
 527                 .name           = "dac",
 528                 .devname        = "s5p-sdo",
 529                 .enable         = exynos4_clk_ip_tv_ctrl,
 530                 .ctrlbit        = (1 << 2),
 531         }, {
 532                 .name           = "mixer",
 533                 .devname        = "s5p-mixer",
 534                 .enable         = exynos4_clk_ip_tv_ctrl,
 535                 .ctrlbit        = (1 << 1),
 536         }, {
 537                 .name           = "vp",
 538                 .devname        = "s5p-mixer",
 539                 .enable         = exynos4_clk_ip_tv_ctrl,
 540                 .ctrlbit        = (1 << 0),
 541         }, {
 542                 .name           = "hdmi",
 543                 .devname        = "exynos4-hdmi",
 544                 .enable         = exynos4_clk_ip_tv_ctrl,
 545                 .ctrlbit        = (1 << 3),
 546         }, {
 547                 .name           = "hdmiphy",
 548                 .devname        = "exynos4-hdmi",
 549                 .enable         = exynos4_clk_hdmiphy_ctrl,
 550                 .ctrlbit        = (1 << 0),
 551         }, {
 552                 .name           = "dacphy",
 553                 .devname        = "s5p-sdo",
 554                 .enable         = exynos4_clk_dac_ctrl,
 555                 .ctrlbit        = (1 << 0),
 556         }, {
 557                 .name           = "dma",
 558                 .devname        = "dma-pl330.0",
 559                 .enable         = exynos4_clk_ip_fsys_ctrl,
 560                 .ctrlbit        = (1 << 0),
 561         }, {
 562                 .name           = "dma",
 563                 .devname        = "dma-pl330.1",
 564                 .enable         = exynos4_clk_ip_fsys_ctrl,
 565                 .ctrlbit        = (1 << 1),
 566         }, {
 567                 .name           = "adc",
 568                 .enable         = exynos4_clk_ip_peril_ctrl,
 569                 .ctrlbit        = (1 << 15),
 570         }, {
 571                 .name           = "keypad",
 572                 .enable         = exynos4_clk_ip_perir_ctrl,
 573                 .ctrlbit        = (1 << 16),
 574         }, {
 575                 .name           = "rtc",
 576                 .enable         = exynos4_clk_ip_perir_ctrl,
 577                 .ctrlbit        = (1 << 15),
 578         }, {
 579                 .name           = "watchdog",
 580                 .parent         = &clk_aclk_100.clk,
 581                 .enable         = exynos4_clk_ip_perir_ctrl,
 582                 .ctrlbit        = (1 << 14),
 583         }, {
 584                 .name           = "usbhost",
 585                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 586                 .ctrlbit        = (1 << 12),
 587         }, {
 588                 .name           = "otg",
 589                 .enable         = exynos4_clk_ip_fsys_ctrl,
 590                 .ctrlbit        = (1 << 13),
 591         }, {
 592                 .name           = "spi",
 593                 .devname        = "s3c64xx-spi.0",
 594                 .enable         = exynos4_clk_ip_peril_ctrl,
 595                 .ctrlbit        = (1 << 16),
 596         }, {
 597                 .name           = "spi",
 598                 .devname        = "s3c64xx-spi.1",
 599                 .enable         = exynos4_clk_ip_peril_ctrl,
 600                 .ctrlbit        = (1 << 17),
 601         }, {
 602                 .name           = "spi",
 603                 .devname        = "s3c64xx-spi.2",
 604                 .enable         = exynos4_clk_ip_peril_ctrl,
 605                 .ctrlbit        = (1 << 18),
 606         }, {
 607                 .name           = "iis",
 608                 .devname        = "samsung-i2s.0",
 609                 .enable         = exynos4_clk_ip_peril_ctrl,
 610                 .ctrlbit        = (1 << 19),
 611         }, {
 612                 .name           = "iis",
 613                 .devname        = "samsung-i2s.1",
 614                 .enable         = exynos4_clk_ip_peril_ctrl,
 615                 .ctrlbit        = (1 << 20),
 616         }, {
 617                 .name           = "iis",
 618                 .devname        = "samsung-i2s.2",
 619                 .enable         = exynos4_clk_ip_peril_ctrl,
 620                 .ctrlbit        = (1 << 21),
 621         }, {
 622                 .name           = "ac97",
 623                 .devname        = "samsung-ac97",
 624                 .enable         = exynos4_clk_ip_peril_ctrl,
 625                 .ctrlbit        = (1 << 27),
 626         }, {
 627                 .name           = "fimg2d",
 628                 .enable         = exynos4_clk_ip_image_ctrl,
 629                 .ctrlbit        = (1 << 0),
 630         }, {
 631                 .name           = "mfc",
 632                 .devname        = "s5p-mfc",
 633                 .enable         = exynos4_clk_ip_mfc_ctrl,
 634                 .ctrlbit        = (1 << 0),
 635         }, {
 636                 .name           = "i2c",
 637                 .devname        = "s3c2440-i2c.0",
 638                 .parent         = &clk_aclk_100.clk,
 639                 .enable         = exynos4_clk_ip_peril_ctrl,
 640                 .ctrlbit        = (1 << 6),
 641         }, {
 642                 .name           = "i2c",
 643                 .devname        = "s3c2440-i2c.1",
 644                 .parent         = &clk_aclk_100.clk,
 645                 .enable         = exynos4_clk_ip_peril_ctrl,
 646                 .ctrlbit        = (1 << 7),
 647         }, {
 648                 .name           = "i2c",
 649                 .devname        = "s3c2440-i2c.2",
 650                 .parent         = &clk_aclk_100.clk,
 651                 .enable         = exynos4_clk_ip_peril_ctrl,
 652                 .ctrlbit        = (1 << 8),
 653         }, {
 654                 .name           = "i2c",
 655                 .devname        = "s3c2440-i2c.3",
 656                 .parent         = &clk_aclk_100.clk,
 657                 .enable         = exynos4_clk_ip_peril_ctrl,
 658                 .ctrlbit        = (1 << 9),
 659         }, {
 660                 .name           = "i2c",
 661                 .devname        = "s3c2440-i2c.4",
 662                 .parent         = &clk_aclk_100.clk,
 663                 .enable         = exynos4_clk_ip_peril_ctrl,
 664                 .ctrlbit        = (1 << 10),
 665         }, {
 666                 .name           = "i2c",
 667                 .devname        = "s3c2440-i2c.5",
 668                 .parent         = &clk_aclk_100.clk,
 669                 .enable         = exynos4_clk_ip_peril_ctrl,
 670                 .ctrlbit        = (1 << 11),
 671         }, {
 672                 .name           = "i2c",
 673                 .devname        = "s3c2440-i2c.6",
 674                 .parent         = &clk_aclk_100.clk,
 675                 .enable         = exynos4_clk_ip_peril_ctrl,
 676                 .ctrlbit        = (1 << 12),
 677         }, {
 678                 .name           = "i2c",
 679                 .devname        = "s3c2440-i2c.7",
 680                 .parent         = &clk_aclk_100.clk,
 681                 .enable         = exynos4_clk_ip_peril_ctrl,
 682                 .ctrlbit        = (1 << 13),
 683         }, {
 684                 .name           = "i2c",
 685                 .devname        = "s3c2440-hdmiphy-i2c",
 686                 .parent         = &clk_aclk_100.clk,
 687                 .enable         = exynos4_clk_ip_peril_ctrl,
 688                 .ctrlbit        = (1 << 14),
 689         }, {
 690                 .name           = "SYSMMU_MDMA",
 691                 .enable         = exynos4_clk_ip_image_ctrl,
 692                 .ctrlbit        = (1 << 5),
 693         }, {
 694                 .name           = "SYSMMU_FIMC0",
 695                 .enable         = exynos4_clk_ip_cam_ctrl,
 696                 .ctrlbit        = (1 << 7),
 697         }, {
 698                 .name           = "SYSMMU_FIMC1",
 699                 .enable         = exynos4_clk_ip_cam_ctrl,
 700                 .ctrlbit        = (1 << 8),
 701         }, {
 702                 .name           = "SYSMMU_FIMC2",
 703                 .enable         = exynos4_clk_ip_cam_ctrl,
 704                 .ctrlbit        = (1 << 9),
 705         }, {
 706                 .name           = "SYSMMU_FIMC3",
 707                 .enable         = exynos4_clk_ip_cam_ctrl,
 708                 .ctrlbit        = (1 << 10),
 709         }, {
 710                 .name           = "SYSMMU_JPEG",
 711                 .enable         = exynos4_clk_ip_cam_ctrl,
 712                 .ctrlbit        = (1 << 11),
 713         }, {
 714                 .name           = "SYSMMU_FIMD0",
 715                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 716                 .ctrlbit        = (1 << 4),
 717         }, {
 718                 .name           = "SYSMMU_FIMD1",
 719                 .enable         = exynos4_clk_ip_lcd1_ctrl,
 720                 .ctrlbit        = (1 << 4),
 721         }, {
 722                 .name           = "SYSMMU_PCIe",
 723                 .enable         = exynos4_clk_ip_fsys_ctrl,
 724                 .ctrlbit        = (1 << 18),
 725         }, {
 726                 .name           = "SYSMMU_G2D",
 727                 .enable         = exynos4_clk_ip_image_ctrl,
 728                 .ctrlbit        = (1 << 3),
 729         }, {
 730                 .name           = "SYSMMU_ROTATOR",
 731                 .enable         = exynos4_clk_ip_image_ctrl,
 732                 .ctrlbit        = (1 << 4),
 733         }, {
 734                 .name           = "SYSMMU_TV",
 735                 .enable         = exynos4_clk_ip_tv_ctrl,
 736                 .ctrlbit        = (1 << 4),
 737         }, {
 738                 .name           = "SYSMMU_MFC_L",
 739                 .enable         = exynos4_clk_ip_mfc_ctrl,
 740                 .ctrlbit        = (1 << 1),
 741         }, {
 742                 .name           = "SYSMMU_MFC_R",
 743                 .enable         = exynos4_clk_ip_mfc_ctrl,
 744                 .ctrlbit        = (1 << 2),
 745         }
 746 };
 747
 748 static struct clk init_clocks[] = {
 749         {
 750                 .name           = "uart",
 751                 .devname        = "s5pv210-uart.0",
 752                 .enable         = exynos4_clk_ip_peril_ctrl,
 753                 .ctrlbit        = (1 << 0),
 754         }, {
 755                 .name           = "uart",
 756                 .devname        = "s5pv210-uart.1",
 757                 .enable         = exynos4_clk_ip_peril_ctrl,
 758                 .ctrlbit        = (1 << 1),
 759         }, {
 760                 .name           = "uart",
 761                 .devname        = "s5pv210-uart.2",
 762                 .enable         = exynos4_clk_ip_peril_ctrl,
 763                 .ctrlbit        = (1 << 2),
 764         }, {
 765                 .name           = "uart",
 766                 .devname        = "s5pv210-uart.3",
 767                 .enable         = exynos4_clk_ip_peril_ctrl,
 768                 .ctrlbit        = (1 << 3),
 769         }, {
 770                 .name           = "uart",
 771                 .devname        = "s5pv210-uart.4",
 772                 .enable         = exynos4_clk_ip_peril_ctrl,
 773                 .ctrlbit        = (1 << 4),
 774         }, {
 775                 .name           = "uart",
 776                 .devname        = "s5pv210-uart.5",
 777                 .enable         = exynos4_clk_ip_peril_ctrl,
 778                 .ctrlbit        = (1 << 5),
 779         }
 780 };
 781
 782 struct clk *clkset_group_list[] = {
 783         [0] = &clk_ext_xtal_mux,
 784         [1] = &clk_xusbxti,
 785         [2] = &clk_sclk_hdmi27m,
 786         [3] = &clk_sclk_usbphy0,
 787         [4] = &clk_sclk_usbphy1,
 788         [5] = &clk_sclk_hdmiphy,
 789         [6] = &clk_mout_mpll.clk,
 790         [7] = &clk_mout_epll.clk,
 791         [8] = &clk_sclk_vpll.clk,
 792 };
 793
 794 struct clksrc_sources clkset_group = {
 795         .sources        = clkset_group_list,
 796         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 797 };
 798
 799 static struct clk *clkset_mout_g2d0_list[] = {
 800         [0] = &clk_mout_mpll.clk,
 801         [1] = &clk_sclk_apll.clk,
 802 };
 803
 804 static struct clksrc_sources clkset_mout_g2d0 = {
 805         .sources        = clkset_mout_g2d0_list,
 806         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
 807 };
 808
 809 static struct clksrc_clk clk_mout_g2d0 = {
 810         .clk    = {
 811                 .name           = "mout_g2d0",
 812         },
 813         .sources        = &clkset_mout_g2d0,
 814         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 815 };
 816
 817 static struct clk *clkset_mout_g2d1_list[] = {
 818         [0] = &clk_mout_epll.clk,
 819         [1] = &clk_sclk_vpll.clk,
 820 };
 821
 822 static struct clksrc_sources clkset_mout_g2d1 = {
 823         .sources        = clkset_mout_g2d1_list,
 824         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
 825 };
 826
 827 static struct clksrc_clk clk_mout_g2d1 = {
 828         .clk    = {
 829                 .name           = "mout_g2d1",
 830         },
 831         .sources        = &clkset_mout_g2d1,
 832         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 833 };
 834
 835 static struct clk *clkset_mout_g2d_list[] = {
 836         [0] = &clk_mout_g2d0.clk,
 837         [1] = &clk_mout_g2d1.clk,
 838 };
 839
 840 static struct clksrc_sources clkset_mout_g2d = {
 841         .sources        = clkset_mout_g2d_list,
 842         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
 843 };
 844
 845 static struct clk *clkset_mout_mfc0_list[] = {
 846         [0] = &clk_mout_mpll.clk,
 847         [1] = &clk_sclk_apll.clk,
 848 };
 849
 850 static struct clksrc_sources clkset_mout_mfc0 = {
 851         .sources        = clkset_mout_mfc0_list,
 852         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
 853 };
 854
 855 static struct clksrc_clk clk_mout_mfc0 = {
 856         .clk    = {
 857                 .name           = "mout_mfc0",
 858         },
 859         .sources        = &clkset_mout_mfc0,
 860         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
 861 };
 862
 863 static struct clk *clkset_mout_mfc1_list[] = {
 864         [0] = &clk_mout_epll.clk,
 865         [1] = &clk_sclk_vpll.clk,
 866 };
 867
 868 static struct clksrc_sources clkset_mout_mfc1 = {
 869         .sources        = clkset_mout_mfc1_list,
 870         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
 871 };
 872
 873 static struct clksrc_clk clk_mout_mfc1 = {
 874         .clk    = {
 875                 .name           = "mout_mfc1",
 876         },
 877         .sources        = &clkset_mout_mfc1,
 878         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
 879 };
 880
 881 static struct clk *clkset_mout_mfc_list[] = {
 882         [0] = &clk_mout_mfc0.clk,
 883         [1] = &clk_mout_mfc1.clk,
 884 };
 885
 886 static struct clksrc_sources clkset_mout_mfc = {
 887         .sources        = clkset_mout_mfc_list,
 888         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
 889 };
 890
 891 static struct clk *clkset_sclk_dac_list[] = {
 892         [0] = &clk_sclk_vpll.clk,
 893         [1] = &clk_sclk_hdmiphy,
 894 };
 895
 896 static struct clksrc_sources clkset_sclk_dac = {
 897         .sources        = clkset_sclk_dac_list,
 898         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 899 };
 900
 901 static struct clksrc_clk clk_sclk_dac = {
 902         .clk            = {
 903                 .name           = "sclk_dac",
 904                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 905                 .ctrlbit        = (1 << 8),
 906         },
 907         .sources = &clkset_sclk_dac,
 908         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
 909 };
 910
 911 static struct clksrc_clk clk_sclk_pixel = {
 912         .clk            = {
 913                 .name           = "sclk_pixel",
 914                 .parent = &clk_sclk_vpll.clk,
 915         },
 916         .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
 917 };
 918
 919 static struct clk *clkset_sclk_hdmi_list[] = {
 920         [0] = &clk_sclk_pixel.clk,
 921         [1] = &clk_sclk_hdmiphy,
 922 };
 923
 924 static struct clksrc_sources clkset_sclk_hdmi = {
 925         .sources        = clkset_sclk_hdmi_list,
 926         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 927 };
 928
 929 static struct clksrc_clk clk_sclk_hdmi = {
 930         .clk            = {
 931                 .name           = "sclk_hdmi",
 932                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 933                 .ctrlbit        = (1 << 0),
 934         },
 935         .sources = &clkset_sclk_hdmi,
 936         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
 937 };
 938
 939 static struct clk *clkset_sclk_mixer_list[] = {
 940         [0] = &clk_sclk_dac.clk,
 941         [1] = &clk_sclk_hdmi.clk,
 942 };
 943
 944 static struct clksrc_sources clkset_sclk_mixer = {
 945         .sources        = clkset_sclk_mixer_list,
 946         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 947 };
 948
 949 static struct clksrc_clk clk_sclk_mixer = {
 950         .clk            = {
 951                 .name           = "sclk_mixer",
 952                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 953                 .ctrlbit        = (1 << 4),
 954         },
 955         .sources = &clkset_sclk_mixer,
 956         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
 957 };
 958
 959 static struct clksrc_clk *sclk_tv[] = {
 960         &clk_sclk_dac,
 961         &clk_sclk_pixel,
 962         &clk_sclk_hdmi,
 963         &clk_sclk_mixer,
 964 };
 965
 966 static struct clksrc_clk clk_dout_mmc0 = {
 967         .clk            = {
 968                 .name           = "dout_mmc0",
 969         },
 970         .sources = &clkset_group,
 971         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
 972         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 973 };
 974
 975 static struct clksrc_clk clk_dout_mmc1 = {
 976         .clk            = {
 977                 .name           = "dout_mmc1",
 978         },
 979         .sources = &clkset_group,
 980         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
 981         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 982 };
 983
 984 static struct clksrc_clk clk_dout_mmc2 = {
 985         .clk            = {
 986                 .name           = "dout_mmc2",
 987         },
 988         .sources = &clkset_group,
 989         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
 990         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 991 };
 992
 993 static struct clksrc_clk clk_dout_mmc3 = {
 994         .clk            = {
 995                 .name           = "dout_mmc3",
 996         },
 997         .sources = &clkset_group,
 998         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
 999         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1000 };
1001
1002 static struct clksrc_clk clk_dout_mmc4 = {
1003         .clk            = {
1004                 .name           = "dout_mmc4",
1005         },
1006         .sources = &clkset_group,
1007         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1008         .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1009 };
1010
1011 static struct clksrc_clk clksrcs[] = {
1012         {
1013                 .clk    = {
1014                         .name           = "uclk1",
1015                         .devname        = "s5pv210-uart.0",
1016                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1017                         .ctrlbit        = (1 << 0),
1018                 },
1019                 .sources = &clkset_group,
1020                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1021                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1022         }, {
1023                 .clk            = {
1024                         .name           = "uclk1",
1025                         .devname        = "s5pv210-uart.1",
1026                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1027                         .ctrlbit        = (1 << 4),
1028                 },
1029                 .sources = &clkset_group,
1030                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1031                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1032         }, {
1033                 .clk            = {
1034                         .name           = "uclk1",
1035                         .devname        = "s5pv210-uart.2",
1036                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1037                         .ctrlbit        = (1 << 8),
1038                 },
1039                 .sources = &clkset_group,
1040                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1041                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1042         }, {
1043                 .clk            = {
1044                         .name           = "uclk1",
1045                         .devname        = "s5pv210-uart.3",
1046                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1047                         .ctrlbit        = (1 << 12),
1048                 },
1049                 .sources = &clkset_group,
1050                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1051                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1052         }, {
1053                 .clk            = {
1054                         .name           = "sclk_pwm",
1055                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1056                         .ctrlbit        = (1 << 24),
1057                 },
1058                 .sources = &clkset_group,
1059                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1060                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1061         }, {
1062                 .clk            = {
1063                         .name           = "sclk_csis",
1064                         .devname        = "s5p-mipi-csis.0",
1065                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1066                         .ctrlbit        = (1 << 24),
1067                 },
1068                 .sources = &clkset_group,
1069                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1070                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1071         }, {
1072                 .clk            = {
1073                         .name           = "sclk_csis",
1074                         .devname        = "s5p-mipi-csis.1",
1075                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1076                         .ctrlbit        = (1 << 28),
1077                 },
1078                 .sources = &clkset_group,
1079                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1080                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1081         }, {
1082                 .clk            = {
1083                         .name           = "sclk_cam0",
1084                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1085                         .ctrlbit        = (1 << 16),
1086                 },
1087                 .sources = &clkset_group,
1088                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1089                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1090         }, {
1091                 .clk            = {
1092                         .name           = "sclk_cam1",
1093                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1094                         .ctrlbit        = (1 << 20),
1095                 },
1096                 .sources = &clkset_group,
1097                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1098                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1099         }, {
1100                 .clk            = {
1101                         .name           = "sclk_fimc",
1102                         .devname        = "exynos4-fimc.0",
1103                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1104                         .ctrlbit        = (1 << 0),
1105                 },
1106                 .sources = &clkset_group,
1107                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1108                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1109         }, {
1110                 .clk            = {
1111                         .name           = "sclk_fimc",
1112                         .devname        = "exynos4-fimc.1",
1113                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1114                         .ctrlbit        = (1 << 4),
1115                 },
1116                 .sources = &clkset_group,
1117                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1118                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1119         }, {
1120                 .clk            = {
1121                         .name           = "sclk_fimc",
1122                         .devname        = "exynos4-fimc.2",
1123                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1124                         .ctrlbit        = (1 << 8),
1125                 },
1126                 .sources = &clkset_group,
1127                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1128                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1129         }, {
1130                 .clk            = {
1131                         .name           = "sclk_fimc",
1132                         .devname        = "exynos4-fimc.3",
1133                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1134                         .ctrlbit        = (1 << 12),
1135                 },
1136                 .sources = &clkset_group,
1137                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1138                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1139         }, {
1140                 .clk            = {
1141                         .name           = "sclk_fimd",
1142                         .devname        = "exynos4-fb.0",
1143                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1144                         .ctrlbit        = (1 << 0),
1145                 },
1146                 .sources = &clkset_group,
1147                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1148                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1149         }, {
1150                 .clk            = {
1151                         .name           = "sclk_spi",
1152                         .devname        = "s3c64xx-spi.0",
1153                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1154                         .ctrlbit        = (1 << 16),
1155                 },
1156                 .sources = &clkset_group,
1157                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1158                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1159         }, {
1160                 .clk            = {
1161                         .name           = "sclk_spi",
1162                         .devname        = "s3c64xx-spi.1",
1163                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1164                         .ctrlbit        = (1 << 20),
1165                 },
1166                 .sources = &clkset_group,
1167                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1168                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1169         }, {
1170                 .clk            = {
1171                         .name           = "sclk_spi",
1172                         .devname        = "s3c64xx-spi.2",
1173                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1174                         .ctrlbit        = (1 << 24),
1175                 },
1176                 .sources = &clkset_group,
1177                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1178                 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1179         }, {
1180                 .clk            = {
1181                         .name           = "sclk_fimg2d",
1182                 },
1183                 .sources = &clkset_mout_g2d,
1184                 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1185                 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1186         }, {
1187                 .clk            = {
1188                         .name           = "sclk_mfc",
1189                         .devname        = "s5p-mfc",
1190                 },
1191                 .sources = &clkset_mout_mfc,
1192                 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1193                 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1194         }, {
1195                 .clk            = {
1196                         .name           = "sclk_mmc",
1197                         .devname        = "s3c-sdhci.0",
1198                         .parent         = &clk_dout_mmc0.clk,
1199                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1200                         .ctrlbit        = (1 << 0),
1201                 },
1202                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1203         }, {
1204                 .clk            = {
1205                         .name           = "sclk_mmc",
1206                         .devname        = "s3c-sdhci.1",
1207                         .parent         = &clk_dout_mmc1.clk,
1208                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1209                         .ctrlbit        = (1 << 4),
1210                 },
1211                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1212         }, {
1213                 .clk            = {
1214                         .name           = "sclk_mmc",
1215                         .devname        = "s3c-sdhci.2",
1216                         .parent         = &clk_dout_mmc2.clk,
1217                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1218                         .ctrlbit        = (1 << 8),
1219                 },
1220                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1221         }, {
1222                 .clk            = {
1223                         .name           = "sclk_mmc",
1224                         .devname        = "s3c-sdhci.3",
1225                         .parent         = &clk_dout_mmc3.clk,
1226                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1227                         .ctrlbit        = (1 << 12),
1228                 },
1229                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1230         }, {
1231                 .clk            = {
1232                         .name           = "sclk_dwmmc",
1233                         .parent         = &clk_dout_mmc4.clk,
1234                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1235                         .ctrlbit        = (1 << 16),
1236                 },
1237                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1238         }
1239 };
1240
1241 /* Clock initialization code */
1242 static struct clksrc_clk *sysclks[] = {
1243         &clk_mout_apll,
1244         &clk_sclk_apll,
1245         &clk_mout_epll,
1246         &clk_mout_mpll,
1247         &clk_moutcore,
1248         &clk_coreclk,
1249         &clk_armclk,
1250         &clk_aclk_corem0,
1251         &clk_aclk_cores,
1252         &clk_aclk_corem1,
1253         &clk_periphclk,
1254         &clk_mout_corebus,
1255         &clk_sclk_dmc,
1256         &clk_aclk_cored,
1257         &clk_aclk_corep,
1258         &clk_aclk_acp,
1259         &clk_pclk_acp,
1260         &clk_vpllsrc,
1261         &clk_sclk_vpll,
1262         &clk_aclk_200,
1263         &clk_aclk_100,
1264         &clk_aclk_160,
1265         &clk_aclk_133,
1266         &clk_dout_mmc0,
1267         &clk_dout_mmc1,
1268         &clk_dout_mmc2,
1269         &clk_dout_mmc3,
1270         &clk_dout_mmc4,
1271         &clk_mout_mfc0,
1272         &clk_mout_mfc1,
1273 };
1274
1275 static int xtal_rate;
1276
1277 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1278 {
1279         if (soc_is_exynos4210())
1280                 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1281                                         pll_4508);
1282         else if (soc_is_exynos4212() || soc_is_exynos4412())
1283                 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1284         else
1285                 return 0;
1286 }
1287
1288 static struct clk_ops exynos4_fout_apll_ops = {
1289         .get_rate = exynos4_fout_apll_get_rate,
1290 };
1291
1292 static u32 vpll_div[][8] = {
1293         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
1294         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1295 };
1296
1297 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1298 {
1299         return clk->rate;
1300 }
1301
1302 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1303 {
1304         unsigned int vpll_con0, vpll_con1 = 0;
1305         unsigned int i;
1306
1307         /* Return if nothing changed */
1308         if (clk->rate == rate)
1309                 return 0;
1310
1311         vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1312         vpll_con0 &= ~(0x1 << 27 |                                      \
1313                         PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
1314                         PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
1315                         PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1316
1317         vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1318         vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
1319                         PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1320                         PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1321
1322         for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1323                 if (vpll_div[i][0] == rate) {
1324                         vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1325                         vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1326                         vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1327                         vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1328                         vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1329                         vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1330                         vpll_con0 |= vpll_div[i][7] << 27;
1331                         break;
1332                 }
1333         }
1334
1335         if (i == ARRAY_SIZE(vpll_div)) {
1336                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1337                                 __func__);
1338                 return -EINVAL;
1339         }
1340
1341         __raw_writel(vpll_con0, S5P_VPLL_CON0);
1342         __raw_writel(vpll_con1, S5P_VPLL_CON1);
1343
1344         /* Wait for VPLL lock */
1345         while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1346                 continue;
1347
1348         clk->rate = rate;
1349         return 0;
1350 }
1351
1352 static struct clk_ops exynos4_vpll_ops = {
1353         .get_rate = exynos4_vpll_get_rate,
1354         .set_rate = exynos4_vpll_set_rate,
1355 };
1356
1357 void __init_or_cpufreq exynos4_setup_clocks(void)
1358 {
1359         struct clk *xtal_clk;
1360         unsigned long apll = 0;
1361         unsigned long mpll = 0;
1362         unsigned long epll = 0;
1363         unsigned long vpll = 0;
1364         unsigned long vpllsrc;
1365         unsigned long xtal;
1366         unsigned long armclk;
1367         unsigned long sclk_dmc;
1368         unsigned long aclk_200;
1369         unsigned long aclk_100;
1370         unsigned long aclk_160;
1371         unsigned long aclk_133;
1372         unsigned int ptr;
1373
1374         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1375
1376         xtal_clk = clk_get(NULL, "xtal");
1377         BUG_ON(IS_ERR(xtal_clk));
1378
1379         xtal = clk_get_rate(xtal_clk);
1380
1381         xtal_rate = xtal;
1382
1383         clk_put(xtal_clk);
1384
1385         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1386
1387         if (soc_is_exynos4210()) {
1388                 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1389                                         pll_4508);
1390                 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1391                                         pll_4508);
1392                 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1393                                         __raw_readl(S5P_EPLL_CON1), pll_4600);
1394
1395                 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1396                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1397                                         __raw_readl(S5P_VPLL_CON1), pll_4650c);
1398         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1399                 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1400                 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1401                 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1402                                         __raw_readl(S5P_EPLL_CON1));
1403
1404                 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1405                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1406                                         __raw_readl(S5P_VPLL_CON1));
1407         } else {
1408                 /* nothing */
1409         }
1410
1411         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1412         clk_fout_mpll.rate = mpll;
1413         clk_fout_epll.rate = epll;
1414         clk_fout_vpll.ops = &exynos4_vpll_ops;
1415         clk_fout_vpll.rate = vpll;
1416
1417         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1418                         apll, mpll, epll, vpll);
1419
1420         armclk = clk_get_rate(&clk_armclk.clk);
1421         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1422
1423         aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1424         aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1425         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1426         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1427
1428         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1429                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1430                         armclk, sclk_dmc, aclk_200,
1431                         aclk_100, aclk_160, aclk_133);
1432
1433         clk_f.rate = armclk;
1434         clk_h.rate = sclk_dmc;
1435         clk_p.rate = aclk_100;
1436
1437         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1438                 s3c_set_clksrc(&clksrcs[ptr], true);
1439 }
1440
1441 static struct clk *clks[] __initdata = {
1442         &clk_sclk_hdmi27m,
1443         &clk_sclk_hdmiphy,
1444         &clk_sclk_usbphy0,
1445         &clk_sclk_usbphy1,
1446 };
1447
1448 #ifdef CONFIG_PM_SLEEP
1449 static int exynos4_clock_suspend(void)
1450 {
1451         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1452         return 0;
1453 }
1454
1455 static void exynos4_clock_resume(void)
1456 {
1457         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1458 }
1459
1460 #else
1461 #define exynos4_clock_suspend NULL
1462 #define exynos4_clock_resume NULL
1463 #endif
1464
1465 struct syscore_ops exynos4_clock_syscore_ops = {
1466         .suspend        = exynos4_clock_suspend,
1467         .resume         = exynos4_clock_resume,
1468 };
1469
1470 void __init exynos4_register_clocks(void)
1471 {
1472         int ptr;
1473
1474         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1475
1476         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1477                 s3c_register_clksrc(sysclks[ptr], 1);
1478
1479         for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1480                 s3c_register_clksrc(sclk_tv[ptr], 1);
1481
1482         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1483         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1484
1485         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1486         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1487
1488         register_syscore_ops(&exynos4_clock_syscore_ops);
1489         s3c24xx_register_clock(&dummy_apb_pclk);
1490
1491         s3c_pwmclk_init();
1492 }