2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Clock support for EXYNOS5 SoCs
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/err.h>
15 #include <linux/syscore_ops.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
26 #include <mach/regs-clock.h>
30 #ifdef CONFIG_PM_SLEEP
31 static struct sleep_save exynos5_clock_save[] = {
32 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
33 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
34 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
35 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
36 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
37 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
38 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
39 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
40 SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
41 SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
42 SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
43 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
44 SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
45 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
46 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
47 SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
48 SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
49 SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
50 SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
51 SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
52 SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
53 SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
54 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
55 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
56 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
57 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
58 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
59 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
60 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
61 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
62 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
63 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
64 SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
65 SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
66 SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
67 SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
68 SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
69 SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
70 SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
71 SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
72 SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
73 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
74 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
75 SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
76 SAVE_ITEM(EXYNOS5_EPLL_CON0),
77 SAVE_ITEM(EXYNOS5_EPLL_CON1),
78 SAVE_ITEM(EXYNOS5_EPLL_CON2),
79 SAVE_ITEM(EXYNOS5_VPLL_CON0),
80 SAVE_ITEM(EXYNOS5_VPLL_CON1),
81 SAVE_ITEM(EXYNOS5_VPLL_CON2),
82 SAVE_ITEM(EXYNOS5_PWR_CTRL1),
83 SAVE_ITEM(EXYNOS5_PWR_CTRL2),
87 static struct clk exynos5_clk_sclk_dptxphy = {
91 static struct clk exynos5_clk_sclk_hdmi24m = {
92 .name = "sclk_hdmi24m",
96 static struct clk exynos5_clk_sclk_hdmi27m = {
97 .name = "sclk_hdmi27m",
101 static struct clk exynos5_clk_sclk_hdmiphy = {
102 .name = "sclk_hdmiphy",
105 static struct clk exynos5_clk_sclk_usbphy = {
106 .name = "sclk_usbphy",
110 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
112 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
115 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
117 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
120 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
122 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
125 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
127 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
130 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
132 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
135 static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
137 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
140 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
142 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
145 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
147 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
150 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
152 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
155 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
157 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
160 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
162 return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
165 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
167 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
170 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
172 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
175 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
177 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
180 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
182 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
185 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
187 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
190 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
192 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
195 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
197 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
200 static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
202 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
205 /* Core list of CMU_CPU side */
207 static struct clksrc_clk exynos5_clk_mout_apll = {
211 .sources = &clk_src_apll,
212 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
215 static struct clksrc_clk exynos5_clk_sclk_apll = {
218 .parent = &exynos5_clk_mout_apll.clk,
220 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
223 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
225 .name = "mout_bpll_fout",
227 .sources = &clk_src_bpll_fout,
228 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
231 static struct clk *exynos5_clk_src_bpll_list[] = {
233 [1] = &exynos5_clk_mout_bpll_fout.clk,
236 static struct clksrc_sources exynos5_clk_src_bpll = {
237 .sources = exynos5_clk_src_bpll_list,
238 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
241 static struct clksrc_clk exynos5_clk_mout_bpll = {
245 .sources = &exynos5_clk_src_bpll,
246 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
249 static struct clk *exynos5_clk_src_bpll_user_list[] = {
251 [1] = &exynos5_clk_mout_bpll.clk,
254 static struct clksrc_sources exynos5_clk_src_bpll_user = {
255 .sources = exynos5_clk_src_bpll_user_list,
256 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
259 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
261 .name = "mout_bpll_user",
263 .sources = &exynos5_clk_src_bpll_user,
264 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
267 static struct clksrc_clk exynos5_clk_mout_cpll = {
271 .sources = &clk_src_cpll,
272 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
275 static struct clksrc_clk exynos5_clk_mout_epll = {
279 .sources = &clk_src_epll,
280 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
283 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
285 .name = "mout_mpll_fout",
287 .sources = &clk_src_mpll_fout,
288 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
291 static struct clk *exynos5_clk_src_mpll_list[] = {
293 [1] = &exynos5_clk_mout_mpll_fout.clk,
296 static struct clksrc_sources exynos5_clk_src_mpll = {
297 .sources = exynos5_clk_src_mpll_list,
298 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
301 static struct clksrc_clk exynos5_clk_mout_mpll = {
305 .sources = &exynos5_clk_src_mpll,
306 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
309 static struct clk *exynos_clkset_vpllsrc_list[] = {
311 [1] = &exynos5_clk_sclk_hdmi27m,
314 static struct clksrc_sources exynos5_clkset_vpllsrc = {
315 .sources = exynos_clkset_vpllsrc_list,
316 .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
319 static struct clksrc_clk exynos5_clk_vpllsrc = {
322 .enable = exynos5_clksrc_mask_top_ctrl,
325 .sources = &exynos5_clkset_vpllsrc,
326 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
329 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
330 [0] = &exynos5_clk_vpllsrc.clk,
331 [1] = &clk_fout_vpll,
334 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
335 .sources = exynos5_clkset_sclk_vpll_list,
336 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
339 static struct clksrc_clk exynos5_clk_sclk_vpll = {
343 .sources = &exynos5_clkset_sclk_vpll,
344 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
347 static struct clksrc_clk exynos5_clk_sclk_pixel = {
349 .name = "sclk_pixel",
350 .parent = &exynos5_clk_sclk_vpll.clk,
352 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
355 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
356 [0] = &exynos5_clk_sclk_pixel.clk,
357 [1] = &exynos5_clk_sclk_hdmiphy,
360 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
361 .sources = exynos5_clkset_sclk_hdmi_list,
362 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
365 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
368 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
369 .ctrlbit = (1 << 20),
371 .sources = &exynos5_clkset_sclk_hdmi,
372 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
375 static struct clksrc_clk *exynos5_sclk_tv[] = {
376 &exynos5_clk_sclk_pixel,
377 &exynos5_clk_sclk_hdmi,
380 static struct clk *exynos5_clk_src_mpll_user_list[] = {
382 [1] = &exynos5_clk_mout_mpll.clk,
385 static struct clksrc_sources exynos5_clk_src_mpll_user = {
386 .sources = exynos5_clk_src_mpll_user_list,
387 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
390 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
392 .name = "mout_mpll_user",
394 .sources = &exynos5_clk_src_mpll_user,
395 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
398 static struct clk *exynos5_clkset_mout_cpu_list[] = {
399 [0] = &exynos5_clk_mout_apll.clk,
400 [1] = &exynos5_clk_mout_mpll.clk,
403 static struct clksrc_sources exynos5_clkset_mout_cpu = {
404 .sources = exynos5_clkset_mout_cpu_list,
405 .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
408 static struct clksrc_clk exynos5_clk_mout_cpu = {
412 .sources = &exynos5_clkset_mout_cpu,
413 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
416 static struct clksrc_clk exynos5_clk_dout_armclk = {
418 .name = "dout_armclk",
419 .parent = &exynos5_clk_mout_cpu.clk,
421 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
424 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
426 .name = "dout_arm2clk",
427 .parent = &exynos5_clk_dout_armclk.clk,
429 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
432 static struct clk exynos5_clk_armclk = {
434 .parent = &exynos5_clk_dout_arm2clk.clk,
437 /* Core list of CMU_CDREX side */
439 static struct clk *exynos5_clkset_cdrex_list[] = {
440 [0] = &exynos5_clk_mout_mpll.clk,
441 [1] = &exynos5_clk_mout_bpll.clk,
444 static struct clksrc_sources exynos5_clkset_cdrex = {
445 .sources = exynos5_clkset_cdrex_list,
446 .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
449 static struct clksrc_clk exynos5_clk_cdrex = {
453 .sources = &exynos5_clkset_cdrex,
454 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
455 .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
458 static struct clksrc_clk exynos5_clk_aclk_acp = {
461 .parent = &exynos5_clk_mout_mpll.clk,
463 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
466 static struct clksrc_clk exynos5_clk_pclk_acp = {
469 .parent = &exynos5_clk_aclk_acp.clk,
471 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
474 /* Core list of CMU_TOP side */
476 static struct clk *exynos5_clkset_aclk_top_list[] = {
477 [0] = &exynos5_clk_mout_mpll_user.clk,
478 [1] = &exynos5_clk_mout_bpll_user.clk,
481 static struct clksrc_sources exynos5_clkset_aclk = {
482 .sources = exynos5_clkset_aclk_top_list,
483 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
486 static struct clksrc_clk exynos5_clk_aclk_400 = {
490 .sources = &exynos5_clkset_aclk,
491 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
492 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
495 static struct clk *exynos5_clkset_aclk_333_166_list[] = {
496 [0] = &exynos5_clk_mout_cpll.clk,
497 [1] = &exynos5_clk_mout_mpll_user.clk,
500 static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
501 .sources = exynos5_clkset_aclk_333_166_list,
502 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
505 static struct clksrc_clk exynos5_clk_aclk_333 = {
509 .sources = &exynos5_clkset_aclk_333_166,
510 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
511 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
514 static struct clksrc_clk exynos5_clk_aclk_166 = {
518 .sources = &exynos5_clkset_aclk_333_166,
519 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
520 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
523 static struct clksrc_clk exynos5_clk_aclk_266 = {
526 .parent = &exynos5_clk_mout_mpll_user.clk,
528 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
531 static struct clksrc_clk exynos5_clk_aclk_200 = {
535 .sources = &exynos5_clkset_aclk,
536 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
537 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
540 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
542 .name = "aclk_66_pre",
543 .parent = &exynos5_clk_mout_mpll_user.clk,
545 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
548 static struct clksrc_clk exynos5_clk_aclk_66 = {
551 .parent = &exynos5_clk_aclk_66_pre.clk,
553 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
556 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
558 .name = "mout_aclk_300_gscl_mid",
560 .sources = &exynos5_clkset_aclk,
561 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
564 static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
565 [0] = &exynos5_clk_sclk_vpll.clk,
566 [1] = &exynos5_clk_mout_cpll.clk,
569 static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
570 .sources = exynos5_clkset_aclk_300_mid1_list,
571 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
574 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
576 .name = "mout_aclk_300_gscl_mid1",
578 .sources = &exynos5_clkset_aclk_300_gscl_mid1,
579 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
582 static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
583 [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
584 [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
587 static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
588 .sources = exynos5_clkset_aclk_300_gscl_list,
589 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
592 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
594 .name = "mout_aclk_300_gscl",
596 .sources = &exynos5_clkset_aclk_300_gscl,
597 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
600 static struct clk *exynos5_clk_src_gscl_300_list[] = {
601 [0] = &clk_ext_xtal_mux,
602 [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
605 static struct clksrc_sources exynos5_clk_src_gscl_300 = {
606 .sources = exynos5_clk_src_gscl_300_list,
607 .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
610 static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
612 .name = "aclk_300_gscl",
614 .sources = &exynos5_clk_src_gscl_300,
615 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
618 static struct clk exynos5_init_clocks_off[] = {
621 .parent = &exynos5_clk_aclk_66.clk,
622 .enable = exynos5_clk_ip_peric_ctrl,
623 .ctrlbit = (1 << 24),
626 .parent = &exynos5_clk_aclk_66.clk,
627 .enable = exynos5_clk_ip_peris_ctrl,
628 .ctrlbit = (1 << 21),
631 .parent = &exynos5_clk_aclk_66.clk,
632 .enable = exynos5_clk_ip_peris_ctrl,
633 .ctrlbit = (1 << 20),
636 .parent = &exynos5_clk_aclk_66.clk,
637 .enable = exynos5_clk_ip_peris_ctrl,
638 .ctrlbit = (1 << 19),
640 .name = "biu", /* bus interface unit clock */
641 .devname = "dw_mmc.0",
642 .parent = &exynos5_clk_aclk_200.clk,
643 .enable = exynos5_clk_ip_fsys_ctrl,
644 .ctrlbit = (1 << 12),
647 .devname = "dw_mmc.1",
648 .parent = &exynos5_clk_aclk_200.clk,
649 .enable = exynos5_clk_ip_fsys_ctrl,
650 .ctrlbit = (1 << 13),
653 .devname = "dw_mmc.2",
654 .parent = &exynos5_clk_aclk_200.clk,
655 .enable = exynos5_clk_ip_fsys_ctrl,
656 .ctrlbit = (1 << 14),
659 .devname = "dw_mmc.3",
660 .parent = &exynos5_clk_aclk_200.clk,
661 .enable = exynos5_clk_ip_fsys_ctrl,
662 .ctrlbit = (1 << 15),
665 .devname = "exynos5-sata",
666 .parent = &exynos5_clk_aclk_200.clk,
667 .enable = exynos5_clk_ip_fsys_ctrl,
671 .devname = "exynos5-sata-phy",
672 .parent = &exynos5_clk_aclk_200.clk,
673 .enable = exynos5_clk_ip_fsys_ctrl,
674 .ctrlbit = (1 << 24),
677 .devname = "exynos5-sata-phy-i2c",
678 .parent = &exynos5_clk_aclk_200.clk,
679 .enable = exynos5_clk_ip_fsys_ctrl,
680 .ctrlbit = (1 << 25),
683 .devname = "s5p-mfc-v6",
684 .enable = exynos5_clk_ip_mfc_ctrl,
688 .devname = "exynos5-hdmi",
689 .enable = exynos5_clk_ip_disp1_ctrl,
693 .devname = "exynos5-hdmi",
694 .enable = exynos5_clk_hdmiphy_ctrl,
698 .devname = "exynos5-mixer",
699 .enable = exynos5_clk_ip_disp1_ctrl,
703 .devname = "exynos-dp",
704 .enable = exynos5_clk_ip_disp1_ctrl,
708 .enable = exynos5_clk_ip_gen_ctrl,
712 .enable = exynos5_clk_ip_disp1_ctrl,
716 .devname = "samsung-i2s.1",
717 .enable = exynos5_clk_ip_peric_ctrl,
718 .ctrlbit = (1 << 20),
721 .devname = "samsung-i2s.2",
722 .enable = exynos5_clk_ip_peric_ctrl,
723 .ctrlbit = (1 << 21),
726 .devname = "samsung-pcm.1",
727 .enable = exynos5_clk_ip_peric_ctrl,
728 .ctrlbit = (1 << 22),
731 .devname = "samsung-pcm.2",
732 .enable = exynos5_clk_ip_peric_ctrl,
733 .ctrlbit = (1 << 23),
736 .devname = "samsung-spdif",
737 .enable = exynos5_clk_ip_peric_ctrl,
738 .ctrlbit = (1 << 26),
741 .devname = "samsung-ac97",
742 .enable = exynos5_clk_ip_peric_ctrl,
743 .ctrlbit = (1 << 27),
746 .enable = exynos5_clk_ip_fsys_ctrl ,
747 .ctrlbit = (1 << 18),
750 .enable = exynos5_clk_ip_fsys_ctrl,
754 .enable = exynos5_clk_ip_fsys_ctrl,
755 .ctrlbit = (1 << 22),
758 .enable = exynos5_clk_ip_fsys_ctrl,
759 .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
762 .enable = exynos5_clk_ip_core_ctrl,
763 .ctrlbit = ((1 << 21) | (1 << 3)),
766 .enable = exynos5_clk_ip_fsys_ctrl,
770 .devname = "s3c2440-i2c.0",
771 .parent = &exynos5_clk_aclk_66.clk,
772 .enable = exynos5_clk_ip_peric_ctrl,
776 .devname = "s3c2440-i2c.1",
777 .parent = &exynos5_clk_aclk_66.clk,
778 .enable = exynos5_clk_ip_peric_ctrl,
782 .devname = "s3c2440-i2c.2",
783 .parent = &exynos5_clk_aclk_66.clk,
784 .enable = exynos5_clk_ip_peric_ctrl,
788 .devname = "s3c2440-i2c.3",
789 .parent = &exynos5_clk_aclk_66.clk,
790 .enable = exynos5_clk_ip_peric_ctrl,
794 .devname = "s3c2440-i2c.4",
795 .parent = &exynos5_clk_aclk_66.clk,
796 .enable = exynos5_clk_ip_peric_ctrl,
797 .ctrlbit = (1 << 10),
800 .devname = "s3c2440-i2c.5",
801 .parent = &exynos5_clk_aclk_66.clk,
802 .enable = exynos5_clk_ip_peric_ctrl,
803 .ctrlbit = (1 << 11),
806 .devname = "s3c2440-i2c.6",
807 .parent = &exynos5_clk_aclk_66.clk,
808 .enable = exynos5_clk_ip_peric_ctrl,
809 .ctrlbit = (1 << 12),
812 .devname = "s3c2440-i2c.7",
813 .parent = &exynos5_clk_aclk_66.clk,
814 .enable = exynos5_clk_ip_peric_ctrl,
815 .ctrlbit = (1 << 13),
818 .devname = "s3c2440-hdmiphy-i2c",
819 .parent = &exynos5_clk_aclk_66.clk,
820 .enable = exynos5_clk_ip_peric_ctrl,
821 .ctrlbit = (1 << 14),
824 .devname = "exynos4210-spi.0",
825 .parent = &exynos5_clk_aclk_66.clk,
826 .enable = exynos5_clk_ip_peric_ctrl,
827 .ctrlbit = (1 << 16),
830 .devname = "exynos4210-spi.1",
831 .parent = &exynos5_clk_aclk_66.clk,
832 .enable = exynos5_clk_ip_peric_ctrl,
833 .ctrlbit = (1 << 17),
836 .devname = "exynos4210-spi.2",
837 .parent = &exynos5_clk_aclk_66.clk,
838 .enable = exynos5_clk_ip_peric_ctrl,
839 .ctrlbit = (1 << 18),
842 .devname = "exynos-gsc.0",
843 .enable = exynos5_clk_ip_gscl_ctrl,
847 .devname = "exynos-gsc.1",
848 .enable = exynos5_clk_ip_gscl_ctrl,
852 .devname = "exynos-gsc.2",
853 .enable = exynos5_clk_ip_gscl_ctrl,
857 .devname = "exynos-gsc.3",
858 .enable = exynos5_clk_ip_gscl_ctrl,
862 .devname = "exynos-sysmmu.1",
863 .enable = &exynos5_clk_ip_mfc_ctrl,
867 .devname = "exynos-sysmmu.0",
868 .enable = &exynos5_clk_ip_mfc_ctrl,
872 .devname = "exynos-sysmmu.2",
873 .enable = &exynos5_clk_ip_disp1_ctrl,
877 .devname = "exynos-sysmmu.3",
878 .enable = &exynos5_clk_ip_gen_ctrl,
882 .devname = "exynos-sysmmu.4",
883 .enable = &exynos5_clk_ip_gen_ctrl,
887 .devname = "exynos-sysmmu.5",
888 .enable = &exynos5_clk_ip_gscl_ctrl,
892 .devname = "exynos-sysmmu.6",
893 .enable = &exynos5_clk_ip_gscl_ctrl,
897 .devname = "exynos-sysmmu.7",
898 .enable = &exynos5_clk_ip_gscl_ctrl,
902 .devname = "exynos-sysmmu.8",
903 .enable = &exynos5_clk_ip_gscl_ctrl,
904 .ctrlbit = (1 << 10),
907 .devname = "exynos-sysmmu.9",
908 .enable = &exynos5_clk_ip_isp0_ctrl,
909 .ctrlbit = (0x3F << 8),
912 .devname = "exynos-sysmmu.10",
913 .enable = &exynos5_clk_ip_isp1_ctrl,
914 .ctrlbit = (0xF << 4),
917 .devname = "exynos-sysmmu.11",
918 .enable = &exynos5_clk_ip_disp1_ctrl,
922 .devname = "exynos-sysmmu.12",
923 .enable = &exynos5_clk_ip_gscl_ctrl,
924 .ctrlbit = (1 << 11),
927 .devname = "exynos-sysmmu.13",
928 .enable = &exynos5_clk_ip_gscl_ctrl,
929 .ctrlbit = (1 << 12),
932 .devname = "exynos-sysmmu.14",
933 .enable = &exynos5_clk_ip_acp_ctrl,
938 static struct clk exynos5_init_clocks_on[] = {
941 .devname = "s5pv210-uart.0",
942 .enable = exynos5_clk_ip_peric_ctrl,
946 .devname = "s5pv210-uart.1",
947 .enable = exynos5_clk_ip_peric_ctrl,
951 .devname = "s5pv210-uart.2",
952 .enable = exynos5_clk_ip_peric_ctrl,
956 .devname = "s5pv210-uart.3",
957 .enable = exynos5_clk_ip_peric_ctrl,
961 .devname = "s5pv210-uart.4",
962 .enable = exynos5_clk_ip_peric_ctrl,
966 .devname = "s5pv210-uart.5",
967 .enable = exynos5_clk_ip_peric_ctrl,
972 static struct clk exynos5_clk_pdma0 = {
974 .devname = "dma-pl330.0",
975 .enable = exynos5_clk_ip_fsys_ctrl,
979 static struct clk exynos5_clk_pdma1 = {
981 .devname = "dma-pl330.1",
982 .enable = exynos5_clk_ip_fsys_ctrl,
986 static struct clk exynos5_clk_mdma1 = {
988 .devname = "dma-pl330.2",
989 .enable = exynos5_clk_ip_gen_ctrl,
993 static struct clk exynos5_clk_fimd1 = {
995 .devname = "exynos5-fb.1",
996 .enable = exynos5_clk_ip_disp1_ctrl,
1000 static struct clk *exynos5_clkset_group_list[] = {
1001 [0] = &clk_ext_xtal_mux,
1003 [2] = &exynos5_clk_sclk_hdmi24m,
1004 [3] = &exynos5_clk_sclk_dptxphy,
1005 [4] = &exynos5_clk_sclk_usbphy,
1006 [5] = &exynos5_clk_sclk_hdmiphy,
1007 [6] = &exynos5_clk_mout_mpll_user.clk,
1008 [7] = &exynos5_clk_mout_epll.clk,
1009 [8] = &exynos5_clk_sclk_vpll.clk,
1010 [9] = &exynos5_clk_mout_cpll.clk,
1013 static struct clksrc_sources exynos5_clkset_group = {
1014 .sources = exynos5_clkset_group_list,
1015 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
1018 /* Possible clock sources for aclk_266_gscl_sub Mux */
1019 static struct clk *clk_src_gscl_266_list[] = {
1020 [0] = &clk_ext_xtal_mux,
1021 [1] = &exynos5_clk_aclk_266.clk,
1024 static struct clksrc_sources clk_src_gscl_266 = {
1025 .sources = clk_src_gscl_266_list,
1026 .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
1029 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
1031 .name = "dout_mmc0",
1033 .sources = &exynos5_clkset_group,
1034 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
1035 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
1038 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
1040 .name = "dout_mmc1",
1042 .sources = &exynos5_clkset_group,
1043 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
1044 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1047 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
1049 .name = "dout_mmc2",
1051 .sources = &exynos5_clkset_group,
1052 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
1053 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1056 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
1058 .name = "dout_mmc3",
1060 .sources = &exynos5_clkset_group,
1061 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
1062 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1065 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
1067 .name = "dout_mmc4",
1069 .sources = &exynos5_clkset_group,
1070 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
1071 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1074 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
1077 .devname = "exynos4210-uart.0",
1078 .enable = exynos5_clksrc_mask_peric0_ctrl,
1079 .ctrlbit = (1 << 0),
1081 .sources = &exynos5_clkset_group,
1082 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
1083 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
1086 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
1089 .devname = "exynos4210-uart.1",
1090 .enable = exynos5_clksrc_mask_peric0_ctrl,
1091 .ctrlbit = (1 << 4),
1093 .sources = &exynos5_clkset_group,
1094 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
1095 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
1098 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
1101 .devname = "exynos4210-uart.2",
1102 .enable = exynos5_clksrc_mask_peric0_ctrl,
1103 .ctrlbit = (1 << 8),
1105 .sources = &exynos5_clkset_group,
1106 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
1107 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1110 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1113 .devname = "exynos4210-uart.3",
1114 .enable = exynos5_clksrc_mask_peric0_ctrl,
1115 .ctrlbit = (1 << 12),
1117 .sources = &exynos5_clkset_group,
1118 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1119 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1122 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1124 .name = "ciu", /* card interface unit clock */
1125 .devname = "dw_mmc.0",
1126 .parent = &exynos5_clk_dout_mmc0.clk,
1127 .enable = exynos5_clksrc_mask_fsys_ctrl,
1128 .ctrlbit = (1 << 0),
1130 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1133 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1136 .devname = "dw_mmc.1",
1137 .parent = &exynos5_clk_dout_mmc1.clk,
1138 .enable = exynos5_clksrc_mask_fsys_ctrl,
1139 .ctrlbit = (1 << 4),
1141 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1144 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1147 .devname = "dw_mmc.2",
1148 .parent = &exynos5_clk_dout_mmc2.clk,
1149 .enable = exynos5_clksrc_mask_fsys_ctrl,
1150 .ctrlbit = (1 << 8),
1152 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1155 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1158 .devname = "dw_mmc.3",
1159 .parent = &exynos5_clk_dout_mmc3.clk,
1160 .enable = exynos5_clksrc_mask_fsys_ctrl,
1161 .ctrlbit = (1 << 12),
1163 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1166 static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1168 .name = "mdout_spi",
1169 .devname = "exynos4210-spi.0",
1171 .sources = &exynos5_clkset_group,
1172 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1173 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1176 static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1178 .name = "mdout_spi",
1179 .devname = "exynos4210-spi.1",
1181 .sources = &exynos5_clkset_group,
1182 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1183 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1186 static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1188 .name = "mdout_spi",
1189 .devname = "exynos4210-spi.2",
1191 .sources = &exynos5_clkset_group,
1192 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1193 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1196 static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1199 .devname = "exynos4210-spi.0",
1200 .parent = &exynos5_clk_mdout_spi0.clk,
1201 .enable = exynos5_clksrc_mask_peric1_ctrl,
1202 .ctrlbit = (1 << 16),
1204 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1207 static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1210 .devname = "exynos4210-spi.1",
1211 .parent = &exynos5_clk_mdout_spi1.clk,
1212 .enable = exynos5_clksrc_mask_peric1_ctrl,
1213 .ctrlbit = (1 << 20),
1215 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1218 static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1221 .devname = "exynos4210-spi.2",
1222 .parent = &exynos5_clk_mdout_spi2.clk,
1223 .enable = exynos5_clksrc_mask_peric1_ctrl,
1224 .ctrlbit = (1 << 24),
1226 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1229 static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1231 .name = "sclk_fimd",
1232 .devname = "exynos5-fb.1",
1233 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
1234 .ctrlbit = (1 << 0),
1236 .sources = &exynos5_clkset_group,
1237 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1238 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1241 static struct clksrc_clk exynos5_clksrcs[] = {
1244 .name = "aclk_266_gscl",
1246 .sources = &clk_src_gscl_266,
1247 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1251 .devname = "mali-t604.0",
1252 .enable = exynos5_clk_block_ctrl,
1253 .ctrlbit = (1 << 1),
1255 .sources = &exynos5_clkset_aclk,
1256 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1257 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1260 .name = "sclk_sata",
1261 .devname = "exynos5-sata",
1262 .enable = exynos5_clksrc_mask_fsys_ctrl,
1263 .ctrlbit = (1 << 24),
1265 .sources = &exynos5_clkset_aclk,
1266 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
1267 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
1270 .name = "sclk_gscl_wrap",
1271 .devname = "s5p-mipi-csis.0",
1272 .enable = exynos5_clksrc_mask_gscl_ctrl,
1273 .ctrlbit = (1 << 24),
1275 .sources = &exynos5_clkset_group,
1276 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1277 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1280 .name = "sclk_gscl_wrap",
1281 .devname = "s5p-mipi-csis.1",
1282 .enable = exynos5_clksrc_mask_gscl_ctrl,
1283 .ctrlbit = (1 << 28),
1285 .sources = &exynos5_clkset_group,
1286 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1287 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1290 .name = "sclk_cam0",
1291 .enable = exynos5_clksrc_mask_gscl_ctrl,
1292 .ctrlbit = (1 << 16),
1294 .sources = &exynos5_clkset_group,
1295 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1296 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1299 .name = "sclk_cam1",
1300 .enable = exynos5_clksrc_mask_gscl_ctrl,
1301 .ctrlbit = (1 << 20),
1303 .sources = &exynos5_clkset_group,
1304 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1305 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1308 .name = "sclk_jpeg",
1309 .parent = &exynos5_clk_mout_cpll.clk,
1311 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1315 /* Clock initialization code */
1316 static struct clksrc_clk *exynos5_sysclks[] = {
1317 &exynos5_clk_mout_apll,
1318 &exynos5_clk_sclk_apll,
1319 &exynos5_clk_mout_bpll,
1320 &exynos5_clk_mout_bpll_fout,
1321 &exynos5_clk_mout_bpll_user,
1322 &exynos5_clk_mout_cpll,
1323 &exynos5_clk_mout_epll,
1324 &exynos5_clk_mout_mpll,
1325 &exynos5_clk_mout_mpll_fout,
1326 &exynos5_clk_mout_mpll_user,
1327 &exynos5_clk_vpllsrc,
1328 &exynos5_clk_sclk_vpll,
1329 &exynos5_clk_mout_cpu,
1330 &exynos5_clk_dout_armclk,
1331 &exynos5_clk_dout_arm2clk,
1333 &exynos5_clk_aclk_400,
1334 &exynos5_clk_aclk_333,
1335 &exynos5_clk_aclk_266,
1336 &exynos5_clk_aclk_200,
1337 &exynos5_clk_aclk_166,
1338 &exynos5_clk_aclk_300_gscl,
1339 &exynos5_clk_mout_aclk_300_gscl,
1340 &exynos5_clk_mout_aclk_300_gscl_mid,
1341 &exynos5_clk_mout_aclk_300_gscl_mid1,
1342 &exynos5_clk_aclk_66_pre,
1343 &exynos5_clk_aclk_66,
1344 &exynos5_clk_dout_mmc0,
1345 &exynos5_clk_dout_mmc1,
1346 &exynos5_clk_dout_mmc2,
1347 &exynos5_clk_dout_mmc3,
1348 &exynos5_clk_dout_mmc4,
1349 &exynos5_clk_aclk_acp,
1350 &exynos5_clk_pclk_acp,
1351 &exynos5_clk_sclk_spi0,
1352 &exynos5_clk_sclk_spi1,
1353 &exynos5_clk_sclk_spi2,
1354 &exynos5_clk_mdout_spi0,
1355 &exynos5_clk_mdout_spi1,
1356 &exynos5_clk_mdout_spi2,
1357 &exynos5_clk_sclk_fimd1,
1360 static struct clk *exynos5_clk_cdev[] = {
1367 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1368 &exynos5_clk_sclk_uart0,
1369 &exynos5_clk_sclk_uart1,
1370 &exynos5_clk_sclk_uart2,
1371 &exynos5_clk_sclk_uart3,
1372 &exynos5_clk_sclk_mmc0,
1373 &exynos5_clk_sclk_mmc1,
1374 &exynos5_clk_sclk_mmc2,
1375 &exynos5_clk_sclk_mmc3,
1378 static struct clk_lookup exynos5_clk_lookup[] = {
1379 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1380 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1381 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1382 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1383 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1384 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1385 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1386 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1387 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1388 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1389 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1390 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1391 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1392 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1393 CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
1396 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1401 static struct clk *exynos5_clks[] __initdata = {
1402 &exynos5_clk_sclk_hdmi27m,
1403 &exynos5_clk_sclk_hdmiphy,
1405 &clk_fout_bpll_div2,
1407 &clk_fout_mpll_div2,
1408 &exynos5_clk_armclk,
1411 static u32 epll_div[][6] = {
1412 { 192000000, 0, 48, 3, 1, 0 },
1413 { 180000000, 0, 45, 3, 1, 0 },
1414 { 73728000, 1, 73, 3, 3, 47710 },
1415 { 67737600, 1, 90, 4, 3, 20762 },
1416 { 49152000, 0, 49, 3, 3, 9961 },
1417 { 45158400, 0, 45, 3, 3, 10381 },
1418 { 180633600, 0, 45, 3, 1, 10381 },
1421 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1423 unsigned int epll_con, epll_con_k;
1426 unsigned int epll_rate;
1427 unsigned int locktime;
1428 unsigned int lockcnt;
1430 /* Return if nothing changed */
1431 if (clk->rate == rate)
1435 epll_rate = clk_get_rate(clk->parent);
1437 epll_rate = clk_ext_xtal_mux.rate;
1439 if (epll_rate != 24000000) {
1440 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1444 epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1445 epll_con &= ~(0x1 << 27 | \
1446 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1447 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1448 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1450 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1451 if (epll_div[i][0] == rate) {
1452 epll_con_k = epll_div[i][5] << 0;
1453 epll_con |= epll_div[i][1] << 27;
1454 epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1455 epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1456 epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1461 if (i == ARRAY_SIZE(epll_div)) {
1462 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1467 epll_rate /= 1000000;
1469 /* 3000 max_cycls : specification data */
1470 locktime = 3000 / epll_rate * epll_div[i][3];
1471 lockcnt = locktime * 10000 / (10000 / epll_rate);
1473 __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1475 __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1476 __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1479 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1480 } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1487 static struct clk_ops exynos5_epll_ops = {
1488 .get_rate = exynos5_epll_get_rate,
1489 .set_rate = exynos5_epll_set_rate,
1492 static int xtal_rate;
1494 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1496 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1499 static struct clk_ops exynos5_fout_apll_ops = {
1500 .get_rate = exynos5_fout_apll_get_rate,
1504 static int exynos5_clock_suspend(void)
1506 s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1511 static void exynos5_clock_resume(void)
1513 s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1516 #define exynos5_clock_suspend NULL
1517 #define exynos5_clock_resume NULL
1520 static struct syscore_ops exynos5_clock_syscore_ops = {
1521 .suspend = exynos5_clock_suspend,
1522 .resume = exynos5_clock_resume,
1525 void __init_or_cpufreq exynos5_setup_clocks(void)
1527 struct clk *xtal_clk;
1534 unsigned long vpllsrc;
1536 unsigned long armclk;
1537 unsigned long mout_cdrex;
1538 unsigned long aclk_400;
1539 unsigned long aclk_333;
1540 unsigned long aclk_266;
1541 unsigned long aclk_200;
1542 unsigned long aclk_166;
1543 unsigned long aclk_66;
1546 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1548 xtal_clk = clk_get(NULL, "xtal");
1549 BUG_ON(IS_ERR(xtal_clk));
1551 xtal = clk_get_rate(xtal_clk);
1557 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1559 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1560 bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1561 cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1562 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1563 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1564 __raw_readl(EXYNOS5_EPLL_CON1));
1566 vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1567 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1568 __raw_readl(EXYNOS5_VPLL_CON1));
1570 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1571 clk_fout_bpll.rate = bpll;
1572 clk_fout_bpll_div2.rate = bpll >> 1;
1573 clk_fout_cpll.rate = cpll;
1574 clk_fout_mpll.rate = mpll;
1575 clk_fout_mpll_div2.rate = mpll >> 1;
1576 clk_fout_epll.rate = epll;
1577 clk_fout_vpll.rate = vpll;
1579 printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1580 "M=%ld, E=%ld V=%ld",
1581 apll, bpll, cpll, mpll, epll, vpll);
1583 armclk = clk_get_rate(&exynos5_clk_armclk);
1584 mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1586 aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1587 aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1588 aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1589 aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1590 aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1591 aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1593 printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1594 "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1595 "ACLK166=%ld, ACLK66=%ld\n",
1596 armclk, mout_cdrex, aclk_400,
1597 aclk_333, aclk_266, aclk_200,
1601 clk_fout_epll.ops = &exynos5_epll_ops;
1603 if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1604 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1605 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1607 clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1608 clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1610 clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1611 clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1613 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1614 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1617 void __init exynos5_register_clocks(void)
1621 s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1623 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1624 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1626 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1627 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1629 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1630 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1632 s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1633 s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1635 s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1636 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1637 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1639 s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1640 s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1641 clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1643 register_syscore_ops(&exynos5_clock_syscore_ops);