2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS4212 - Clock support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/clk.h>
16 #include <linux/syscore_ops.h>
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
26 #include <mach/hardware.h>
28 #include <mach/regs-clock.h>
31 #include "clock-exynos4.h"
33 #ifdef CONFIG_PM_SLEEP
34 static struct sleep_save exynos4212_clock_save[] = {
35 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
36 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
37 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
38 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
42 static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
44 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
47 static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
49 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
52 static struct clk *clk_src_mpll_user_list[] = {
54 [1] = &exynos4_clk_mout_mpll.clk,
57 static struct clksrc_sources clk_src_mpll_user = {
58 .sources = clk_src_mpll_user_list,
59 .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
62 static struct clksrc_clk clk_mout_mpll_user = {
64 .name = "mout_mpll_user",
66 .sources = &clk_src_mpll_user,
67 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
70 static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
74 .sources = &exynos4_clkset_mout_g2d0,
75 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
78 static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
82 .sources = &exynos4_clkset_mout_g2d1,
83 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
86 static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
87 [0] = &exynos4x12_clk_mout_g2d0.clk,
88 [1] = &exynos4x12_clk_mout_g2d1.clk,
91 static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
92 .sources = exynos4x12_clkset_mout_g2d_list,
93 .nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
96 static struct clksrc_clk *sysclks[] = {
100 static struct clksrc_clk clksrcs[] = {
103 .name = "sclk_fimg2d",
105 .sources = &exynos4x12_clkset_mout_g2d,
106 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
107 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
111 static struct clk init_clocks_off[] = {
114 .devname = "exynos-sysmmu.9",
115 .enable = exynos4_clk_ip_dmc_ctrl,
116 .ctrlbit = (1 << 24),
119 .devname = "exynos-sysmmu.12",
120 .enable = exynos4212_clk_ip_isp0_ctrl,
124 .devname = "exynos-sysmmu.13",
125 .enable = exynos4212_clk_ip_isp1_ctrl,
129 .devname = "exynos-sysmmu.14",
130 .enable = exynos4212_clk_ip_isp0_ctrl,
131 .ctrlbit = (1 << 11),
134 .devname = "exynos-sysmmu.15",
135 .enable = exynos4212_clk_ip_isp0_ctrl,
136 .ctrlbit = (1 << 12),
139 .devname = "exynos-fimc-lite.0",
140 .enable = exynos4212_clk_ip_isp0_ctrl,
144 .devname = "exynos-fimc-lite.1",
145 .enable = exynos4212_clk_ip_isp0_ctrl,
149 .enable = exynos4_clk_ip_dmc_ctrl,
150 .ctrlbit = (1 << 23),
154 #ifdef CONFIG_PM_SLEEP
155 static int exynos4212_clock_suspend(void)
157 s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
162 static void exynos4212_clock_resume(void)
164 s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
168 #define exynos4212_clock_suspend NULL
169 #define exynos4212_clock_resume NULL
172 static struct syscore_ops exynos4212_clock_syscore_ops = {
173 .suspend = exynos4212_clock_suspend,
174 .resume = exynos4212_clock_resume,
177 void __init exynos4212_register_clocks(void)
181 /* usbphy1 is removed */
182 exynos4_clkset_group_list[4] = NULL;
184 /* mout_mpll_user is used */
185 exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
186 exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
188 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
189 exynos4_clk_mout_mpll.reg_src.shift = 12;
190 exynos4_clk_mout_mpll.reg_src.size = 1;
192 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
193 s3c_register_clksrc(sysclks[ptr], 1);
195 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
197 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
198 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
200 register_syscore_ops(&exynos4212_clock_syscore_ops);