Pileus Git - ~andy/linux/blob - arch/arm/mach-exynos/clock-exynos4210.c

   1 /*
   2  * linux/arch/arm/mach-exynos4/clock-exynos4210.c
   3  *
   4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * EXYNOS4210 - Clock support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/syscore_ops.h>
  19
  20 #include <plat/cpu-freq.h>
  21 #include <plat/clock.h>
  22 #include <plat/cpu.h>
  23 #include <plat/pll.h>
  24 #include <plat/s5p-clock.h>
  25 #include <plat/clock-clksrc.h>
  26 #include <plat/pm.h>
  27
  28 #include <mach/hardware.h>
  29 #include <mach/map.h>
  30 #include <mach/regs-clock.h>
  31 #include <mach/exynos4-clock.h>
  32
  33 #include "common.h"
  34
  35 static struct sleep_save exynos4210_clock_save[] = {
  36         SAVE_ITEM(S5P_CLKSRC_IMAGE),
  37         SAVE_ITEM(S5P_CLKSRC_LCD1),
  38         SAVE_ITEM(S5P_CLKDIV_IMAGE),
  39         SAVE_ITEM(S5P_CLKDIV_LCD1),
  40         SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
  41         SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
  42         SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
  43         SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
  44 };
  45
  46 static struct clksrc_clk *sysclks[] = {
  47         /* nothing here yet */
  48 };
  49
  50 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
  51 {
  52         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
  53 }
  54
  55 static struct clksrc_clk clksrcs[] = {
  56         {
  57                 .clk            = {
  58                         .name           = "sclk_sata",
  59                         .id             = -1,
  60                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
  61                         .ctrlbit        = (1 << 24),
  62                 },
  63                 .sources = &clkset_mout_corebus,
  64                 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
  65                 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
  66         }, {
  67                 .clk            = {
  68                         .name           = "sclk_fimd",
  69                         .devname        = "exynos4-fb.1",
  70                         .enable         = exynos4_clksrc_mask_lcd1_ctrl,
  71                         .ctrlbit        = (1 << 0),
  72                 },
  73                 .sources = &clkset_group,
  74                 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
  75                 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
  76         },
  77 };
  78
  79 static struct clk init_clocks_off[] = {
  80         {
  81                 .name           = "sataphy",
  82                 .id             = -1,
  83                 .parent         = &clk_aclk_133.clk,
  84                 .enable         = exynos4_clk_ip_fsys_ctrl,
  85                 .ctrlbit        = (1 << 3),
  86         }, {
  87                 .name           = "sata",
  88                 .id             = -1,
  89                 .parent         = &clk_aclk_133.clk,
  90                 .enable         = exynos4_clk_ip_fsys_ctrl,
  91                 .ctrlbit        = (1 << 10),
  92         }, {
  93                 .name           = "fimd",
  94                 .devname        = "exynos4-fb.1",
  95                 .enable         = exynos4_clk_ip_lcd1_ctrl,
  96                 .ctrlbit        = (1 << 0),
  97         },
  98 };
  99
 100 #ifdef CONFIG_PM_SLEEP
 101 static int exynos4210_clock_suspend(void)
 102 {
 103         s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
 104
 105         return 0;
 106 }
 107
 108 static void exynos4210_clock_resume(void)
 109 {
 110         s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
 111 }
 112
 113 #else
 114 #define exynos4210_clock_suspend NULL
 115 #define exynos4210_clock_resume NULL
 116 #endif
 117
 118 struct syscore_ops exynos4210_clock_syscore_ops = {
 119         .suspend        = exynos4210_clock_suspend,
 120         .resume         = exynos4210_clock_resume,
 121 };
 122
 123 void __init exynos4210_register_clocks(void)
 124 {
 125         int ptr;
 126
 127         clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
 128         clk_mout_mpll.reg_src.shift = 8;
 129         clk_mout_mpll.reg_src.size = 1;
 130
 131         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 132                 s3c_register_clksrc(sysclks[ptr], 1);
 133
 134         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 135
 136         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 137         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 138
 139         register_syscore_ops(&exynos4210_clock_syscore_ops);
 140 }