2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
7 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
8 * role in the ep93xx linux community.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/sched.h>
20 #include <linux/interrupt.h>
21 #include <linux/serial.h>
22 #include <linux/tty.h>
23 #include <linux/bitops.h>
24 #include <linux/serial.h>
25 #include <linux/serial_8250.h>
26 #include <linux/serial_core.h>
27 #include <linux/device.h>
29 #include <linux/time.h>
30 #include <linux/timex.h>
31 #include <linux/delay.h>
32 #include <linux/termios.h>
33 #include <linux/amba/bus.h>
34 #include <linux/amba/serial.h>
36 #include <asm/types.h>
37 #include <asm/setup.h>
38 #include <asm/memory.h>
39 #include <asm/hardware.h>
41 #include <asm/system.h>
42 #include <asm/tlbflush.h>
43 #include <asm/pgtable.h>
46 #include <asm/mach/map.h>
47 #include <asm/mach/time.h>
48 #include <asm/mach/irq.h>
49 #include <asm/arch/gpio.h>
51 #include <asm/hardware/vic.h>
54 /*************************************************************************
55 * Static I/O mappings that are needed for all EP93xx platforms
56 *************************************************************************/
57 static struct map_desc ep93xx_io_desc[] __initdata = {
59 .virtual = EP93XX_AHB_VIRT_BASE,
60 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
61 .length = EP93XX_AHB_SIZE,
64 .virtual = EP93XX_APB_VIRT_BASE,
65 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
66 .length = EP93XX_APB_SIZE,
71 void __init ep93xx_map_io(void)
73 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
77 /*************************************************************************
78 * Timer handling for EP93xx
79 *************************************************************************
80 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
81 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
82 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
83 * is free-running, and can't generate interrupts.
85 * The 508 kHz timers are ideal for use for the timer interrupt, as the
86 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
87 * bit timers (timer 1) since we don't need more than 16 bits of reload
88 * value as long as HZ >= 8.
90 * The higher clock rate of timer 4 makes it a better choice than the
91 * other timers for use in gettimeoffset(), while the fact that it can't
92 * generate interrupts means we don't have to worry about not being able
93 * to use this timer for something else. We also use timer 4 for keeping
94 * track of lost jiffies.
96 static unsigned int last_jiffy_time;
98 #define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
100 static int ep93xx_timer_interrupt(int irq, void *dev_id)
102 write_seqlock(&xtime_lock);
104 __raw_writel(1, EP93XX_TIMER1_CLEAR);
106 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
107 >= TIMER4_TICKS_PER_JIFFY) {
108 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
112 write_sequnlock(&xtime_lock);
117 static struct irqaction ep93xx_timer_irq = {
118 .name = "ep93xx timer",
119 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
120 .handler = ep93xx_timer_interrupt,
123 static void __init ep93xx_timer_init(void)
125 /* Enable periodic HZ timer. */
126 __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
127 __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
128 __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
130 /* Enable lost jiffy timer. */
131 __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
133 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
136 static unsigned long ep93xx_gettimeoffset(void)
140 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
142 /* Calculate (1000000 / 983040) * offset. */
143 return offset + (53 * offset / 3072);
146 struct sys_timer ep93xx_timer = {
147 .init = ep93xx_timer_init,
148 .offset = ep93xx_gettimeoffset,
152 /*************************************************************************
153 * GPIO handling for EP93xx
154 *************************************************************************/
155 static unsigned char gpio_int_unmasked[3];
156 static unsigned char gpio_int_enabled[3];
157 static unsigned char gpio_int_type1[3];
158 static unsigned char gpio_int_type2[3];
160 /* Port ordering is: A B F */
161 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
162 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
163 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
164 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c };
166 static void update_gpio_int_params(unsigned port)
170 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
172 __raw_writeb(gpio_int_type2[port],
173 EP93XX_GPIO_REG(int_type2_register_offset[port]));
175 __raw_writeb(gpio_int_type1[port],
176 EP93XX_GPIO_REG(int_type1_register_offset[port]));
178 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
179 EP93XX_GPIO_REG(int_en_register_offset[port]));
182 /* Port ordering is: A B F D E C G H */
183 static const u8 data_register_offset[8] = {
184 0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40,
187 static const u8 data_direction_register_offset[8] = {
188 0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44,
191 static void ep93xx_gpio_set_direction(unsigned line, int direction)
193 unsigned int data_direction_register;
197 data_direction_register =
198 EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
200 local_irq_save(flags);
201 if (direction == GPIO_OUT) {
202 if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) {
204 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
205 update_gpio_int_params(line >> 3);
208 v = __raw_readb(data_direction_register);
209 v |= 1 << (line & 7);
210 __raw_writeb(v, data_direction_register);
211 } else if (direction == GPIO_IN) {
212 v = __raw_readb(data_direction_register);
213 v &= ~(1 << (line & 7));
214 __raw_writeb(v, data_direction_register);
216 local_irq_restore(flags);
219 void __deprecated gpio_line_config(int line, int direction)
221 ep93xx_gpio_set_direction(line, direction);
223 EXPORT_SYMBOL(gpio_line_config);
225 int gpio_direction_input(unsigned gpio)
227 if (gpio > EP93XX_GPIO_LINE_MAX)
230 ep93xx_gpio_set_direction(gpio, GPIO_IN);
234 EXPORT_SYMBOL(gpio_direction_input);
236 int gpio_direction_output(unsigned gpio, int value)
238 if (gpio > EP93XX_GPIO_LINE_MAX)
241 gpio_set_value(gpio, value);
242 ep93xx_gpio_set_direction(gpio, GPIO_OUT);
246 EXPORT_SYMBOL(gpio_direction_output);
248 int gpio_get_value(unsigned gpio)
250 unsigned int data_register;
252 data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
254 return !!(__raw_readb(data_register) & (1 << (gpio & 7)));
256 EXPORT_SYMBOL(gpio_get_value);
258 void gpio_set_value(unsigned gpio, int value)
260 unsigned int data_register;
264 data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
266 local_irq_save(flags);
267 v = __raw_readb(data_register);
269 v |= 1 << (gpio & 7);
271 v &= ~(1 << (gpio & 7));
272 __raw_writeb(v, data_register);
273 local_irq_restore(flags);
275 EXPORT_SYMBOL(gpio_set_value);
278 /*************************************************************************
279 * EP93xx IRQ handling
280 *************************************************************************/
281 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
283 unsigned char status;
286 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
287 for (i = 0; i < 8; i++) {
288 if (status & (1 << i)) {
289 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
290 desc = irq_desc + gpio_irq;
291 desc_handle_irq(gpio_irq, desc);
295 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
296 for (i = 0; i < 8; i++) {
297 if (status & (1 << i)) {
298 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
299 desc = irq_desc + gpio_irq;
300 desc_handle_irq(gpio_irq, desc);
305 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
308 * map discontiguous hw irq range to continous sw irq range:
310 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
312 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
313 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
315 desc_handle_irq(gpio_irq, irq_desc + gpio_irq);
318 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
320 int line = irq_to_gpio(irq);
321 int port = line >> 3;
322 int port_mask = 1 << (line & 7);
324 gpio_int_unmasked[port] &= ~port_mask;
325 update_gpio_int_params(port);
327 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
330 static void ep93xx_gpio_irq_mask(unsigned int irq)
332 int line = irq_to_gpio(irq);
333 int port = line >> 3;
335 gpio_int_unmasked[port] &= ~(1 << (line & 7));
336 update_gpio_int_params(port);
339 static void ep93xx_gpio_irq_unmask(unsigned int irq)
341 int line = irq_to_gpio(irq);
342 int port = line >> 3;
344 gpio_int_unmasked[port] |= 1 << (line & 7);
345 update_gpio_int_params(port);
350 * gpio_int_type1 controls whether the interrupt is level (0) or
351 * edge (1) triggered, while gpio_int_type2 controls whether it
352 * triggers on low/falling (0) or high/rising (1).
354 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
356 const int gpio = irq_to_gpio(irq);
357 const int port = gpio >> 3;
358 const int port_mask = 1 << (gpio & 7);
360 ep93xx_gpio_set_direction(gpio, GPIO_IN);
362 if (type & IRQT_RISING) {
363 gpio_int_enabled[port] |= port_mask;
364 gpio_int_type1[port] |= port_mask;
365 gpio_int_type2[port] |= port_mask;
366 } else if (type & IRQT_FALLING) {
367 gpio_int_enabled[port] |= port_mask;
368 gpio_int_type1[port] |= port_mask;
369 gpio_int_type2[port] &= ~port_mask;
370 } else if (type & IRQT_HIGH) {
371 gpio_int_enabled[port] |= port_mask;
372 gpio_int_type1[port] &= ~port_mask;
373 gpio_int_type2[port] |= port_mask;
374 } else if (type & IRQT_LOW) {
375 gpio_int_enabled[port] |= port_mask;
376 gpio_int_type1[port] &= ~port_mask;
377 gpio_int_type2[port] &= ~port_mask;
379 gpio_int_enabled[port] &= ~port_mask;
381 update_gpio_int_params(port);
386 static struct irq_chip ep93xx_gpio_irq_chip = {
388 .ack = ep93xx_gpio_irq_mask_ack,
389 .mask = ep93xx_gpio_irq_mask,
390 .unmask = ep93xx_gpio_irq_unmask,
391 .set_type = ep93xx_gpio_irq_type,
395 void __init ep93xx_init_irq(void)
399 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
400 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
402 for (gpio_irq = gpio_to_irq(0);
403 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
404 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
405 set_irq_handler(gpio_irq, handle_level_irq);
406 set_irq_flags(gpio_irq, IRQF_VALID);
409 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
410 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
411 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
412 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
413 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
414 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
415 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
416 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
417 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
421 /*************************************************************************
422 * EP93xx peripheral handling
423 *************************************************************************/
424 #define EP93XX_UART_MCR_OFFSET (0x0100)
426 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
427 void __iomem *base, unsigned int mctrl)
432 if (!(mctrl & TIOCM_RTS))
434 if (!(mctrl & TIOCM_DTR))
437 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
440 static struct amba_pl010_data ep93xx_uart_data = {
441 .set_mctrl = ep93xx_uart_set_mctrl,
444 static struct amba_device uart1_device = {
446 .bus_id = "apb:uart1",
447 .platform_data = &ep93xx_uart_data,
450 .start = EP93XX_UART1_PHYS_BASE,
451 .end = EP93XX_UART1_PHYS_BASE + 0x0fff,
452 .flags = IORESOURCE_MEM,
454 .irq = { IRQ_EP93XX_UART1, NO_IRQ },
455 .periphid = 0x00041010,
458 static struct amba_device uart2_device = {
460 .bus_id = "apb:uart2",
461 .platform_data = &ep93xx_uart_data,
464 .start = EP93XX_UART2_PHYS_BASE,
465 .end = EP93XX_UART2_PHYS_BASE + 0x0fff,
466 .flags = IORESOURCE_MEM,
468 .irq = { IRQ_EP93XX_UART2, NO_IRQ },
469 .periphid = 0x00041010,
472 static struct amba_device uart3_device = {
474 .bus_id = "apb:uart3",
475 .platform_data = &ep93xx_uart_data,
478 .start = EP93XX_UART3_PHYS_BASE,
479 .end = EP93XX_UART3_PHYS_BASE + 0x0fff,
480 .flags = IORESOURCE_MEM,
482 .irq = { IRQ_EP93XX_UART3, NO_IRQ },
483 .periphid = 0x00041010,
487 static struct platform_device ep93xx_rtc_device = {
488 .name = "ep93xx-rtc",
494 static struct resource ep93xx_ohci_resources[] = {
496 .start = EP93XX_USB_PHYS_BASE,
497 .end = EP93XX_USB_PHYS_BASE + 0x0fff,
498 .flags = IORESOURCE_MEM,
501 .start = IRQ_EP93XX_USB,
502 .end = IRQ_EP93XX_USB,
503 .flags = IORESOURCE_IRQ,
507 static struct platform_device ep93xx_ohci_device = {
508 .name = "ep93xx-ohci",
511 .dma_mask = (void *)0xffffffff,
512 .coherent_dma_mask = 0xffffffff,
514 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
515 .resource = ep93xx_ohci_resources,
519 void __init ep93xx_init_devices(void)
524 * Disallow access to MaverickCrunch initially.
526 v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
527 v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
528 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
529 __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
531 amba_device_register(&uart1_device, &iomem_resource);
532 amba_device_register(&uart2_device, &iomem_resource);
533 amba_device_register(&uart3_device, &iomem_resource);
535 platform_device_register(&ep93xx_rtc_device);
536 platform_device_register(&ep93xx_ohci_device);