2 * linux/arch/arm/mach-at91/clock.c
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/debugfs.h>
18 #include <linux/seq_file.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/spinlock.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
26 #include <linux/of_address.h>
28 #include <mach/hardware.h>
29 #include <mach/at91_pmc.h>
32 #include <asm/proc-fns.h>
37 void __iomem *at91_pmc_base;
40 * There's a lot more which can be done with clocks, including cpufreq
41 * integration, slow clock mode support (for system suspend), letting
42 * PLLB be used at other rates (on boards that don't need USB), etc.
45 #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
46 #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
47 #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
48 #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
52 * Chips have some kind of clocks : group them by functionality
54 #define cpu_has_utmi() ( cpu_is_at91sam9rl() \
55 || cpu_is_at91sam9g45() \
56 || cpu_is_at91sam9x5())
58 #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
59 || cpu_is_at91sam9g45() \
60 || cpu_is_at91sam9x5())
62 #define cpu_has_300M_plla() (cpu_is_at91sam9g10())
64 #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
65 || cpu_is_at91sam9g45() \
66 || cpu_is_at91sam9x5()))
68 #define cpu_has_upll() (cpu_is_at91sam9g45() \
69 || cpu_is_at91sam9x5())
71 /* USB host HS & FS */
72 #define cpu_has_uhp() (!cpu_is_at91sam9rl())
74 /* USB device FS only */
75 #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
76 || cpu_is_at91sam9g45() \
77 || cpu_is_at91sam9x5()))
79 #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
80 || cpu_is_at91sam9x5())
82 #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
83 || cpu_is_at91sam9x5())
85 #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
87 static LIST_HEAD(clocks);
88 static DEFINE_SPINLOCK(clk_lock);
90 static u32 at91_pllb_usb_init;
93 * Four primary clock sources: two crystal oscillators (32K, main), and
94 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
95 * 48 MHz (unless no USB function clocks are needed). The main clock and
96 * both PLLs are turned off to run in "slow clock mode" (system suspend).
98 static struct clk clk32k = {
100 .rate_hz = AT91_SLOW_CLOCK,
101 .users = 1, /* always on */
103 .type = CLK_TYPE_PRIMARY,
105 static struct clk main_clk = {
107 .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
109 .type = CLK_TYPE_PRIMARY,
111 static struct clk plla = {
114 .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
116 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
119 static void pllb_mode(struct clk *clk, int is_on)
124 is_on = AT91_PMC_LOCKB;
125 value = at91_pllb_usb_init;
129 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
130 at91_pmc_write(AT91_CKGR_PLLBR, value);
134 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
137 static struct clk pllb = {
140 .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
143 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
146 static void pmc_sys_mode(struct clk *clk, int is_on)
149 at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
151 at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
154 static void pmc_uckr_mode(struct clk *clk, int is_on)
156 unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
159 is_on = AT91_PMC_LOCKU;
160 at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
162 at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
166 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
169 /* USB function clocks (PLLB must be 48 MHz) */
170 static struct clk udpck = {
173 .mode = pmc_sys_mode,
175 struct clk utmi_clk = {
178 .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
179 .mode = pmc_uckr_mode,
180 .type = CLK_TYPE_PLL,
182 static struct clk uhpck = {
184 /*.parent = ... we choose parent at runtime */
185 .mode = pmc_sys_mode,
190 * The master clock is divided from the CPU clock (by 1-4). It's used for
191 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
192 * (e.g baud rate generation). It's sourced from one of the primary clocks.
196 .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
199 static void pmc_periph_mode(struct clk *clk, int is_on)
202 at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
204 at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
207 static struct clk __init *at91_css_to_clk(unsigned long css)
210 case AT91_PMC_CSS_SLOW:
212 case AT91_PMC_CSS_MAIN:
214 case AT91_PMC_CSS_PLLA:
216 case AT91_PMC_CSS_PLLB:
218 /* CSS_PLLB == CSS_UPLL */
220 else if (cpu_has_pllb())
223 /* alternate PMC: can use master clock */
224 case AT91_PMC_CSS_MASTER:
231 static int pmc_prescaler_divider(u32 reg)
233 if (cpu_has_alt_prescaler()) {
234 return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
236 return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
240 static void __clk_enable(struct clk *clk)
243 __clk_enable(clk->parent);
244 if (clk->users++ == 0 && clk->mode)
248 int clk_enable(struct clk *clk)
252 spin_lock_irqsave(&clk_lock, flags);
254 spin_unlock_irqrestore(&clk_lock, flags);
257 EXPORT_SYMBOL(clk_enable);
259 static void __clk_disable(struct clk *clk)
261 BUG_ON(clk->users == 0);
262 if (--clk->users == 0 && clk->mode)
265 __clk_disable(clk->parent);
268 void clk_disable(struct clk *clk)
272 spin_lock_irqsave(&clk_lock, flags);
274 spin_unlock_irqrestore(&clk_lock, flags);
276 EXPORT_SYMBOL(clk_disable);
278 unsigned long clk_get_rate(struct clk *clk)
283 spin_lock_irqsave(&clk_lock, flags);
286 if (rate || !clk->parent)
290 spin_unlock_irqrestore(&clk_lock, flags);
293 EXPORT_SYMBOL(clk_get_rate);
295 /*------------------------------------------------------------------------*/
297 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
300 * For now, only the programmable clocks support reparenting (MCK could
301 * do this too, with care) or rate changing (the PLLs could do this too,
302 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
303 * a better rate match; we don't.
306 long clk_round_rate(struct clk *clk, unsigned long rate)
310 unsigned long actual;
311 unsigned long prev = ULONG_MAX;
313 if (!clk_is_programmable(clk))
315 spin_lock_irqsave(&clk_lock, flags);
317 actual = clk->parent->rate_hz;
318 for (prescale = 0; prescale < 7; prescale++) {
322 if (actual && actual <= rate) {
323 if ((prev - rate) < (rate - actual)) {
332 spin_unlock_irqrestore(&clk_lock, flags);
333 return (prescale < 7) ? actual : -ENOENT;
335 EXPORT_SYMBOL(clk_round_rate);
337 int clk_set_rate(struct clk *clk, unsigned long rate)
341 unsigned long prescale_offset, css_mask;
342 unsigned long actual;
344 if (!clk_is_programmable(clk))
349 if (cpu_has_alt_prescaler()) {
350 prescale_offset = PMC_ALT_PRES_OFFSET;
351 css_mask = AT91_PMC_ALT_PCKR_CSS;
353 prescale_offset = PMC_PRES_OFFSET;
354 css_mask = AT91_PMC_CSS;
357 spin_lock_irqsave(&clk_lock, flags);
359 actual = clk->parent->rate_hz;
360 for (prescale = 0; prescale < 7; prescale++) {
361 if (actual && actual <= rate) {
364 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
365 pckr &= css_mask; /* keep clock selection */
366 pckr |= prescale << prescale_offset;
367 at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
368 clk->rate_hz = actual;
374 spin_unlock_irqrestore(&clk_lock, flags);
375 return (prescale < 7) ? actual : -ENOENT;
377 EXPORT_SYMBOL(clk_set_rate);
379 struct clk *clk_get_parent(struct clk *clk)
383 EXPORT_SYMBOL(clk_get_parent);
385 int clk_set_parent(struct clk *clk, struct clk *parent)
391 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
394 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
397 spin_lock_irqsave(&clk_lock, flags);
399 clk->rate_hz = parent->rate_hz;
400 clk->parent = parent;
401 at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
403 spin_unlock_irqrestore(&clk_lock, flags);
406 EXPORT_SYMBOL(clk_set_parent);
408 /* establish PCK0..PCKN parentage and rate */
409 static void __init init_programmable_clock(struct clk *clk)
413 unsigned int css_mask;
415 if (cpu_has_alt_prescaler())
416 css_mask = AT91_PMC_ALT_PCKR_CSS;
418 css_mask = AT91_PMC_CSS;
420 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
421 parent = at91_css_to_clk(pckr & css_mask);
422 clk->parent = parent;
423 clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
426 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
428 /*------------------------------------------------------------------------*/
430 #ifdef CONFIG_DEBUG_FS
432 static int at91_clk_show(struct seq_file *s, void *unused)
434 u32 scsr, pcsr, uckr = 0, sr;
437 scsr = at91_pmc_read(AT91_PMC_SCSR);
438 pcsr = at91_pmc_read(AT91_PMC_PCSR);
439 sr = at91_pmc_read(AT91_PMC_SR);
440 seq_printf(s, "SCSR = %8x\n", scsr);
441 seq_printf(s, "PCSR = %8x\n", pcsr);
442 seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
443 seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
444 seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
446 seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
447 if (cpu_has_utmi()) {
448 uckr = at91_pmc_read(AT91_CKGR_UCKR);
449 seq_printf(s, "UCKR = %8x\n", uckr);
451 seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
453 seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
454 seq_printf(s, "SR = %8x\n", sr);
458 list_for_each_entry(clk, &clocks, node) {
461 if (clk->mode == pmc_sys_mode)
462 state = (scsr & clk->pmc_mask) ? "on" : "off";
463 else if (clk->mode == pmc_periph_mode)
464 state = (pcsr & clk->pmc_mask) ? "on" : "off";
465 else if (clk->mode == pmc_uckr_mode)
466 state = (uckr & clk->pmc_mask) ? "on" : "off";
467 else if (clk->pmc_mask)
468 state = (sr & clk->pmc_mask) ? "on" : "off";
469 else if (clk == &clk32k || clk == &main_clk)
474 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
475 clk->name, clk->users, state, clk_get_rate(clk),
476 clk->parent ? clk->parent->name : "");
481 static int at91_clk_open(struct inode *inode, struct file *file)
483 return single_open(file, at91_clk_show, NULL);
486 static const struct file_operations at91_clk_operations = {
487 .open = at91_clk_open,
490 .release = single_release,
493 static int __init at91_clk_debugfs_init(void)
495 /* /sys/kernel/debug/at91_clk */
496 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
500 postcore_initcall(at91_clk_debugfs_init);
504 /*------------------------------------------------------------------------*/
506 /* Register a new clock */
507 static void __init at91_clk_add(struct clk *clk)
509 list_add_tail(&clk->node, &clocks);
511 clk->cl.con_id = clk->name;
513 clkdev_add(&clk->cl);
516 int __init clk_register(struct clk *clk)
518 if (clk_is_peripheral(clk)) {
521 clk->mode = pmc_periph_mode;
523 else if (clk_is_sys(clk)) {
525 clk->mode = pmc_sys_mode;
527 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
528 else if (clk_is_programmable(clk)) {
529 clk->mode = pmc_sys_mode;
530 init_programmable_clock(clk);
539 /*------------------------------------------------------------------------*/
541 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
546 mul = (reg >> 16) & 0x7ff;
556 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
558 if (pll == &pllb && (reg & AT91_PMC_USB96M))
564 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
566 unsigned i, div = 0, mul = 0, diff = 1 << 30;
567 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
569 /* PLL output max 240 MHz (or 180 MHz per errata) */
570 if (out_freq > 240000000)
573 for (i = 1; i < 256; i++) {
575 unsigned input, mul1;
578 * PLL input between 1MHz and 32MHz per spec, but lower
579 * frequences seem necessary in some cases so allow 100K.
580 * Warning: some newer products need 2MHz min.
582 input = main_freq / i;
583 if (cpu_is_at91sam9g20() && input < 2000000)
587 if (input > 32000000)
590 mul1 = out_freq / input;
591 if (cpu_is_at91sam9g20() && mul > 63)
598 diff1 = out_freq - input * mul1;
609 if (i == 256 && diff > (out_freq >> 5))
611 return ret | ((mul - 1) << 16) | div;
616 static struct clk *const standard_pmc_clocks[] __initdata = {
617 /* four primary clocks */
626 /* PLLB generated USB full speed clock init */
627 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
630 * USB clock init: choose 48 MHz PLLB value,
631 * disable 48MHz clock during usb peripheral suspend.
633 * REVISIT: assumes MCK doesn't derive from PLLB!
635 uhpck.parent = &pllb;
637 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
638 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
639 if (cpu_is_at91rm9200()) {
640 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
641 udpck.pmc_mask = AT91RM9200_PMC_UDP;
642 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
643 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
644 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
645 cpu_is_at91sam9g10()) {
646 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
647 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
649 at91_pmc_write(AT91_CKGR_PLLBR, 0);
651 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
652 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
655 /* UPLL generated USB full speed clock init */
656 static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
659 * USB clock init: choose 480 MHz from UPLL,
661 unsigned int usbr = AT91_PMC_USBS_UPLL;
663 /* Setup divider by 10 to reach 48 MHz */
664 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
666 at91_pmc_write(AT91_PMC_USB, usbr);
668 /* Now set uhpck values */
669 uhpck.parent = &utmi_clk;
670 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
671 uhpck.rate_hz = utmi_clk.rate_hz;
672 uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
675 static int __init at91_pmc_init(unsigned long main_clock)
677 unsigned tmp, freq, mckr;
679 int pll_overclock = false;
682 * When the bootloader initialized the main oscillator correctly,
683 * there's no problem using the cycle counter. But if it didn't,
684 * or when using oscillator bypass mode, we must be told the speed
689 tmp = at91_pmc_read(AT91_CKGR_MCFR);
690 } while (!(tmp & AT91_PMC_MAINRDY));
691 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
693 main_clk.rate_hz = main_clock;
695 /* report if PLLA is more than mildly overclocked */
696 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
697 if (cpu_has_300M_plla()) {
698 if (plla.rate_hz > 300000000)
699 pll_overclock = true;
700 } else if (cpu_has_800M_plla()) {
701 if (plla.rate_hz > 800000000)
702 pll_overclock = true;
704 if (plla.rate_hz > 209000000)
705 pll_overclock = true;
708 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
710 if (cpu_has_plladiv2()) {
711 mckr = at91_pmc_read(AT91_PMC_MCKR);
712 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
715 if (!cpu_has_pllb() && cpu_has_upll()) {
716 /* setup UTMI clock as the fourth primary clock
717 * (instead of pllb) */
718 utmi_clk.type |= CLK_TYPE_PRIMARY;
726 if (cpu_has_utmi()) {
728 * multiplier is hard-wired to 40
729 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
731 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
733 /* UTMI bias and PLL are managed at the same time */
735 utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
742 at91_pllb_usbfs_clock_init(main_clock);
744 /* assumes that we choose UPLL for USB and not PLLA */
745 at91_upll_usbfs_clock_init(main_clock);
748 * MCK and CPU derive from one of those primary clocks.
749 * For now, assume this parentage won't change.
751 mckr = at91_pmc_read(AT91_PMC_MCKR);
752 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
753 freq = mck.parent->rate_hz;
754 freq /= pmc_prescaler_divider(mckr); /* prescale */
755 if (cpu_is_at91rm9200()) {
756 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
757 } else if (cpu_is_at91sam9g20()) {
758 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
759 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
760 if (mckr & AT91_PMC_PDIV)
761 freq /= 2; /* processor clock division */
762 } else if (cpu_has_mdiv3()) {
763 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
764 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
766 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
769 if (cpu_has_alt_prescaler()) {
770 /* Programmable clocks can use MCK */
771 mck.type |= CLK_TYPE_PRIMARY;
775 /* Register the PMC's standard clocks */
776 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
777 at91_clk_add(standard_pmc_clocks[i]);
783 at91_clk_add(&uhpck);
786 at91_clk_add(&udpck);
789 at91_clk_add(&utmi_clk);
791 /* MCK and CPU clock are "always on" */
794 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
795 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
796 (unsigned) main_clock / 1000000,
797 ((unsigned) main_clock % 1000000) / 1000);
802 #if defined(CONFIG_OF)
803 static struct of_device_id pmc_ids[] = {
804 { .compatible = "atmel,at91rm9200-pmc" },
808 static struct of_device_id osc_ids[] = {
809 { .compatible = "atmel,osc" },
813 int __init at91_dt_clock_init(void)
815 struct device_node *np;
818 np = of_find_matching_node(NULL, pmc_ids);
820 panic("unable to find compatible pmc node in dtb\n");
822 at91_pmc_base = of_iomap(np, 0);
824 panic("unable to map pmc cpu registers\n");
828 /* retrieve the freqency of fixed clocks from device tree */
829 np = of_find_matching_node(NULL, osc_ids);
832 if (!of_property_read_u32(np, "clock-frequency", &rate))
838 return at91_pmc_init(main_clock);
842 int __init at91_clock_init(unsigned long main_clock)
844 at91_pmc_base = ioremap(AT91_PMC, 256);
846 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
848 return at91_pmc_init(main_clock);
852 * Several unused clocks may be active. Turn them off.
854 static int __init at91_clock_reset(void)
856 unsigned long pcdr = 0;
857 unsigned long scdr = 0;
860 list_for_each_entry(clk, &clocks, node) {
864 if (clk->mode == pmc_periph_mode)
865 pcdr |= clk->pmc_mask;
867 if (clk->mode == pmc_sys_mode)
868 scdr |= clk->pmc_mask;
870 pr_debug("Clocks: disable unused %s\n", clk->name);
873 at91_pmc_write(AT91_PMC_PCDR, pcdr);
874 at91_pmc_write(AT91_PMC_SCDR, scdr);
878 late_initcall(at91_clock_reset);
880 void at91sam9_idle(void)
882 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);