Pileus Git - ~andy/linux/blob - arch/arm/mach-at91/at91rm9200.c

   1 /*
   2  * arch/arm/mach-at91/at91rm9200.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/irq.h>
  16 #include <asm/mach/arch.h>
  17 #include <asm/mach/map.h>
  18 #include <asm/system_misc.h>
  19 #include <mach/at91rm9200.h>
  20 #include <mach/at91_pmc.h>
  21 #include <mach/at91_st.h>
  22 #include <mach/cpu.h>
  23
  24 #include "soc.h"
  25 #include "generic.h"
  26 #include "clock.h"
  27 #include "sam9_smc.h"
  28
  29 static struct map_desc at91rm9200_io_desc[] __initdata = {
  30         {
  31                 .virtual        = AT91_VA_BASE_EMAC,
  32                 .pfn            = __phys_to_pfn(AT91RM9200_BASE_EMAC),
  33                 .length         = SZ_16K,
  34                 .type           = MT_DEVICE,
  35         },
  36 };
  37
  38 /* --------------------------------------------------------------------
  39  *  Clocks
  40  * -------------------------------------------------------------------- */
  41
  42 /*
  43  * The peripheral clocks.
  44  */
  45 static struct clk udc_clk = {
  46         .name           = "udc_clk",
  47         .pmc_mask       = 1 << AT91RM9200_ID_UDP,
  48         .type           = CLK_TYPE_PERIPHERAL,
  49 };
  50 static struct clk ohci_clk = {
  51         .name           = "ohci_clk",
  52         .pmc_mask       = 1 << AT91RM9200_ID_UHP,
  53         .type           = CLK_TYPE_PERIPHERAL,
  54 };
  55 static struct clk ether_clk = {
  56         .name           = "ether_clk",
  57         .pmc_mask       = 1 << AT91RM9200_ID_EMAC,
  58         .type           = CLK_TYPE_PERIPHERAL,
  59 };
  60 static struct clk mmc_clk = {
  61         .name           = "mci_clk",
  62         .pmc_mask       = 1 << AT91RM9200_ID_MCI,
  63         .type           = CLK_TYPE_PERIPHERAL,
  64 };
  65 static struct clk twi_clk = {
  66         .name           = "twi_clk",
  67         .pmc_mask       = 1 << AT91RM9200_ID_TWI,
  68         .type           = CLK_TYPE_PERIPHERAL,
  69 };
  70 static struct clk usart0_clk = {
  71         .name           = "usart0_clk",
  72         .pmc_mask       = 1 << AT91RM9200_ID_US0,
  73         .type           = CLK_TYPE_PERIPHERAL,
  74 };
  75 static struct clk usart1_clk = {
  76         .name           = "usart1_clk",
  77         .pmc_mask       = 1 << AT91RM9200_ID_US1,
  78         .type           = CLK_TYPE_PERIPHERAL,
  79 };
  80 static struct clk usart2_clk = {
  81         .name           = "usart2_clk",
  82         .pmc_mask       = 1 << AT91RM9200_ID_US2,
  83         .type           = CLK_TYPE_PERIPHERAL,
  84 };
  85 static struct clk usart3_clk = {
  86         .name           = "usart3_clk",
  87         .pmc_mask       = 1 << AT91RM9200_ID_US3,
  88         .type           = CLK_TYPE_PERIPHERAL,
  89 };
  90 static struct clk spi_clk = {
  91         .name           = "spi_clk",
  92         .pmc_mask       = 1 << AT91RM9200_ID_SPI,
  93         .type           = CLK_TYPE_PERIPHERAL,
  94 };
  95 static struct clk pioA_clk = {
  96         .name           = "pioA_clk",
  97         .pmc_mask       = 1 << AT91RM9200_ID_PIOA,
  98         .type           = CLK_TYPE_PERIPHERAL,
  99 };
 100 static struct clk pioB_clk = {
 101         .name           = "pioB_clk",
 102         .pmc_mask       = 1 << AT91RM9200_ID_PIOB,
 103         .type           = CLK_TYPE_PERIPHERAL,
 104 };
 105 static struct clk pioC_clk = {
 106         .name           = "pioC_clk",
 107         .pmc_mask       = 1 << AT91RM9200_ID_PIOC,
 108         .type           = CLK_TYPE_PERIPHERAL,
 109 };
 110 static struct clk pioD_clk = {
 111         .name           = "pioD_clk",
 112         .pmc_mask       = 1 << AT91RM9200_ID_PIOD,
 113         .type           = CLK_TYPE_PERIPHERAL,
 114 };
 115 static struct clk ssc0_clk = {
 116         .name           = "ssc0_clk",
 117         .pmc_mask       = 1 << AT91RM9200_ID_SSC0,
 118         .type           = CLK_TYPE_PERIPHERAL,
 119 };
 120 static struct clk ssc1_clk = {
 121         .name           = "ssc1_clk",
 122         .pmc_mask       = 1 << AT91RM9200_ID_SSC1,
 123         .type           = CLK_TYPE_PERIPHERAL,
 124 };
 125 static struct clk ssc2_clk = {
 126         .name           = "ssc2_clk",
 127         .pmc_mask       = 1 << AT91RM9200_ID_SSC2,
 128         .type           = CLK_TYPE_PERIPHERAL,
 129 };
 130 static struct clk tc0_clk = {
 131         .name           = "tc0_clk",
 132         .pmc_mask       = 1 << AT91RM9200_ID_TC0,
 133         .type           = CLK_TYPE_PERIPHERAL,
 134 };
 135 static struct clk tc1_clk = {
 136         .name           = "tc1_clk",
 137         .pmc_mask       = 1 << AT91RM9200_ID_TC1,
 138         .type           = CLK_TYPE_PERIPHERAL,
 139 };
 140 static struct clk tc2_clk = {
 141         .name           = "tc2_clk",
 142         .pmc_mask       = 1 << AT91RM9200_ID_TC2,
 143         .type           = CLK_TYPE_PERIPHERAL,
 144 };
 145 static struct clk tc3_clk = {
 146         .name           = "tc3_clk",
 147         .pmc_mask       = 1 << AT91RM9200_ID_TC3,
 148         .type           = CLK_TYPE_PERIPHERAL,
 149 };
 150 static struct clk tc4_clk = {
 151         .name           = "tc4_clk",
 152         .pmc_mask       = 1 << AT91RM9200_ID_TC4,
 153         .type           = CLK_TYPE_PERIPHERAL,
 154 };
 155 static struct clk tc5_clk = {
 156         .name           = "tc5_clk",
 157         .pmc_mask       = 1 << AT91RM9200_ID_TC5,
 158         .type           = CLK_TYPE_PERIPHERAL,
 159 };
 160
 161 static struct clk *periph_clocks[] __initdata = {
 162         &pioA_clk,
 163         &pioB_clk,
 164         &pioC_clk,
 165         &pioD_clk,
 166         &usart0_clk,
 167         &usart1_clk,
 168         &usart2_clk,
 169         &usart3_clk,
 170         &mmc_clk,
 171         &udc_clk,
 172         &twi_clk,
 173         &spi_clk,
 174         &ssc0_clk,
 175         &ssc1_clk,
 176         &ssc2_clk,
 177         &tc0_clk,
 178         &tc1_clk,
 179         &tc2_clk,
 180         &tc3_clk,
 181         &tc4_clk,
 182         &tc5_clk,
 183         &ohci_clk,
 184         &ether_clk,
 185         // irq0 .. irq6
 186 };
 187
 188 static struct clk_lookup periph_clocks_lookups[] = {
 189         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 190         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 191         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 192         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 193         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 194         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 195         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 196         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 197         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
 198         /* fake hclk clock */
 199         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 200         CLKDEV_CON_ID("pioA", &pioA_clk),
 201         CLKDEV_CON_ID("pioB", &pioB_clk),
 202         CLKDEV_CON_ID("pioC", &pioC_clk),
 203         CLKDEV_CON_ID("pioD", &pioD_clk),
 204 };
 205
 206 static struct clk_lookup usart_clocks_lookups[] = {
 207         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 208         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 209         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 210         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 211         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 212 };
 213
 214 /*
 215  * The four programmable clocks.
 216  * You must configure pin multiplexing to bring these signals out.
 217  */
 218 static struct clk pck0 = {
 219         .name           = "pck0",
 220         .pmc_mask       = AT91_PMC_PCK0,
 221         .type           = CLK_TYPE_PROGRAMMABLE,
 222         .id             = 0,
 223 };
 224 static struct clk pck1 = {
 225         .name           = "pck1",
 226         .pmc_mask       = AT91_PMC_PCK1,
 227         .type           = CLK_TYPE_PROGRAMMABLE,
 228         .id             = 1,
 229 };
 230 static struct clk pck2 = {
 231         .name           = "pck2",
 232         .pmc_mask       = AT91_PMC_PCK2,
 233         .type           = CLK_TYPE_PROGRAMMABLE,
 234         .id             = 2,
 235 };
 236 static struct clk pck3 = {
 237         .name           = "pck3",
 238         .pmc_mask       = AT91_PMC_PCK3,
 239         .type           = CLK_TYPE_PROGRAMMABLE,
 240         .id             = 3,
 241 };
 242
 243 static void __init at91rm9200_register_clocks(void)
 244 {
 245         int i;
 246
 247         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 248                 clk_register(periph_clocks[i]);
 249
 250         clkdev_add_table(periph_clocks_lookups,
 251                          ARRAY_SIZE(periph_clocks_lookups));
 252         clkdev_add_table(usart_clocks_lookups,
 253                          ARRAY_SIZE(usart_clocks_lookups));
 254
 255         clk_register(&pck0);
 256         clk_register(&pck1);
 257         clk_register(&pck2);
 258         clk_register(&pck3);
 259 }
 260
 261 static struct clk_lookup console_clock_lookup;
 262
 263 void __init at91rm9200_set_console_clock(int id)
 264 {
 265         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 266                 return;
 267
 268         console_clock_lookup.con_id = "usart";
 269         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 270         clkdev_add(&console_clock_lookup);
 271 }
 272
 273 /* --------------------------------------------------------------------
 274  *  GPIO
 275  * -------------------------------------------------------------------- */
 276
 277 static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
 278         {
 279                 .id             = AT91RM9200_ID_PIOA,
 280                 .regbase        = AT91RM9200_BASE_PIOA,
 281         }, {
 282                 .id             = AT91RM9200_ID_PIOB,
 283                 .regbase        = AT91RM9200_BASE_PIOB,
 284         }, {
 285                 .id             = AT91RM9200_ID_PIOC,
 286                 .regbase        = AT91RM9200_BASE_PIOC,
 287         }, {
 288                 .id             = AT91RM9200_ID_PIOD,
 289                 .regbase        = AT91RM9200_BASE_PIOD,
 290         }
 291 };
 292
 293 static void at91rm9200_idle(void)
 294 {
 295         /*
 296          * Disable the processor clock.  The processor will be automatically
 297          * re-enabled by an interrupt or by a reset.
 298          */
 299         at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 300 }
 301
 302 static void at91rm9200_restart(char mode, const char *cmd)
 303 {
 304         /*
 305          * Perform a hardware reset with the use of the Watchdog timer.
 306          */
 307         at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
 308         at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
 309 }
 310
 311 /* --------------------------------------------------------------------
 312  *  AT91RM9200 processor initialization
 313  * -------------------------------------------------------------------- */
 314 static void __init at91rm9200_map_io(void)
 315 {
 316         /* Map peripherals */
 317         at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
 318         iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
 319 }
 320
 321 static void __init at91rm9200_ioremap_registers(void)
 322 {
 323         at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
 324         at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
 325 }
 326
 327 static void __init at91rm9200_initialize(void)
 328 {
 329         arm_pm_idle = at91rm9200_idle;
 330         arm_pm_restart = at91rm9200_restart;
 331         at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
 332                         | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
 333                         | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
 334                         | (1 << AT91RM9200_ID_IRQ6);
 335
 336         /* Initialize GPIO subsystem */
 337         at91_gpio_init(at91rm9200_gpio,
 338                 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
 339 }
 340
 341
 342 /* --------------------------------------------------------------------
 343  *  Interrupt initialization
 344  * -------------------------------------------------------------------- */
 345
 346 /*
 347  * The default interrupt priority levels (0 = lowest, 7 = highest).
 348  */
 349 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 350         7,      /* Advanced Interrupt Controller (FIQ) */
 351         7,      /* System Peripherals */
 352         1,      /* Parallel IO Controller A */
 353         1,      /* Parallel IO Controller B */
 354         1,      /* Parallel IO Controller C */
 355         1,      /* Parallel IO Controller D */
 356         5,      /* USART 0 */
 357         5,      /* USART 1 */
 358         5,      /* USART 2 */
 359         5,      /* USART 3 */
 360         0,      /* Multimedia Card Interface */
 361         2,      /* USB Device Port */
 362         6,      /* Two-Wire Interface */
 363         5,      /* Serial Peripheral Interface */
 364         4,      /* Serial Synchronous Controller 0 */
 365         4,      /* Serial Synchronous Controller 1 */
 366         4,      /* Serial Synchronous Controller 2 */
 367         0,      /* Timer Counter 0 */
 368         0,      /* Timer Counter 1 */
 369         0,      /* Timer Counter 2 */
 370         0,      /* Timer Counter 3 */
 371         0,      /* Timer Counter 4 */
 372         0,      /* Timer Counter 5 */
 373         2,      /* USB Host port */
 374         3,      /* Ethernet MAC */
 375         0,      /* Advanced Interrupt Controller (IRQ0) */
 376         0,      /* Advanced Interrupt Controller (IRQ1) */
 377         0,      /* Advanced Interrupt Controller (IRQ2) */
 378         0,      /* Advanced Interrupt Controller (IRQ3) */
 379         0,      /* Advanced Interrupt Controller (IRQ4) */
 380         0,      /* Advanced Interrupt Controller (IRQ5) */
 381         0       /* Advanced Interrupt Controller (IRQ6) */
 382 };
 383
 384 struct at91_init_soc __initdata at91rm9200_soc = {
 385         .map_io = at91rm9200_map_io,
 386         .default_irq_priority = at91rm9200_default_irq_priority,
 387         .ioremap_registers = at91rm9200_ioremap_registers,
 388         .register_clocks = at91rm9200_register_clocks,
 389         .init = at91rm9200_initialize,
 390 };