2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Authors: Rusty Russell <rusty@rustcorp.com.au>
4 * Christoffer Dall <c.dall@virtualopensystems.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 #include <linux/kvm_host.h>
21 #include <linux/uaccess.h>
22 #include <asm/kvm_arm.h>
23 #include <asm/kvm_host.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_coproc.h>
26 #include <asm/cacheflush.h>
27 #include <asm/cputype.h>
28 #include <trace/events/kvm.h>
30 #include "../vfp/vfpinstr.h"
36 /******************************************************************************
37 * Co-processor emulation
38 *****************************************************************************/
40 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
41 static u32 cache_levels;
43 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
46 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
48 kvm_inject_undefined(vcpu);
52 int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
55 * We can get here, if the host has been built without VFPv3 support,
56 * but the guest attempted a floating point operation.
58 kvm_inject_undefined(vcpu);
62 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
64 kvm_inject_undefined(vcpu);
68 int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
70 kvm_inject_undefined(vcpu);
74 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
77 * Compute guest MPIDR. We build a virtual cluster out of the
78 * vcpu_id, but we read the 'U' bit from the underlying
81 vcpu->arch.cp15[c0_MPIDR] = ((read_cpuid_mpidr() & MPIDR_SMP_BITMASK) |
82 ((vcpu->vcpu_id >> 2) << MPIDR_LEVEL_BITS) |
86 /* TRM entries A7:4.3.31 A15:4.3.28 - RO WI */
87 static bool access_actlr(struct kvm_vcpu *vcpu,
88 const struct coproc_params *p,
89 const struct coproc_reg *r)
92 return ignore_write(vcpu, p);
94 *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c1_ACTLR];
98 /* TRM entries A7:4.3.56, A15:4.3.60 - R/O. */
99 static bool access_cbar(struct kvm_vcpu *vcpu,
100 const struct coproc_params *p,
101 const struct coproc_reg *r)
104 return write_to_read_only(vcpu, p);
105 return read_zero(vcpu, p);
108 /* TRM entries A7:4.3.49, A15:4.3.48 - R/O WI */
109 static bool access_l2ctlr(struct kvm_vcpu *vcpu,
110 const struct coproc_params *p,
111 const struct coproc_reg *r)
114 return ignore_write(vcpu, p);
116 *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c9_L2CTLR];
120 static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
124 asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
125 l2ctlr &= ~(3 << 24);
126 ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
127 l2ctlr |= (ncores & 3) << 24;
129 vcpu->arch.cp15[c9_L2CTLR] = l2ctlr;
132 static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
136 /* ACTLR contains SMP bit: make sure you create all cpus first! */
137 asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
138 /* Make the SMP bit consistent with the guest configuration */
139 if (atomic_read(&vcpu->kvm->online_vcpus) > 1)
144 vcpu->arch.cp15[c1_ACTLR] = actlr;
148 * TRM entries: A7:4.3.50, A15:4.3.49
149 * R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored).
151 static bool access_l2ectlr(struct kvm_vcpu *vcpu,
152 const struct coproc_params *p,
153 const struct coproc_reg *r)
156 return ignore_write(vcpu, p);
158 *vcpu_reg(vcpu, p->Rt1) = 0;
162 /* See note at ARM ARM B1.14.4 */
163 static bool access_dcsw(struct kvm_vcpu *vcpu,
164 const struct coproc_params *p,
165 const struct coproc_reg *r)
171 return read_from_write_only(vcpu, p);
175 cpumask_setall(&vcpu->arch.require_dcache_flush);
176 cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
178 /* If we were already preempted, take the long way around */
179 if (cpu != vcpu->arch.last_pcpu) {
184 val = *vcpu_reg(vcpu, p->Rt1);
187 case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
188 case 14: /* DCCISW */
189 asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
193 asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
204 * We could trap ID_DFR0 and tell the guest we don't support performance
205 * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
206 * NAKed, so it will read the PMCR anyway.
208 * Therefore we tell the guest we have 0 counters. Unfortunately, we
209 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
210 * all PM registers, which doesn't crash the guest kernel at least.
212 static bool pm_fake(struct kvm_vcpu *vcpu,
213 const struct coproc_params *p,
214 const struct coproc_reg *r)
217 return ignore_write(vcpu, p);
219 return read_zero(vcpu, p);
222 #define access_pmcr pm_fake
223 #define access_pmcntenset pm_fake
224 #define access_pmcntenclr pm_fake
225 #define access_pmovsr pm_fake
226 #define access_pmselr pm_fake
227 #define access_pmceid0 pm_fake
228 #define access_pmceid1 pm_fake
229 #define access_pmccntr pm_fake
230 #define access_pmxevtyper pm_fake
231 #define access_pmxevcntr pm_fake
232 #define access_pmuserenr pm_fake
233 #define access_pmintenset pm_fake
234 #define access_pmintenclr pm_fake
236 /* Architected CP15 registers.
237 * CRn denotes the primary register number, but is copied to the CRm in the
238 * user space API for 64-bit register access in line with the terminology used
240 * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
241 * registers preceding 32-bit ones.
243 static const struct coproc_reg cp15_regs[] = {
244 /* MPIDR: we use VMPIDR for guest access. */
245 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
246 NULL, reset_mpidr, c0_MPIDR },
248 /* CSSELR: swapped by interrupt.S. */
249 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
250 NULL, reset_unknown, c0_CSSELR },
252 /* ACTLR: trapped by HCR.TAC bit. */
253 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
254 access_actlr, reset_actlr, c1_ACTLR },
256 /* CPACR: swapped by interrupt.S. */
257 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
258 NULL, reset_val, c1_CPACR, 0x00000000 },
260 /* TTBR0/TTBR1: swapped by interrupt.S. */
261 { CRm64( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
262 { CRm64( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
264 /* TTBCR: swapped by interrupt.S. */
265 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
266 NULL, reset_val, c2_TTBCR, 0x00000000 },
268 /* DACR: swapped by interrupt.S. */
269 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
270 NULL, reset_unknown, c3_DACR },
272 /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
273 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
274 NULL, reset_unknown, c5_DFSR },
275 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
276 NULL, reset_unknown, c5_IFSR },
277 { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
278 NULL, reset_unknown, c5_ADFSR },
279 { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
280 NULL, reset_unknown, c5_AIFSR },
282 /* DFAR/IFAR: swapped by interrupt.S. */
283 { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
284 NULL, reset_unknown, c6_DFAR },
285 { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
286 NULL, reset_unknown, c6_IFAR },
288 /* PAR swapped by interrupt.S */
289 { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
292 * DC{C,I,CI}SW operations:
294 { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
295 { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
296 { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
298 * L2CTLR access (guest wants to know #CPUs).
300 { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32,
301 access_l2ctlr, reset_l2ctlr, c9_L2CTLR },
302 { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr},
305 * Dummy performance monitor implementation.
307 { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
308 { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
309 { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
310 { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
311 { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
312 { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
313 { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
314 { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
315 { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
316 { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
317 { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
318 { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
319 { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
321 /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
322 { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
323 NULL, reset_unknown, c10_PRRR},
324 { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
325 NULL, reset_unknown, c10_NMRR},
327 /* VBAR: swapped by interrupt.S. */
328 { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
329 NULL, reset_val, c12_VBAR, 0x00000000 },
331 /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
332 { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
333 NULL, reset_val, c13_CID, 0x00000000 },
334 { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
335 NULL, reset_unknown, c13_TID_URW },
336 { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
337 NULL, reset_unknown, c13_TID_URO },
338 { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
339 NULL, reset_unknown, c13_TID_PRIV },
341 /* CNTKCTL: swapped by interrupt.S. */
342 { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
343 NULL, reset_val, c14_CNTKCTL, 0x00000000 },
345 /* The Configuration Base Address Register. */
346 { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
349 /* Target specific emulation tables */
350 static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
352 void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
356 for (i = 1; i < table->num; i++)
357 BUG_ON(cmp_reg(&table->table[i-1],
358 &table->table[i]) >= 0);
360 target_tables[table->target] = table;
363 /* Get specific register table for this target. */
364 static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
366 struct kvm_coproc_target_table *table;
368 table = target_tables[target];
373 static const struct coproc_reg *find_reg(const struct coproc_params *params,
374 const struct coproc_reg table[],
379 for (i = 0; i < num; i++) {
380 const struct coproc_reg *r = &table[i];
382 if (params->is_64bit != r->is_64)
384 if (params->CRn != r->CRn)
386 if (params->CRm != r->CRm)
388 if (params->Op1 != r->Op1)
390 if (params->Op2 != r->Op2)
398 static int emulate_cp15(struct kvm_vcpu *vcpu,
399 const struct coproc_params *params)
402 const struct coproc_reg *table, *r;
404 trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
405 params->CRm, params->Op2, params->is_write);
407 table = get_target_table(vcpu->arch.target, &num);
409 /* Search target-specific then generic table. */
410 r = find_reg(params, table, num);
412 r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
415 /* If we don't have an accessor, we should never get here! */
418 if (likely(r->access(vcpu, params, r))) {
419 /* Skip instruction, since it was emulated */
420 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
423 /* If access function fails, it should complain. */
425 kvm_err("Unsupported guest CP15 access at: %08lx\n",
427 print_cp_instr(params);
429 kvm_inject_undefined(vcpu);
434 * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
435 * @vcpu: The VCPU pointer
436 * @run: The kvm_run struct
438 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
440 struct coproc_params params;
442 params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
443 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
444 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
445 params.is_64bit = true;
447 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
449 params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
452 return emulate_cp15(vcpu, ¶ms);
455 static void reset_coproc_regs(struct kvm_vcpu *vcpu,
456 const struct coproc_reg *table, size_t num)
460 for (i = 0; i < num; i++)
462 table[i].reset(vcpu, &table[i]);
466 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
467 * @vcpu: The VCPU pointer
468 * @run: The kvm_run struct
470 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
472 struct coproc_params params;
474 params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
475 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
476 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
477 params.is_64bit = false;
479 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
480 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
481 params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
484 return emulate_cp15(vcpu, ¶ms);
487 /******************************************************************************
489 *****************************************************************************/
491 static bool index_to_params(u64 id, struct coproc_params *params)
493 switch (id & KVM_REG_SIZE_MASK) {
494 case KVM_REG_SIZE_U32:
495 /* Any unused index bits means it's not valid. */
496 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
497 | KVM_REG_ARM_COPROC_MASK
498 | KVM_REG_ARM_32_CRN_MASK
499 | KVM_REG_ARM_CRM_MASK
500 | KVM_REG_ARM_OPC1_MASK
501 | KVM_REG_ARM_32_OPC2_MASK))
504 params->is_64bit = false;
505 params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
506 >> KVM_REG_ARM_32_CRN_SHIFT);
507 params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
508 >> KVM_REG_ARM_CRM_SHIFT);
509 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
510 >> KVM_REG_ARM_OPC1_SHIFT);
511 params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
512 >> KVM_REG_ARM_32_OPC2_SHIFT);
514 case KVM_REG_SIZE_U64:
515 /* Any unused index bits means it's not valid. */
516 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
517 | KVM_REG_ARM_COPROC_MASK
518 | KVM_REG_ARM_CRM_MASK
519 | KVM_REG_ARM_OPC1_MASK))
521 params->is_64bit = true;
522 /* CRm to CRn: see cp15_to_index for details */
523 params->CRn = ((id & KVM_REG_ARM_CRM_MASK)
524 >> KVM_REG_ARM_CRM_SHIFT);
525 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
526 >> KVM_REG_ARM_OPC1_SHIFT);
535 /* Decode an index value, and find the cp15 coproc_reg entry. */
536 static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
540 const struct coproc_reg *table, *r;
541 struct coproc_params params;
543 /* We only do cp15 for now. */
544 if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
547 if (!index_to_params(id, ¶ms))
550 table = get_target_table(vcpu->arch.target, &num);
551 r = find_reg(¶ms, table, num);
553 r = find_reg(¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
555 /* Not saved in the cp15 array? */
563 * These are the invariant cp15 registers: we let the guest see the host
564 * versions of these, so they're part of the guest state.
566 * A future CPU may provide a mechanism to present different values to
567 * the guest, or a future kvm may trap them.
569 /* Unfortunately, there's no register-argument for mrc, so generate. */
570 #define FUNCTION_FOR32(crn, crm, op1, op2, name) \
571 static void get_##name(struct kvm_vcpu *v, \
572 const struct coproc_reg *r) \
576 asm volatile("mrc p15, " __stringify(op1) \
577 ", %0, c" __stringify(crn) \
578 ", c" __stringify(crm) \
579 ", " __stringify(op2) "\n" : "=r" (val)); \
580 ((struct coproc_reg *)r)->val = val; \
583 FUNCTION_FOR32(0, 0, 0, 0, MIDR)
584 FUNCTION_FOR32(0, 0, 0, 1, CTR)
585 FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
586 FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
587 FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
588 FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
589 FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
590 FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
591 FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
592 FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
593 FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
594 FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
595 FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
596 FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
597 FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
598 FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
599 FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
600 FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
601 FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
602 FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
603 FUNCTION_FOR32(0, 0, 1, 7, AIDR)
605 /* ->val is filled in by kvm_invariant_coproc_table_init() */
606 static struct coproc_reg invariant_cp15[] = {
607 { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
608 { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
609 { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
610 { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
611 { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
613 { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
614 { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
615 { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
616 { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
617 { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
618 { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
619 { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
620 { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
622 { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
623 { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
624 { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
625 { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
626 { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
627 { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
629 { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
630 { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
633 static int reg_from_user(void *val, const void __user *uaddr, u64 id)
635 /* This Just Works because we are little endian. */
636 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
641 static int reg_to_user(void __user *uaddr, const void *val, u64 id)
643 /* This Just Works because we are little endian. */
644 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
649 static int get_invariant_cp15(u64 id, void __user *uaddr)
651 struct coproc_params params;
652 const struct coproc_reg *r;
654 if (!index_to_params(id, ¶ms))
657 r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15));
661 return reg_to_user(uaddr, &r->val, id);
664 static int set_invariant_cp15(u64 id, void __user *uaddr)
666 struct coproc_params params;
667 const struct coproc_reg *r;
669 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
671 if (!index_to_params(id, ¶ms))
673 r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15));
677 err = reg_from_user(&val, uaddr, id);
681 /* This is what we mean by invariant: you can't change it. */
688 static bool is_valid_cache(u32 val)
692 if (val >= CSSELR_MAX)
695 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
697 ctype = (cache_levels >> (level * 3)) & 7;
700 case 0: /* No cache */
702 case 1: /* Instruction cache only */
704 case 2: /* Data cache only */
705 case 4: /* Unified cache */
707 case 3: /* Separate instruction and data caches */
709 default: /* Reserved: we can't know instruction or data. */
714 /* Which cache CCSIDR represents depends on CSSELR value. */
715 static u32 get_ccsidr(u32 csselr)
719 /* Make sure noone else changes CSSELR during this! */
721 /* Put value into CSSELR */
722 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
724 /* Read result out of CCSIDR */
725 asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
731 static int demux_c15_get(u64 id, void __user *uaddr)
734 u32 __user *uval = uaddr;
736 /* Fail if we have unknown bits set. */
737 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
738 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
741 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
742 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
743 if (KVM_REG_SIZE(id) != 4)
745 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
746 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
747 if (!is_valid_cache(val))
750 return put_user(get_ccsidr(val), uval);
756 static int demux_c15_set(u64 id, void __user *uaddr)
759 u32 __user *uval = uaddr;
761 /* Fail if we have unknown bits set. */
762 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
763 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
766 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
767 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
768 if (KVM_REG_SIZE(id) != 4)
770 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
771 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
772 if (!is_valid_cache(val))
775 if (get_user(newval, uval))
778 /* This is also invariant: you can't change it. */
779 if (newval != get_ccsidr(val))
788 static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
789 KVM_REG_ARM_VFP_FPSCR,
790 KVM_REG_ARM_VFP_FPINST,
791 KVM_REG_ARM_VFP_FPINST2,
792 KVM_REG_ARM_VFP_MVFR0,
793 KVM_REG_ARM_VFP_MVFR1,
794 KVM_REG_ARM_VFP_FPSID };
796 static unsigned int num_fp_regs(void)
798 if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
804 static unsigned int num_vfp_regs(void)
806 /* Normal FP regs + control regs. */
807 return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
810 static int copy_vfp_regids(u64 __user *uindices)
813 const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
814 const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
816 for (i = 0; i < num_fp_regs(); i++) {
817 if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
823 for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
824 if (put_user(u32reg | vfp_sysregs[i], uindices))
829 return num_vfp_regs();
832 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
834 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
837 /* Fail if we have unknown bits set. */
838 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
839 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
842 if (vfpid < num_fp_regs()) {
843 if (KVM_REG_SIZE(id) != 8)
845 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpregs[vfpid],
849 /* FP control registers are all 32 bit. */
850 if (KVM_REG_SIZE(id) != 4)
854 case KVM_REG_ARM_VFP_FPEXC:
855 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpexc, id);
856 case KVM_REG_ARM_VFP_FPSCR:
857 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpscr, id);
858 case KVM_REG_ARM_VFP_FPINST:
859 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst, id);
860 case KVM_REG_ARM_VFP_FPINST2:
861 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst2, id);
862 case KVM_REG_ARM_VFP_MVFR0:
864 return reg_to_user(uaddr, &val, id);
865 case KVM_REG_ARM_VFP_MVFR1:
867 return reg_to_user(uaddr, &val, id);
868 case KVM_REG_ARM_VFP_FPSID:
870 return reg_to_user(uaddr, &val, id);
876 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
878 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
881 /* Fail if we have unknown bits set. */
882 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
883 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
886 if (vfpid < num_fp_regs()) {
887 if (KVM_REG_SIZE(id) != 8)
889 return reg_from_user(&vcpu->arch.vfp_guest.fpregs[vfpid],
893 /* FP control registers are all 32 bit. */
894 if (KVM_REG_SIZE(id) != 4)
898 case KVM_REG_ARM_VFP_FPEXC:
899 return reg_from_user(&vcpu->arch.vfp_guest.fpexc, uaddr, id);
900 case KVM_REG_ARM_VFP_FPSCR:
901 return reg_from_user(&vcpu->arch.vfp_guest.fpscr, uaddr, id);
902 case KVM_REG_ARM_VFP_FPINST:
903 return reg_from_user(&vcpu->arch.vfp_guest.fpinst, uaddr, id);
904 case KVM_REG_ARM_VFP_FPINST2:
905 return reg_from_user(&vcpu->arch.vfp_guest.fpinst2, uaddr, id);
906 /* These are invariant. */
907 case KVM_REG_ARM_VFP_MVFR0:
908 if (reg_from_user(&val, uaddr, id))
910 if (val != fmrx(MVFR0))
913 case KVM_REG_ARM_VFP_MVFR1:
914 if (reg_from_user(&val, uaddr, id))
916 if (val != fmrx(MVFR1))
919 case KVM_REG_ARM_VFP_FPSID:
920 if (reg_from_user(&val, uaddr, id))
922 if (val != fmrx(FPSID))
929 #else /* !CONFIG_VFPv3 */
930 static unsigned int num_vfp_regs(void)
935 static int copy_vfp_regids(u64 __user *uindices)
940 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
945 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
949 #endif /* !CONFIG_VFPv3 */
951 int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
953 const struct coproc_reg *r;
954 void __user *uaddr = (void __user *)(long)reg->addr;
956 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
957 return demux_c15_get(reg->id, uaddr);
959 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
960 return vfp_get_reg(vcpu, reg->id, uaddr);
962 r = index_to_coproc_reg(vcpu, reg->id);
964 return get_invariant_cp15(reg->id, uaddr);
966 /* Note: copies two regs if size is 64 bit. */
967 return reg_to_user(uaddr, &vcpu->arch.cp15[r->reg], reg->id);
970 int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
972 const struct coproc_reg *r;
973 void __user *uaddr = (void __user *)(long)reg->addr;
975 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
976 return demux_c15_set(reg->id, uaddr);
978 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
979 return vfp_set_reg(vcpu, reg->id, uaddr);
981 r = index_to_coproc_reg(vcpu, reg->id);
983 return set_invariant_cp15(reg->id, uaddr);
985 /* Note: copies two regs if size is 64 bit */
986 return reg_from_user(&vcpu->arch.cp15[r->reg], uaddr, reg->id);
989 static unsigned int num_demux_regs(void)
991 unsigned int i, count = 0;
993 for (i = 0; i < CSSELR_MAX; i++)
994 if (is_valid_cache(i))
1000 static int write_demux_regids(u64 __user *uindices)
1002 u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1005 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1006 for (i = 0; i < CSSELR_MAX; i++) {
1007 if (!is_valid_cache(i))
1009 if (put_user(val | i, uindices))
1016 static u64 cp15_to_index(const struct coproc_reg *reg)
1018 u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
1020 val |= KVM_REG_SIZE_U64;
1021 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
1023 * CRn always denotes the primary coproc. reg. nr. for the
1024 * in-kernel representation, but the user space API uses the
1025 * CRm for the encoding, because it is modelled after the
1026 * MRRC/MCRR instructions: see the ARM ARM rev. c page
1029 val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT);
1031 val |= KVM_REG_SIZE_U32;
1032 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
1033 val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
1034 val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
1035 val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
1040 static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
1045 if (put_user(cp15_to_index(reg), *uind))
1052 /* Assumed ordered tables, see kvm_coproc_table_init. */
1053 static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
1055 const struct coproc_reg *i1, *i2, *end1, *end2;
1056 unsigned int total = 0;
1059 /* We check for duplicates here, to allow arch-specific overrides. */
1060 i1 = get_target_table(vcpu->arch.target, &num);
1063 end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
1065 BUG_ON(i1 == end1 || i2 == end2);
1067 /* Walk carefully, as both tables may refer to the same register. */
1069 int cmp = cmp_reg(i1, i2);
1070 /* target-specific overrides generic entry. */
1072 /* Ignore registers we trap but don't save. */
1074 if (!copy_reg_to_user(i1, &uind))
1079 /* Ignore registers we trap but don't save. */
1081 if (!copy_reg_to_user(i2, &uind))
1087 if (cmp <= 0 && ++i1 == end1)
1089 if (cmp >= 0 && ++i2 == end2)
1095 unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
1097 return ARRAY_SIZE(invariant_cp15)
1100 + walk_cp15(vcpu, (u64 __user *)NULL);
1103 int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1108 /* Then give them all the invariant registers' indices. */
1109 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
1110 if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
1115 err = walk_cp15(vcpu, uindices);
1120 err = copy_vfp_regids(uindices);
1125 return write_demux_regids(uindices);
1128 void kvm_coproc_table_init(void)
1132 /* Make sure tables are unique and in order. */
1133 for (i = 1; i < ARRAY_SIZE(cp15_regs); i++)
1134 BUG_ON(cmp_reg(&cp15_regs[i-1], &cp15_regs[i]) >= 0);
1136 /* We abuse the reset function to overwrite the table itself. */
1137 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
1138 invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
1141 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
1143 * If software reads the Cache Type fields from Ctype1
1144 * upwards, once it has seen a value of 0b000, no caches
1145 * exist at further-out levels of the hierarchy. So, for
1146 * example, if Ctype3 is the first Cache Type field with a
1147 * value of 0b000, the values of Ctype4 to Ctype7 must be
1150 asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
1151 for (i = 0; i < 7; i++)
1152 if (((cache_levels >> (i*3)) & 7) == 0)
1154 /* Clear all higher bits. */
1155 cache_levels &= (1 << (i*3))-1;
1159 * kvm_reset_coprocs - sets cp15 registers to reset value
1160 * @vcpu: The VCPU pointer
1162 * This function finds the right table above and sets the registers on the
1163 * virtual CPU struct to their architecturally defined reset values.
1165 void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
1168 const struct coproc_reg *table;
1170 /* Catch someone adding a register without putting in reset entry. */
1171 memset(vcpu->arch.cp15, 0x42, sizeof(vcpu->arch.cp15));
1173 /* Generic chip reset first (so target could override). */
1174 reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
1176 table = get_target_table(vcpu->arch.target, &num);
1177 reset_coproc_regs(vcpu, table, num);
1179 for (num = 1; num < NR_CP15_REGS; num++)
1180 if (vcpu->arch.cp15[num] == 0x42424242)
1181 panic("Didn't reset vcpu->arch.cp15[%zi]", num);