4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/bitmap.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/export.h>
20 #include <linux/perf_event.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/uaccess.h>
24 #include <linux/pm_runtime.h>
26 #include <asm/cputype.h>
28 #include <asm/irq_regs.h>
30 #include <asm/stacktrace.h>
33 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
34 * another platform that supports more, we need to increase this to be the
35 * largest of all platforms.
37 * ARMv7 supports up to 32 events:
38 * cycle counter CCNT + 31 events counters CNT0..30.
39 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
41 #define ARMPMU_MAX_HWEVENTS 32
43 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
44 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
45 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
47 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
49 /* Set at runtime when we know what CPU type we are. */
50 static struct arm_pmu *cpu_pmu;
52 const char *perf_pmu_name(void)
57 return cpu_pmu->pmu.name;
59 EXPORT_SYMBOL_GPL(perf_pmu_name);
61 int perf_num_counters(void)
66 max_events = cpu_pmu->num_events;
70 EXPORT_SYMBOL_GPL(perf_num_counters);
72 #define HW_OP_UNSUPPORTED 0xFFFF
75 PERF_COUNT_HW_CACHE_##_x
77 #define CACHE_OP_UNSUPPORTED 0xFFFF
80 armpmu_map_cache_event(const unsigned (*cache_map)
81 [PERF_COUNT_HW_CACHE_MAX]
82 [PERF_COUNT_HW_CACHE_OP_MAX]
83 [PERF_COUNT_HW_CACHE_RESULT_MAX],
86 unsigned int cache_type, cache_op, cache_result, ret;
88 cache_type = (config >> 0) & 0xff;
89 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
92 cache_op = (config >> 8) & 0xff;
93 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
96 cache_result = (config >> 16) & 0xff;
97 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
100 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
102 if (ret == CACHE_OP_UNSUPPORTED)
109 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
111 int mapping = (*event_map)[config];
112 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
116 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
118 return (int)(config & raw_event_mask);
121 static int map_cpu_event(struct perf_event *event,
122 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
123 const unsigned (*cache_map)
124 [PERF_COUNT_HW_CACHE_MAX]
125 [PERF_COUNT_HW_CACHE_OP_MAX]
126 [PERF_COUNT_HW_CACHE_RESULT_MAX],
129 u64 config = event->attr.config;
131 switch (event->attr.type) {
132 case PERF_TYPE_HARDWARE:
133 return armpmu_map_event(event_map, config);
134 case PERF_TYPE_HW_CACHE:
135 return armpmu_map_cache_event(cache_map, config);
137 return armpmu_map_raw_event(raw_event_mask, config);
144 armpmu_event_set_period(struct perf_event *event,
145 struct hw_perf_event *hwc,
148 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
149 s64 left = local64_read(&hwc->period_left);
150 s64 period = hwc->sample_period;
153 if (unlikely(left <= -period)) {
155 local64_set(&hwc->period_left, left);
156 hwc->last_period = period;
160 if (unlikely(left <= 0)) {
162 local64_set(&hwc->period_left, left);
163 hwc->last_period = period;
167 if (left > (s64)armpmu->max_period)
168 left = armpmu->max_period;
170 local64_set(&hwc->prev_count, (u64)-left);
172 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
174 perf_event_update_userpage(event);
180 armpmu_event_update(struct perf_event *event,
181 struct hw_perf_event *hwc,
184 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
185 u64 delta, prev_raw_count, new_raw_count;
188 prev_raw_count = local64_read(&hwc->prev_count);
189 new_raw_count = armpmu->read_counter(idx);
191 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
192 new_raw_count) != prev_raw_count)
195 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
197 local64_add(delta, &event->count);
198 local64_sub(delta, &hwc->period_left);
200 return new_raw_count;
204 armpmu_read(struct perf_event *event)
206 struct hw_perf_event *hwc = &event->hw;
208 /* Don't read disabled counters! */
212 armpmu_event_update(event, hwc, hwc->idx);
216 armpmu_stop(struct perf_event *event, int flags)
218 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
219 struct hw_perf_event *hwc = &event->hw;
222 * ARM pmu always has to update the counter, so ignore
223 * PERF_EF_UPDATE, see comments in armpmu_start().
225 if (!(hwc->state & PERF_HES_STOPPED)) {
226 armpmu->disable(hwc, hwc->idx);
227 armpmu_event_update(event, hwc, hwc->idx);
228 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
233 armpmu_start(struct perf_event *event, int flags)
235 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
236 struct hw_perf_event *hwc = &event->hw;
239 * ARM pmu always has to reprogram the period, so ignore
240 * PERF_EF_RELOAD, see the comment below.
242 if (flags & PERF_EF_RELOAD)
243 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
247 * Set the period again. Some counters can't be stopped, so when we
248 * were stopped we simply disabled the IRQ source and the counter
249 * may have been left counting. If we don't do this step then we may
250 * get an interrupt too soon or *way* too late if the overflow has
251 * happened since disabling.
253 armpmu_event_set_period(event, hwc, hwc->idx);
254 armpmu->enable(hwc, hwc->idx);
258 armpmu_del(struct perf_event *event, int flags)
260 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
261 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
262 struct hw_perf_event *hwc = &event->hw;
267 armpmu_stop(event, PERF_EF_UPDATE);
268 hw_events->events[idx] = NULL;
269 clear_bit(idx, hw_events->used_mask);
271 perf_event_update_userpage(event);
275 armpmu_add(struct perf_event *event, int flags)
277 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
278 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
279 struct hw_perf_event *hwc = &event->hw;
283 perf_pmu_disable(event->pmu);
285 /* If we don't have a space for the counter then finish early. */
286 idx = armpmu->get_event_idx(hw_events, hwc);
293 * If there is an event in the counter we are going to use then make
294 * sure it is disabled.
297 armpmu->disable(hwc, idx);
298 hw_events->events[idx] = event;
300 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
301 if (flags & PERF_EF_START)
302 armpmu_start(event, PERF_EF_RELOAD);
304 /* Propagate our changes to the userspace mapping. */
305 perf_event_update_userpage(event);
308 perf_pmu_enable(event->pmu);
313 validate_event(struct pmu_hw_events *hw_events,
314 struct perf_event *event)
316 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
317 struct hw_perf_event fake_event = event->hw;
318 struct pmu *leader_pmu = event->group_leader->pmu;
320 if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
323 return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
327 validate_group(struct perf_event *event)
329 struct perf_event *sibling, *leader = event->group_leader;
330 struct pmu_hw_events fake_pmu;
331 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
334 * Initialise the fake PMU. We only need to populate the
335 * used_mask for the purposes of validation.
337 memset(fake_used_mask, 0, sizeof(fake_used_mask));
338 fake_pmu.used_mask = fake_used_mask;
340 if (!validate_event(&fake_pmu, leader))
343 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
344 if (!validate_event(&fake_pmu, sibling))
348 if (!validate_event(&fake_pmu, event))
354 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
356 struct arm_pmu *armpmu = (struct arm_pmu *) dev;
357 struct platform_device *plat_device = armpmu->plat_device;
358 struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
360 return plat->handle_irq(irq, dev, armpmu->handle_irq);
364 armpmu_release_hardware(struct arm_pmu *armpmu)
367 struct platform_device *pmu_device = armpmu->plat_device;
369 irqs = min(pmu_device->num_resources, num_possible_cpus());
371 for (i = 0; i < irqs; ++i) {
372 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
374 irq = platform_get_irq(pmu_device, i);
376 free_irq(irq, armpmu);
379 pm_runtime_put_sync(&pmu_device->dev);
383 armpmu_reserve_hardware(struct arm_pmu *armpmu)
385 struct arm_pmu_platdata *plat;
386 irq_handler_t handle_irq;
387 int i, err, irq, irqs;
388 struct platform_device *pmu_device = armpmu->plat_device;
393 plat = dev_get_platdata(&pmu_device->dev);
394 if (plat && plat->handle_irq)
395 handle_irq = armpmu_platform_irq;
397 handle_irq = armpmu->handle_irq;
399 irqs = min(pmu_device->num_resources, num_possible_cpus());
401 pr_err("no irqs for PMUs defined\n");
405 pm_runtime_get_sync(&pmu_device->dev);
407 for (i = 0; i < irqs; ++i) {
409 irq = platform_get_irq(pmu_device, i);
414 * If we have a single PMU interrupt that we can't shift,
415 * assume that we're running on a uniprocessor machine and
416 * continue. Otherwise, continue without this interrupt.
418 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
419 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
424 err = request_irq(irq, handle_irq,
425 IRQF_DISABLED | IRQF_NOBALANCING,
428 pr_err("unable to request IRQ%d for ARM PMU counters\n",
430 armpmu_release_hardware(armpmu);
434 cpumask_set_cpu(i, &armpmu->active_irqs);
441 hw_perf_event_destroy(struct perf_event *event)
443 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
444 atomic_t *active_events = &armpmu->active_events;
445 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
447 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
448 armpmu_release_hardware(armpmu);
449 mutex_unlock(pmu_reserve_mutex);
454 event_requires_mode_exclusion(struct perf_event_attr *attr)
456 return attr->exclude_idle || attr->exclude_user ||
457 attr->exclude_kernel || attr->exclude_hv;
461 __hw_perf_event_init(struct perf_event *event)
463 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
464 struct hw_perf_event *hwc = &event->hw;
467 mapping = armpmu->map_event(event);
470 pr_debug("event %x:%llx not supported\n", event->attr.type,
476 * We don't assign an index until we actually place the event onto
477 * hardware. Use -1 to signify that we haven't decided where to put it
478 * yet. For SMP systems, each core has it's own PMU so we can't do any
479 * clever allocation or constraints checking at this point.
482 hwc->config_base = 0;
487 * Check whether we need to exclude the counter from certain modes.
489 if ((!armpmu->set_event_filter ||
490 armpmu->set_event_filter(hwc, &event->attr)) &&
491 event_requires_mode_exclusion(&event->attr)) {
492 pr_debug("ARM performance counters do not support "
498 * Store the event encoding into the config_base field.
500 hwc->config_base |= (unsigned long)mapping;
502 if (!hwc->sample_period) {
504 * For non-sampling runs, limit the sample_period to half
505 * of the counter width. That way, the new counter value
506 * is far less likely to overtake the previous one unless
507 * you have some serious IRQ latency issues.
509 hwc->sample_period = armpmu->max_period >> 1;
510 hwc->last_period = hwc->sample_period;
511 local64_set(&hwc->period_left, hwc->sample_period);
515 if (event->group_leader != event) {
516 err = validate_group(event);
524 static int armpmu_event_init(struct perf_event *event)
526 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
528 atomic_t *active_events = &armpmu->active_events;
530 /* does not support taken branch sampling */
531 if (has_branch_stack(event))
534 if (armpmu->map_event(event) == -ENOENT)
537 event->destroy = hw_perf_event_destroy;
539 if (!atomic_inc_not_zero(active_events)) {
540 mutex_lock(&armpmu->reserve_mutex);
541 if (atomic_read(active_events) == 0)
542 err = armpmu_reserve_hardware(armpmu);
545 atomic_inc(active_events);
546 mutex_unlock(&armpmu->reserve_mutex);
552 err = __hw_perf_event_init(event);
554 hw_perf_event_destroy(event);
559 static void armpmu_enable(struct pmu *pmu)
561 struct arm_pmu *armpmu = to_arm_pmu(pmu);
562 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
563 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
569 static void armpmu_disable(struct pmu *pmu)
571 struct arm_pmu *armpmu = to_arm_pmu(pmu);
575 #ifdef CONFIG_PM_RUNTIME
576 static int armpmu_runtime_resume(struct device *dev)
578 struct arm_pmu_platdata *plat = dev_get_platdata(dev);
580 if (plat && plat->runtime_resume)
581 return plat->runtime_resume(dev);
586 static int armpmu_runtime_suspend(struct device *dev)
588 struct arm_pmu_platdata *plat = dev_get_platdata(dev);
590 if (plat && plat->runtime_suspend)
591 return plat->runtime_suspend(dev);
597 static void __init armpmu_init(struct arm_pmu *armpmu)
599 atomic_set(&armpmu->active_events, 0);
600 mutex_init(&armpmu->reserve_mutex);
602 armpmu->pmu = (struct pmu) {
603 .pmu_enable = armpmu_enable,
604 .pmu_disable = armpmu_disable,
605 .event_init = armpmu_event_init,
608 .start = armpmu_start,
614 int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
617 pr_info("enabled with %s PMU driver, %d counters available\n",
618 armpmu->name, armpmu->num_events);
619 return perf_pmu_register(&armpmu->pmu, name, type);
622 /* Include the PMU-specific implementations. */
623 #include "perf_event_xscale.c"
624 #include "perf_event_v6.c"
625 #include "perf_event_v7.c"
627 static struct pmu_hw_events *armpmu_get_cpu_events(void)
629 return &__get_cpu_var(cpu_hw_events);
632 static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
635 for_each_possible_cpu(cpu) {
636 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
637 events->events = per_cpu(hw_events, cpu);
638 events->used_mask = per_cpu(used_mask, cpu);
639 raw_spin_lock_init(&events->pmu_lock);
641 cpu_pmu->get_hw_events = armpmu_get_cpu_events;
643 /* Ensure the PMU has sane values out of reset. */
644 if (cpu_pmu && cpu_pmu->reset)
645 on_each_cpu(cpu_pmu->reset, NULL, 1);
649 * PMU hardware loses all context when a CPU goes offline.
650 * When a CPU is hotplugged back in, since some hardware registers are
651 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
652 * junk values out of them.
654 static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
655 unsigned long action, void *hcpu)
657 if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
660 if (cpu_pmu && cpu_pmu->reset)
661 cpu_pmu->reset(NULL);
666 static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
667 .notifier_call = pmu_cpu_notify,
670 static const struct dev_pm_ops armpmu_dev_pm_ops = {
671 SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
675 * PMU platform driver and devicetree bindings.
677 static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
678 {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
679 {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
680 {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
681 {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
682 {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
683 {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
684 {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init},
685 {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init},
689 static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
695 * CPU PMU identification and probing.
697 static struct arm_pmu *__devinit probe_current_pmu(void)
699 struct arm_pmu *pmu = NULL;
701 unsigned long cpuid = read_cpuid_id();
702 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
703 unsigned long part_number = (cpuid & 0xFFF0);
705 pr_info("probing PMU on CPU %d\n", cpu);
708 if (0x41 == implementor) {
709 switch (part_number) {
710 case 0xB360: /* ARM1136 */
711 case 0xB560: /* ARM1156 */
712 case 0xB760: /* ARM1176 */
713 pmu = armv6pmu_init();
715 case 0xB020: /* ARM11mpcore */
716 pmu = armv6mpcore_pmu_init();
718 case 0xC080: /* Cortex-A8 */
719 pmu = armv7_a8_pmu_init();
721 case 0xC090: /* Cortex-A9 */
722 pmu = armv7_a9_pmu_init();
724 case 0xC050: /* Cortex-A5 */
725 pmu = armv7_a5_pmu_init();
727 case 0xC0F0: /* Cortex-A15 */
728 pmu = armv7_a15_pmu_init();
730 case 0xC070: /* Cortex-A7 */
731 pmu = armv7_a7_pmu_init();
734 /* Intel CPUs [xscale]. */
735 } else if (0x69 == implementor) {
736 part_number = (cpuid >> 13) & 0x7;
737 switch (part_number) {
739 pmu = xscale1pmu_init();
742 pmu = xscale2pmu_init();
751 static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
753 const struct of_device_id *of_id;
754 struct arm_pmu *(*init_fn)(void);
755 struct device_node *node = pdev->dev.of_node;
758 pr_info("attempt to register multiple PMU devices!");
762 if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
763 init_fn = of_id->data;
766 cpu_pmu = probe_current_pmu();
772 cpu_pmu->plat_device = pdev;
773 cpu_pmu_init(cpu_pmu);
774 register_cpu_notifier(&pmu_cpu_notifier);
775 armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
780 static struct platform_driver cpu_pmu_driver = {
783 .pm = &armpmu_dev_pm_ops,
784 .of_match_table = cpu_pmu_of_device_ids,
786 .probe = cpu_pmu_device_probe,
787 .id_table = cpu_pmu_plat_device_ids,
790 static int __init register_pmu_driver(void)
792 return platform_driver_register(&cpu_pmu_driver);
794 device_initcall(register_pmu_driver);
797 * Callchain handling code.
801 * The registers we're interested in are at the end of the variable
802 * length saved register structure. The fp points at the end of this
803 * structure so the address of this struct is:
804 * (struct frame_tail *)(xxx->fp)-1
806 * This code has been adapted from the ARM OProfile support.
809 struct frame_tail __user *fp;
812 } __attribute__((packed));
815 * Get the return address for a single stackframe and return a pointer to the
818 static struct frame_tail __user *
819 user_backtrace(struct frame_tail __user *tail,
820 struct perf_callchain_entry *entry)
822 struct frame_tail buftail;
824 /* Also check accessibility of one struct frame_tail beyond */
825 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
827 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
830 perf_callchain_store(entry, buftail.lr);
833 * Frame pointers should strictly progress back up the stack
834 * (towards higher addresses).
836 if (tail + 1 >= buftail.fp)
839 return buftail.fp - 1;
843 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
845 struct frame_tail __user *tail;
848 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
850 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
851 tail && !((unsigned long)tail & 0x3))
852 tail = user_backtrace(tail, entry);
856 * Gets called by walk_stackframe() for every stackframe. This will be called
857 * whist unwinding the stackframe and is like a subroutine return so we use
861 callchain_trace(struct stackframe *fr,
864 struct perf_callchain_entry *entry = data;
865 perf_callchain_store(entry, fr->pc);
870 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
872 struct stackframe fr;
874 fr.fp = regs->ARM_fp;
875 fr.sp = regs->ARM_sp;
876 fr.lr = regs->ARM_lr;
877 fr.pc = regs->ARM_pc;
878 walk_stackframe(&fr, callchain_trace, entry);