2 * arch/arm/kernel/kprobes-thumb.c
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/kprobes.h>
18 * True if current instruction is in an IT block.
20 #define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000)
23 * Return the condition code to check for the currently executing instruction.
24 * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
25 * in_it_block returns true.
27 #define current_cond(cpsr) ((cpsr >> 12) & 0xf)
30 * Return the PC value for a probe in thumb code.
31 * This is the address of the probed instruction plus 4.
32 * We subtract one because the address will have bit zero set to indicate
33 * a pointer to thumb code.
35 static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p)
37 return (unsigned long)p->addr - 1 + 4;
41 t32_simulate_table_branch(struct kprobe *p, struct pt_regs *regs)
43 kprobe_opcode_t insn = p->opcode;
44 unsigned long pc = thumb_probe_pc(p);
45 int rn = (insn >> 16) & 0xf;
48 unsigned long rnv = (rn == 15) ? pc : regs->uregs[rn];
49 unsigned long rmv = regs->uregs[rm];
50 unsigned int halfwords;
52 if (insn & 0x10) /* TBH */
53 halfwords = ((u16 *)rnv)[rmv];
55 halfwords = ((u8 *)rnv)[rmv];
57 regs->ARM_pc = pc + 2 * halfwords;
61 t32_simulate_mrs(struct kprobe *p, struct pt_regs *regs)
63 kprobe_opcode_t insn = p->opcode;
64 int rd = (insn >> 8) & 0xf;
65 unsigned long mask = 0xf8ff03df; /* Mask out execution state */
66 regs->uregs[rd] = regs->ARM_cpsr & mask;
70 t32_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
72 kprobe_opcode_t insn = p->opcode;
73 unsigned long pc = thumb_probe_pc(p);
75 long offset = insn & 0x7ff; /* imm11 */
76 offset += (insn & 0x003f0000) >> 5; /* imm6 */
77 offset += (insn & 0x00002000) << 4; /* J1 */
78 offset += (insn & 0x00000800) << 7; /* J2 */
79 offset -= (insn & 0x04000000) >> 7; /* Apply sign bit */
81 regs->ARM_pc = pc + (offset * 2);
84 static enum kprobe_insn __kprobes
85 t32_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
87 int cc = (insn >> 22) & 0xf;
88 asi->insn_check_cc = kprobe_condition_checks[cc];
89 asi->insn_handler = t32_simulate_cond_branch;
90 return INSN_GOOD_NO_SLOT;
94 t32_simulate_branch(struct kprobe *p, struct pt_regs *regs)
96 kprobe_opcode_t insn = p->opcode;
97 unsigned long pc = thumb_probe_pc(p);
99 long offset = insn & 0x7ff; /* imm11 */
100 offset += (insn & 0x03ff0000) >> 5; /* imm10 */
101 offset += (insn & 0x00002000) << 9; /* J1 */
102 offset += (insn & 0x00000800) << 10; /* J2 */
103 if (insn & 0x04000000)
104 offset -= 0x00800000; /* Apply sign bit */
106 offset ^= 0x00600000; /* Invert J1 and J2 */
108 if (insn & (1 << 14)) {
110 regs->ARM_lr = (unsigned long)p->addr + 4;
111 if (!(insn & (1 << 12))) {
112 /* BLX so switch to ARM mode */
113 regs->ARM_cpsr &= ~PSR_T_BIT;
118 regs->ARM_pc = pc + (offset * 2);
121 static enum kprobe_insn __kprobes
122 t32_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
124 enum kprobe_insn ret = kprobe_decode_ldmstm(insn, asi);
126 /* Fixup modified instruction to have halfwords in correct order...*/
128 ((u16 *)asi->insn)[0] = insn >> 16;
129 ((u16 *)asi->insn)[1] = insn & 0xffff;
134 static void __kprobes
135 t32_emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
137 kprobe_opcode_t insn = p->opcode;
138 unsigned long pc = thumb_probe_pc(p) & ~3;
139 int rt1 = (insn >> 12) & 0xf;
140 int rt2 = (insn >> 8) & 0xf;
141 int rn = (insn >> 16) & 0xf;
143 register unsigned long rt1v asm("r0") = regs->uregs[rt1];
144 register unsigned long rt2v asm("r1") = regs->uregs[rt2];
145 register unsigned long rnv asm("r2") = (rn == 15) ? pc
148 __asm__ __volatile__ (
150 : "=r" (rt1v), "=r" (rt2v), "=r" (rnv)
151 : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (p->ainsn.insn_fn)
152 : "lr", "memory", "cc"
156 regs->uregs[rn] = rnv; /* Writeback base register */
157 regs->uregs[rt1] = rt1v;
158 regs->uregs[rt2] = rt2v;
161 static void __kprobes
162 t32_emulate_rd8rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
164 kprobe_opcode_t insn = p->opcode;
165 int rd = (insn >> 8) & 0xf;
166 int rn = (insn >> 16) & 0xf;
169 register unsigned long rdv asm("r1") = regs->uregs[rd];
170 register unsigned long rnv asm("r2") = regs->uregs[rn];
171 register unsigned long rmv asm("r3") = regs->uregs[rm];
172 unsigned long cpsr = regs->ARM_cpsr;
174 __asm__ __volatile__ (
175 "msr cpsr_fs, %[cpsr] \n\t"
177 "mrs %[cpsr], cpsr \n\t"
178 : "=r" (rdv), [cpsr] "=r" (cpsr)
179 : "0" (rdv), "r" (rnv), "r" (rmv),
180 "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
181 : "lr", "memory", "cc"
184 regs->uregs[rd] = rdv;
185 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
188 static void __kprobes
189 t32_emulate_rd8pc16_noflags(struct kprobe *p, struct pt_regs *regs)
191 kprobe_opcode_t insn = p->opcode;
192 unsigned long pc = thumb_probe_pc(p);
193 int rd = (insn >> 8) & 0xf;
195 register unsigned long rdv asm("r1") = regs->uregs[rd];
196 register unsigned long rnv asm("r2") = pc & ~3;
198 __asm__ __volatile__ (
201 : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
202 : "lr", "memory", "cc"
205 regs->uregs[rd] = rdv;
208 static void __kprobes
209 t32_emulate_rd8rn16_noflags(struct kprobe *p, struct pt_regs *regs)
211 kprobe_opcode_t insn = p->opcode;
212 int rd = (insn >> 8) & 0xf;
213 int rn = (insn >> 16) & 0xf;
215 register unsigned long rdv asm("r1") = regs->uregs[rd];
216 register unsigned long rnv asm("r2") = regs->uregs[rn];
218 __asm__ __volatile__ (
221 : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
222 : "lr", "memory", "cc"
225 regs->uregs[rd] = rdv;
228 static const union decode_item t32_table_1110_100x_x0xx[] = {
229 /* Load/store multiple instructions */
231 /* Rn is PC 1110 100x x0xx 1111 xxxx xxxx xxxx xxxx */
232 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
234 /* SRS 1110 1000 00x0 xxxx xxxx xxxx xxxx xxxx */
235 /* RFE 1110 1000 00x1 xxxx xxxx xxxx xxxx xxxx */
236 DECODE_REJECT (0xffc00000, 0xe8000000),
237 /* SRS 1110 1001 10x0 xxxx xxxx xxxx xxxx xxxx */
238 /* RFE 1110 1001 10x1 xxxx xxxx xxxx xxxx xxxx */
239 DECODE_REJECT (0xffc00000, 0xe9800000),
241 /* STM Rn, {...pc} 1110 100x x0x0 xxxx 1xxx xxxx xxxx xxxx */
242 DECODE_REJECT (0xfe508000, 0xe8008000),
243 /* LDM Rn, {...lr,pc} 1110 100x x0x1 xxxx 11xx xxxx xxxx xxxx */
244 DECODE_REJECT (0xfe50c000, 0xe810c000),
245 /* LDM/STM Rn, {...sp} 1110 100x x0xx xxxx xx1x xxxx xxxx xxxx */
246 DECODE_REJECT (0xfe402000, 0xe8002000),
248 /* STMIA 1110 1000 10x0 xxxx xxxx xxxx xxxx xxxx */
249 /* LDMIA 1110 1000 10x1 xxxx xxxx xxxx xxxx xxxx */
250 /* STMDB 1110 1001 00x0 xxxx xxxx xxxx xxxx xxxx */
251 /* LDMDB 1110 1001 00x1 xxxx xxxx xxxx xxxx xxxx */
252 DECODE_CUSTOM (0xfe400000, 0xe8000000, t32_decode_ldmstm),
257 static const union decode_item t32_table_1110_100x_x1xx[] = {
258 /* Load/store dual, load/store exclusive, table branch */
260 /* STRD (immediate) 1110 1000 x110 xxxx xxxx xxxx xxxx xxxx */
261 /* LDRD (immediate) 1110 1000 x111 xxxx xxxx xxxx xxxx xxxx */
262 DECODE_OR (0xff600000, 0xe8600000),
263 /* STRD (immediate) 1110 1001 x1x0 xxxx xxxx xxxx xxxx xxxx */
264 /* LDRD (immediate) 1110 1001 x1x1 xxxx xxxx xxxx xxxx xxxx */
265 DECODE_EMULATEX (0xff400000, 0xe9400000, t32_emulate_ldrdstrd,
266 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
268 /* TBB 1110 1000 1101 xxxx xxxx xxxx 0000 xxxx */
269 /* TBH 1110 1000 1101 xxxx xxxx xxxx 0001 xxxx */
270 DECODE_SIMULATEX(0xfff000e0, 0xe8d00000, t32_simulate_table_branch,
271 REGS(NOSP, 0, 0, 0, NOSPPC)),
273 /* STREX 1110 1000 0100 xxxx xxxx xxxx xxxx xxxx */
274 /* LDREX 1110 1000 0101 xxxx xxxx xxxx xxxx xxxx */
275 /* STREXB 1110 1000 1100 xxxx xxxx xxxx 0100 xxxx */
276 /* STREXH 1110 1000 1100 xxxx xxxx xxxx 0101 xxxx */
277 /* STREXD 1110 1000 1100 xxxx xxxx xxxx 0111 xxxx */
278 /* LDREXB 1110 1000 1101 xxxx xxxx xxxx 0100 xxxx */
279 /* LDREXH 1110 1000 1101 xxxx xxxx xxxx 0101 xxxx */
280 /* LDREXD 1110 1000 1101 xxxx xxxx xxxx 0111 xxxx */
281 /* And unallocated instructions... */
285 static const union decode_item t32_table_1110_101x[] = {
286 /* Data-processing (shifted register) */
288 /* TST 1110 1010 0001 xxxx xxxx 1111 xxxx xxxx */
289 /* TEQ 1110 1010 1001 xxxx xxxx 1111 xxxx xxxx */
290 DECODE_EMULATEX (0xff700f00, 0xea100f00, t32_emulate_rd8rn16rm0_rwflags,
291 REGS(NOSPPC, 0, 0, 0, NOSPPC)),
293 /* CMN 1110 1011 0001 xxxx xxxx 1111 xxxx xxxx */
294 DECODE_OR (0xfff00f00, 0xeb100f00),
295 /* CMP 1110 1011 1011 xxxx xxxx 1111 xxxx xxxx */
296 DECODE_EMULATEX (0xfff00f00, 0xebb00f00, t32_emulate_rd8rn16rm0_rwflags,
297 REGS(NOPC, 0, 0, 0, NOSPPC)),
299 /* MOV 1110 1010 010x 1111 xxxx xxxx xxxx xxxx */
300 /* MVN 1110 1010 011x 1111 xxxx xxxx xxxx xxxx */
301 DECODE_EMULATEX (0xffcf0000, 0xea4f0000, t32_emulate_rd8rn16rm0_rwflags,
302 REGS(0, 0, NOSPPC, 0, NOSPPC)),
304 /* ??? 1110 1010 101x xxxx xxxx xxxx xxxx xxxx */
305 /* ??? 1110 1010 111x xxxx xxxx xxxx xxxx xxxx */
306 DECODE_REJECT (0xffa00000, 0xeaa00000),
307 /* ??? 1110 1011 001x xxxx xxxx xxxx xxxx xxxx */
308 DECODE_REJECT (0xffe00000, 0xeb200000),
309 /* ??? 1110 1011 100x xxxx xxxx xxxx xxxx xxxx */
310 DECODE_REJECT (0xffe00000, 0xeb800000),
311 /* ??? 1110 1011 111x xxxx xxxx xxxx xxxx xxxx */
312 DECODE_REJECT (0xffe00000, 0xebe00000),
314 /* ADD/SUB SP, SP, Rm, LSL #0..3 */
315 /* 1110 1011 x0xx 1101 x000 1101 xx00 xxxx */
316 DECODE_EMULATEX (0xff4f7f30, 0xeb0d0d00, t32_emulate_rd8rn16rm0_rwflags,
317 REGS(SP, 0, SP, 0, NOSPPC)),
319 /* ADD/SUB SP, SP, Rm, shift */
320 /* 1110 1011 x0xx 1101 xxxx 1101 xxxx xxxx */
321 DECODE_REJECT (0xff4f0f00, 0xeb0d0d00),
323 /* ADD/SUB Rd, SP, Rm, shift */
324 /* 1110 1011 x0xx 1101 xxxx xxxx xxxx xxxx */
325 DECODE_EMULATEX (0xff4f0000, 0xeb0d0000, t32_emulate_rd8rn16rm0_rwflags,
326 REGS(SP, 0, NOPC, 0, NOSPPC)),
328 /* AND 1110 1010 000x xxxx xxxx xxxx xxxx xxxx */
329 /* BIC 1110 1010 001x xxxx xxxx xxxx xxxx xxxx */
330 /* ORR 1110 1010 010x xxxx xxxx xxxx xxxx xxxx */
331 /* ORN 1110 1010 011x xxxx xxxx xxxx xxxx xxxx */
332 /* EOR 1110 1010 100x xxxx xxxx xxxx xxxx xxxx */
333 /* PKH 1110 1010 110x xxxx xxxx xxxx xxxx xxxx */
334 /* ADD 1110 1011 000x xxxx xxxx xxxx xxxx xxxx */
335 /* ADC 1110 1011 010x xxxx xxxx xxxx xxxx xxxx */
336 /* SBC 1110 1011 011x xxxx xxxx xxxx xxxx xxxx */
337 /* SUB 1110 1011 101x xxxx xxxx xxxx xxxx xxxx */
338 /* RSB 1110 1011 110x xxxx xxxx xxxx xxxx xxxx */
339 DECODE_EMULATEX (0xfe000000, 0xea000000, t32_emulate_rd8rn16rm0_rwflags,
340 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
345 static const union decode_item t32_table_1111_0x0x___0[] = {
346 /* Data-processing (modified immediate) */
348 /* TST 1111 0x00 0001 xxxx 0xxx 1111 xxxx xxxx */
349 /* TEQ 1111 0x00 1001 xxxx 0xxx 1111 xxxx xxxx */
350 DECODE_EMULATEX (0xfb708f00, 0xf0100f00, t32_emulate_rd8rn16rm0_rwflags,
351 REGS(NOSPPC, 0, 0, 0, 0)),
353 /* CMN 1111 0x01 0001 xxxx 0xxx 1111 xxxx xxxx */
354 DECODE_OR (0xfbf08f00, 0xf1100f00),
355 /* CMP 1111 0x01 1011 xxxx 0xxx 1111 xxxx xxxx */
356 DECODE_EMULATEX (0xfbf08f00, 0xf1b00f00, t32_emulate_rd8rn16rm0_rwflags,
357 REGS(NOPC, 0, 0, 0, 0)),
359 /* MOV 1111 0x00 010x 1111 0xxx xxxx xxxx xxxx */
360 /* MVN 1111 0x00 011x 1111 0xxx xxxx xxxx xxxx */
361 DECODE_EMULATEX (0xfbcf8000, 0xf04f0000, t32_emulate_rd8rn16rm0_rwflags,
362 REGS(0, 0, NOSPPC, 0, 0)),
364 /* ??? 1111 0x00 101x xxxx 0xxx xxxx xxxx xxxx */
365 DECODE_REJECT (0xfbe08000, 0xf0a00000),
366 /* ??? 1111 0x00 110x xxxx 0xxx xxxx xxxx xxxx */
367 /* ??? 1111 0x00 111x xxxx 0xxx xxxx xxxx xxxx */
368 DECODE_REJECT (0xfbc08000, 0xf0c00000),
369 /* ??? 1111 0x01 001x xxxx 0xxx xxxx xxxx xxxx */
370 DECODE_REJECT (0xfbe08000, 0xf1200000),
371 /* ??? 1111 0x01 100x xxxx 0xxx xxxx xxxx xxxx */
372 DECODE_REJECT (0xfbe08000, 0xf1800000),
373 /* ??? 1111 0x01 111x xxxx 0xxx xxxx xxxx xxxx */
374 DECODE_REJECT (0xfbe08000, 0xf1e00000),
376 /* ADD Rd, SP, #imm 1111 0x01 000x 1101 0xxx xxxx xxxx xxxx */
377 /* SUB Rd, SP, #imm 1111 0x01 101x 1101 0xxx xxxx xxxx xxxx */
378 DECODE_EMULATEX (0xfb4f8000, 0xf10d0000, t32_emulate_rd8rn16rm0_rwflags,
379 REGS(SP, 0, NOPC, 0, 0)),
381 /* AND 1111 0x00 000x xxxx 0xxx xxxx xxxx xxxx */
382 /* BIC 1111 0x00 001x xxxx 0xxx xxxx xxxx xxxx */
383 /* ORR 1111 0x00 010x xxxx 0xxx xxxx xxxx xxxx */
384 /* ORN 1111 0x00 011x xxxx 0xxx xxxx xxxx xxxx */
385 /* EOR 1111 0x00 100x xxxx 0xxx xxxx xxxx xxxx */
386 /* ADD 1111 0x01 000x xxxx 0xxx xxxx xxxx xxxx */
387 /* ADC 1111 0x01 010x xxxx 0xxx xxxx xxxx xxxx */
388 /* SBC 1111 0x01 011x xxxx 0xxx xxxx xxxx xxxx */
389 /* SUB 1111 0x01 101x xxxx 0xxx xxxx xxxx xxxx */
390 /* RSB 1111 0x01 110x xxxx 0xxx xxxx xxxx xxxx */
391 DECODE_EMULATEX (0xfa008000, 0xf0000000, t32_emulate_rd8rn16rm0_rwflags,
392 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
397 static const union decode_item t32_table_1111_0x1x___0[] = {
398 /* Data-processing (plain binary immediate) */
400 /* ADDW Rd, PC, #imm 1111 0x10 0000 1111 0xxx xxxx xxxx xxxx */
401 DECODE_OR (0xfbff8000, 0xf20f0000),
402 /* SUBW Rd, PC, #imm 1111 0x10 1010 1111 0xxx xxxx xxxx xxxx */
403 DECODE_EMULATEX (0xfbff8000, 0xf2af0000, t32_emulate_rd8pc16_noflags,
404 REGS(PC, 0, NOSPPC, 0, 0)),
406 /* ADDW SP, SP, #imm 1111 0x10 0000 1101 0xxx 1101 xxxx xxxx */
407 DECODE_OR (0xfbff8f00, 0xf20d0d00),
408 /* SUBW SP, SP, #imm 1111 0x10 1010 1101 0xxx 1101 xxxx xxxx */
409 DECODE_EMULATEX (0xfbff8f00, 0xf2ad0d00, t32_emulate_rd8rn16_noflags,
410 REGS(SP, 0, SP, 0, 0)),
412 /* ADDW 1111 0x10 0000 xxxx 0xxx xxxx xxxx xxxx */
413 DECODE_OR (0xfbf08000, 0xf2000000),
414 /* SUBW 1111 0x10 1010 xxxx 0xxx xxxx xxxx xxxx */
415 DECODE_EMULATEX (0xfbf08000, 0xf2a00000, t32_emulate_rd8rn16_noflags,
416 REGS(NOPCX, 0, NOSPPC, 0, 0)),
418 /* MOVW 1111 0x10 0100 xxxx 0xxx xxxx xxxx xxxx */
419 /* MOVT 1111 0x10 1100 xxxx 0xxx xxxx xxxx xxxx */
420 DECODE_EMULATEX (0xfb708000, 0xf2400000, t32_emulate_rd8rn16_noflags,
421 REGS(0, 0, NOSPPC, 0, 0)),
423 /* SSAT16 1111 0x11 0010 xxxx 0000 xxxx 00xx xxxx */
424 /* SSAT 1111 0x11 00x0 xxxx 0xxx xxxx xxxx xxxx */
425 /* USAT16 1111 0x11 1010 xxxx 0000 xxxx 00xx xxxx */
426 /* USAT 1111 0x11 10x0 xxxx 0xxx xxxx xxxx xxxx */
427 DECODE_EMULATEX (0xfb508000, 0xf3000000, t32_emulate_rd8rn16rm0_rwflags,
428 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
430 /* SFBX 1111 0x11 0100 xxxx 0xxx xxxx xxxx xxxx */
431 /* UFBX 1111 0x11 1100 xxxx 0xxx xxxx xxxx xxxx */
432 DECODE_EMULATEX (0xfb708000, 0xf3400000, t32_emulate_rd8rn16_noflags,
433 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
435 /* BFC 1111 0x11 0110 1111 0xxx xxxx xxxx xxxx */
436 DECODE_EMULATEX (0xfbff8000, 0xf36f0000, t32_emulate_rd8rn16_noflags,
437 REGS(0, 0, NOSPPC, 0, 0)),
439 /* BFI 1111 0x11 0110 xxxx 0xxx xxxx xxxx xxxx */
440 DECODE_EMULATEX (0xfbf08000, 0xf3600000, t32_emulate_rd8rn16_noflags,
441 REGS(NOSPPCX, 0, NOSPPC, 0, 0)),
446 static const union decode_item t32_table_1111_0xxx___1[] = {
447 /* Branches and miscellaneous control */
449 /* YIELD 1111 0011 1010 xxxx 10x0 x000 0000 0001 */
450 DECODE_OR (0xfff0d7ff, 0xf3a08001),
451 /* SEV 1111 0011 1010 xxxx 10x0 x000 0000 0100 */
452 DECODE_EMULATE (0xfff0d7ff, 0xf3a08004, kprobe_emulate_none),
453 /* NOP 1111 0011 1010 xxxx 10x0 x000 0000 0000 */
454 /* WFE 1111 0011 1010 xxxx 10x0 x000 0000 0010 */
455 /* WFI 1111 0011 1010 xxxx 10x0 x000 0000 0011 */
456 DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, kprobe_simulate_nop),
458 /* MRS Rd, CPSR 1111 0011 1110 xxxx 10x0 xxxx xxxx xxxx */
459 DECODE_SIMULATEX(0xfff0d000, 0xf3e08000, t32_simulate_mrs,
460 REGS(0, 0, NOSPPC, 0, 0)),
463 * Unsupported instructions
464 * 1111 0x11 1xxx xxxx 10x0 xxxx xxxx xxxx
466 * MSR 1111 0011 100x xxxx 10x0 xxxx xxxx xxxx
467 * DBG hint 1111 0011 1010 xxxx 10x0 x000 1111 xxxx
468 * Unallocated hints 1111 0011 1010 xxxx 10x0 x000 xxxx xxxx
469 * CPS 1111 0011 1010 xxxx 10x0 xxxx xxxx xxxx
470 * CLREX/DSB/DMB/ISB 1111 0011 1011 xxxx 10x0 xxxx xxxx xxxx
471 * BXJ 1111 0011 1100 xxxx 10x0 xxxx xxxx xxxx
472 * SUBS PC,LR,#<imm8> 1111 0011 1101 xxxx 10x0 xxxx xxxx xxxx
473 * MRS Rd, SPSR 1111 0011 1111 xxxx 10x0 xxxx xxxx xxxx
474 * SMC 1111 0111 1111 xxxx 1000 xxxx xxxx xxxx
475 * UNDEFINED 1111 0111 1111 xxxx 1010 xxxx xxxx xxxx
476 * ??? 1111 0111 1xxx xxxx 1010 xxxx xxxx xxxx
478 DECODE_REJECT (0xfb80d000, 0xf3808000),
480 /* Bcc 1111 0xxx xxxx xxxx 10x0 xxxx xxxx xxxx */
481 DECODE_CUSTOM (0xf800d000, 0xf0008000, t32_decode_cond_branch),
483 /* BLX 1111 0xxx xxxx xxxx 11x0 xxxx xxxx xxx0 */
484 DECODE_OR (0xf800d001, 0xf000c000),
485 /* B 1111 0xxx xxxx xxxx 10x1 xxxx xxxx xxxx */
486 /* BL 1111 0xxx xxxx xxxx 11x1 xxxx xxxx xxxx */
487 DECODE_SIMULATE (0xf8009000, 0xf0009000, t32_simulate_branch),
492 const union decode_item kprobe_decode_thumb32_table[] = {
495 * Load/store multiple instructions
496 * 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx
498 DECODE_TABLE (0xfe400000, 0xe8000000, t32_table_1110_100x_x0xx),
501 * Load/store dual, load/store exclusive, table branch
502 * 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx
504 DECODE_TABLE (0xfe400000, 0xe8400000, t32_table_1110_100x_x1xx),
507 * Data-processing (shifted register)
508 * 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx
510 DECODE_TABLE (0xfe000000, 0xea000000, t32_table_1110_101x),
513 * Data-processing (modified immediate)
514 * 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx
516 DECODE_TABLE (0xfa008000, 0xf0000000, t32_table_1111_0x0x___0),
519 * Data-processing (plain binary immediate)
520 * 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx
522 DECODE_TABLE (0xfa008000, 0xf2000000, t32_table_1111_0x1x___0),
525 * Branches and miscellaneous control
526 * 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx
528 DECODE_TABLE (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1),
533 static void __kprobes
534 t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
536 kprobe_opcode_t insn = p->opcode;
537 unsigned long pc = thumb_probe_pc(p);
538 int rm = (insn >> 3) & 0xf;
539 unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];
541 if (insn & (1 << 7)) /* BLX ? */
542 regs->ARM_lr = (unsigned long)p->addr + 2;
544 bx_write_pc(rmv, regs);
547 static void __kprobes
548 t16_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
550 kprobe_opcode_t insn = p->opcode;
551 unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3);
552 long index = insn & 0xff;
553 int rt = (insn >> 8) & 0x7;
554 regs->uregs[rt] = base[index];
557 static void __kprobes
558 t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs)
560 kprobe_opcode_t insn = p->opcode;
561 unsigned long* base = (unsigned long *)regs->ARM_sp;
562 long index = insn & 0xff;
563 int rt = (insn >> 8) & 0x7;
564 if (insn & 0x800) /* LDR */
565 regs->uregs[rt] = base[index];
567 base[index] = regs->uregs[rt];
570 static void __kprobes
571 t16_simulate_reladr(struct kprobe *p, struct pt_regs *regs)
573 kprobe_opcode_t insn = p->opcode;
574 unsigned long base = (insn & 0x800) ? regs->ARM_sp
575 : (thumb_probe_pc(p) & ~3);
576 long offset = insn & 0xff;
577 int rt = (insn >> 8) & 0x7;
578 regs->uregs[rt] = base + offset * 4;
581 static void __kprobes
582 t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs)
584 kprobe_opcode_t insn = p->opcode;
585 long imm = insn & 0x7f;
586 if (insn & 0x80) /* SUB */
587 regs->ARM_sp -= imm * 4;
589 regs->ARM_sp += imm * 4;
592 static void __kprobes
593 t16_simulate_cbz(struct kprobe *p, struct pt_regs *regs)
595 kprobe_opcode_t insn = p->opcode;
597 kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
598 if (nonzero & 0x800) {
599 long i = insn & 0x200;
600 long imm5 = insn & 0xf8;
601 unsigned long pc = thumb_probe_pc(p);
602 regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
606 static void __kprobes
607 t16_simulate_it(struct kprobe *p, struct pt_regs *regs)
610 * The 8 IT state bits are split into two parts in CPSR:
611 * ITSTATE<1:0> are in CPSR<26:25>
612 * ITSTATE<7:2> are in CPSR<15:10>
613 * The new IT state is in the lower byte of insn.
615 kprobe_opcode_t insn = p->opcode;
616 unsigned long cpsr = regs->ARM_cpsr;
617 cpsr &= ~PSR_IT_MASK;
618 cpsr |= (insn & 0xfc) << 8;
619 cpsr |= (insn & 0x03) << 25;
620 regs->ARM_cpsr = cpsr;
623 static void __kprobes
624 t16_singlestep_it(struct kprobe *p, struct pt_regs *regs)
627 t16_simulate_it(p, regs);
630 static enum kprobe_insn __kprobes
631 t16_decode_it(kprobe_opcode_t insn, struct arch_specific_insn *asi)
633 asi->insn_singlestep = t16_singlestep_it;
634 return INSN_GOOD_NO_SLOT;
637 static void __kprobes
638 t16_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
640 kprobe_opcode_t insn = p->opcode;
641 unsigned long pc = thumb_probe_pc(p);
642 long offset = insn & 0x7f;
643 offset -= insn & 0x80; /* Apply sign bit */
644 regs->ARM_pc = pc + (offset * 2);
647 static enum kprobe_insn __kprobes
648 t16_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
650 int cc = (insn >> 8) & 0xf;
651 asi->insn_check_cc = kprobe_condition_checks[cc];
652 asi->insn_handler = t16_simulate_cond_branch;
653 return INSN_GOOD_NO_SLOT;
656 static void __kprobes
657 t16_simulate_branch(struct kprobe *p, struct pt_regs *regs)
659 kprobe_opcode_t insn = p->opcode;
660 unsigned long pc = thumb_probe_pc(p);
661 long offset = insn & 0x3ff;
662 offset -= insn & 0x400; /* Apply sign bit */
663 regs->ARM_pc = pc + (offset * 2);
666 static unsigned long __kprobes
667 t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
669 unsigned long oldcpsr = regs->ARM_cpsr;
670 unsigned long newcpsr;
672 __asm__ __volatile__ (
673 "msr cpsr_fs, %[oldcpsr] \n\t"
674 "ldmia %[regs], {r0-r7} \n\t"
676 "stmia %[regs], {r0-r7} \n\t"
677 "mrs %[newcpsr], cpsr \n\t"
678 : [newcpsr] "=r" (newcpsr)
679 : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
680 [fn] "r" (p->ainsn.insn_fn)
681 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
685 return (oldcpsr & ~APSR_MASK) | (newcpsr & APSR_MASK);
688 static void __kprobes
689 t16_emulate_loregs_rwflags(struct kprobe *p, struct pt_regs *regs)
691 regs->ARM_cpsr = t16_emulate_loregs(p, regs);
694 static void __kprobes
695 t16_emulate_loregs_noitrwflags(struct kprobe *p, struct pt_regs *regs)
697 unsigned long cpsr = t16_emulate_loregs(p, regs);
698 if (!in_it_block(cpsr))
699 regs->ARM_cpsr = cpsr;
702 static void __kprobes
703 t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
705 kprobe_opcode_t insn = p->opcode;
706 unsigned long pc = thumb_probe_pc(p);
707 int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
708 int rm = (insn >> 3) & 0xf;
710 register unsigned long rdnv asm("r1");
711 register unsigned long rmv asm("r0");
712 unsigned long cpsr = regs->ARM_cpsr;
714 rdnv = (rdn == 15) ? pc : regs->uregs[rdn];
715 rmv = (rm == 15) ? pc : regs->uregs[rm];
717 __asm__ __volatile__ (
718 "msr cpsr_fs, %[cpsr] \n\t"
720 "mrs %[cpsr], cpsr \n\t"
721 : "=r" (rdnv), [cpsr] "=r" (cpsr)
722 : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
723 : "lr", "memory", "cc"
729 regs->uregs[rdn] = rdnv;
730 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
733 static enum kprobe_insn __kprobes
734 t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi)
737 insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
738 ((u16 *)asi->insn)[0] = insn;
739 asi->insn_handler = t16_emulate_hiregs;
743 static void __kprobes
744 t16_emulate_push(struct kprobe *p, struct pt_regs *regs)
746 __asm__ __volatile__ (
747 "ldr r9, [%[regs], #13*4] \n\t"
748 "ldr r8, [%[regs], #14*4] \n\t"
749 "ldmia %[regs], {r0-r7} \n\t"
751 "str r9, [%[regs], #13*4] \n\t"
753 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
754 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
759 static enum kprobe_insn __kprobes
760 t16_decode_push(kprobe_opcode_t insn, struct arch_specific_insn *asi)
763 * To simulate a PUSH we use a Thumb-2 "STMDB R9!, {registers}"
764 * and call it with R9=SP and LR in the register list represented
767 ((u16 *)asi->insn)[0] = 0xe929; /* 1st half STMDB R9!,{} */
768 ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
769 asi->insn_handler = t16_emulate_push;
773 static void __kprobes
774 t16_emulate_pop_nopc(struct kprobe *p, struct pt_regs *regs)
776 __asm__ __volatile__ (
777 "ldr r9, [%[regs], #13*4] \n\t"
778 "ldmia %[regs], {r0-r7} \n\t"
780 "stmia %[regs], {r0-r7} \n\t"
781 "str r9, [%[regs], #13*4] \n\t"
783 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
784 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
789 static void __kprobes
790 t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
792 register unsigned long pc asm("r8");
794 __asm__ __volatile__ (
795 "ldr r9, [%[regs], #13*4] \n\t"
796 "ldmia %[regs], {r0-r7} \n\t"
798 "stmia %[regs], {r0-r7} \n\t"
799 "str r9, [%[regs], #13*4] \n\t"
801 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
802 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
806 bx_write_pc(pc, regs);
809 static enum kprobe_insn __kprobes
810 t16_decode_pop(kprobe_opcode_t insn, struct arch_specific_insn *asi)
813 * To simulate a POP we use a Thumb-2 "LDMDB R9!, {registers}"
814 * and call it with R9=SP and PC in the register list represented
817 ((u16 *)asi->insn)[0] = 0xe8b9; /* 1st half LDMIA R9!,{} */
818 ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
819 asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc
820 : t16_emulate_pop_nopc;
824 static const union decode_item t16_table_1011[] = {
825 /* Miscellaneous 16-bit instructions */
827 /* ADD (SP plus immediate) 1011 0000 0xxx xxxx */
828 /* SUB (SP minus immediate) 1011 0000 1xxx xxxx */
829 DECODE_SIMULATE (0xff00, 0xb000, t16_simulate_add_sp_imm),
831 /* CBZ 1011 00x1 xxxx xxxx */
832 /* CBNZ 1011 10x1 xxxx xxxx */
833 DECODE_SIMULATE (0xf500, 0xb100, t16_simulate_cbz),
835 /* SXTH 1011 0010 00xx xxxx */
836 /* SXTB 1011 0010 01xx xxxx */
837 /* UXTH 1011 0010 10xx xxxx */
838 /* UXTB 1011 0010 11xx xxxx */
839 /* REV 1011 1010 00xx xxxx */
840 /* REV16 1011 1010 01xx xxxx */
841 /* ??? 1011 1010 10xx xxxx */
842 /* REVSH 1011 1010 11xx xxxx */
843 DECODE_REJECT (0xffc0, 0xba80),
844 DECODE_EMULATE (0xf500, 0xb000, t16_emulate_loregs_rwflags),
846 /* PUSH 1011 010x xxxx xxxx */
847 DECODE_CUSTOM (0xfe00, 0xb400, t16_decode_push),
848 /* POP 1011 110x xxxx xxxx */
849 DECODE_CUSTOM (0xfe00, 0xbc00, t16_decode_pop),
853 * 1011 1111 xxxx xxxx
856 /* YIELD 1011 1111 0001 0000 */
857 DECODE_OR (0xffff, 0xbf10),
858 /* SEV 1011 1111 0100 0000 */
859 DECODE_EMULATE (0xffff, 0xbf40, kprobe_emulate_none),
860 /* NOP 1011 1111 0000 0000 */
861 /* WFE 1011 1111 0010 0000 */
862 /* WFI 1011 1111 0011 0000 */
863 DECODE_SIMULATE (0xffcf, 0xbf00, kprobe_simulate_nop),
864 /* Unassigned hints 1011 1111 xxxx 0000 */
865 DECODE_REJECT (0xff0f, 0xbf00),
866 /* IT 1011 1111 xxxx xxxx */
867 DECODE_CUSTOM (0xff00, 0xbf00, t16_decode_it),
869 /* SETEND 1011 0110 010x xxxx */
870 /* CPS 1011 0110 011x xxxx */
871 /* BKPT 1011 1110 xxxx xxxx */
872 /* And unallocated instructions... */
876 const union decode_item kprobe_decode_thumb16_table[] = {
879 * Shift (immediate), add, subtract, move, and compare
880 * 00xx xxxx xxxx xxxx
883 /* CMP (immediate) 0010 1xxx xxxx xxxx */
884 DECODE_EMULATE (0xf800, 0x2800, t16_emulate_loregs_rwflags),
886 /* ADD (register) 0001 100x xxxx xxxx */
887 /* SUB (register) 0001 101x xxxx xxxx */
888 /* LSL (immediate) 0000 0xxx xxxx xxxx */
889 /* LSR (immediate) 0000 1xxx xxxx xxxx */
890 /* ASR (immediate) 0001 0xxx xxxx xxxx */
891 /* ADD (immediate, Thumb) 0001 110x xxxx xxxx */
892 /* SUB (immediate, Thumb) 0001 111x xxxx xxxx */
893 /* MOV (immediate) 0010 0xxx xxxx xxxx */
894 /* ADD (immediate, Thumb) 0011 0xxx xxxx xxxx */
895 /* SUB (immediate, Thumb) 0011 1xxx xxxx xxxx */
896 DECODE_EMULATE (0xc000, 0x0000, t16_emulate_loregs_noitrwflags),
899 * 16-bit Thumb data-processing instructions
900 * 0100 00xx xxxx xxxx
903 /* TST (register) 0100 0010 00xx xxxx */
904 DECODE_EMULATE (0xffc0, 0x4200, t16_emulate_loregs_rwflags),
905 /* CMP (register) 0100 0010 10xx xxxx */
906 /* CMN (register) 0100 0010 11xx xxxx */
907 DECODE_EMULATE (0xff80, 0x4280, t16_emulate_loregs_rwflags),
908 /* AND (register) 0100 0000 00xx xxxx */
909 /* EOR (register) 0100 0000 01xx xxxx */
910 /* LSL (register) 0100 0000 10xx xxxx */
911 /* LSR (register) 0100 0000 11xx xxxx */
912 /* ASR (register) 0100 0001 00xx xxxx */
913 /* ADC (register) 0100 0001 01xx xxxx */
914 /* SBC (register) 0100 0001 10xx xxxx */
915 /* ROR (register) 0100 0001 11xx xxxx */
916 /* RSB (immediate) 0100 0010 01xx xxxx */
917 /* ORR (register) 0100 0011 00xx xxxx */
918 /* MUL 0100 0011 00xx xxxx */
919 /* BIC (register) 0100 0011 10xx xxxx */
920 /* MVN (register) 0100 0011 10xx xxxx */
921 DECODE_EMULATE (0xfc00, 0x4000, t16_emulate_loregs_noitrwflags),
924 * Special data instructions and branch and exchange
925 * 0100 01xx xxxx xxxx
928 /* BLX pc 0100 0111 1111 1xxx */
929 DECODE_REJECT (0xfff8, 0x47f8),
931 /* BX (register) 0100 0111 0xxx xxxx */
932 /* BLX (register) 0100 0111 1xxx xxxx */
933 DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx),
935 /* ADD pc, pc 0100 0100 1111 1111 */
936 DECODE_REJECT (0xffff, 0x44ff),
938 /* ADD (register) 0100 0100 xxxx xxxx */
939 /* CMP (register) 0100 0101 xxxx xxxx */
940 /* MOV (register) 0100 0110 xxxx xxxx */
941 DECODE_CUSTOM (0xfc00, 0x4400, t16_decode_hiregs),
944 * Load from Literal Pool
945 * LDR (literal) 0100 1xxx xxxx xxxx
947 DECODE_SIMULATE (0xf800, 0x4800, t16_simulate_ldr_literal),
950 * 16-bit Thumb Load/store instructions
951 * 0101 xxxx xxxx xxxx
952 * 011x xxxx xxxx xxxx
953 * 100x xxxx xxxx xxxx
956 /* STR (register) 0101 000x xxxx xxxx */
957 /* STRH (register) 0101 001x xxxx xxxx */
958 /* STRB (register) 0101 010x xxxx xxxx */
959 /* LDRSB (register) 0101 011x xxxx xxxx */
960 /* LDR (register) 0101 100x xxxx xxxx */
961 /* LDRH (register) 0101 101x xxxx xxxx */
962 /* LDRB (register) 0101 110x xxxx xxxx */
963 /* LDRSH (register) 0101 111x xxxx xxxx */
964 /* STR (immediate, Thumb) 0110 0xxx xxxx xxxx */
965 /* LDR (immediate, Thumb) 0110 1xxx xxxx xxxx */
966 /* STRB (immediate, Thumb) 0111 0xxx xxxx xxxx */
967 /* LDRB (immediate, Thumb) 0111 1xxx xxxx xxxx */
968 DECODE_EMULATE (0xc000, 0x4000, t16_emulate_loregs_rwflags),
969 /* STRH (immediate, Thumb) 1000 0xxx xxxx xxxx */
970 /* LDRH (immediate, Thumb) 1000 1xxx xxxx xxxx */
971 DECODE_EMULATE (0xf000, 0x8000, t16_emulate_loregs_rwflags),
972 /* STR (immediate, Thumb) 1001 0xxx xxxx xxxx */
973 /* LDR (immediate, Thumb) 1001 1xxx xxxx xxxx */
974 DECODE_SIMULATE (0xf000, 0x9000, t16_simulate_ldrstr_sp_relative),
977 * Generate PC-/SP-relative address
978 * ADR (literal) 1010 0xxx xxxx xxxx
979 * ADD (SP plus immediate) 1010 1xxx xxxx xxxx
981 DECODE_SIMULATE (0xf000, 0xa000, t16_simulate_reladr),
984 * Miscellaneous 16-bit instructions
985 * 1011 xxxx xxxx xxxx
987 DECODE_TABLE (0xf000, 0xb000, t16_table_1011),
989 /* STM 1100 0xxx xxxx xxxx */
990 /* LDM 1100 1xxx xxxx xxxx */
991 DECODE_EMULATE (0xf000, 0xc000, t16_emulate_loregs_rwflags),
994 * Conditional branch, and Supervisor Call
997 /* Permanently UNDEFINED 1101 1110 xxxx xxxx */
998 /* SVC 1101 1111 xxxx xxxx */
999 DECODE_REJECT (0xfe00, 0xde00),
1001 /* Conditional branch 1101 xxxx xxxx xxxx */
1002 DECODE_CUSTOM (0xf000, 0xd000, t16_decode_cond_branch),
1005 * Unconditional branch
1006 * B 1110 0xxx xxxx xxxx
1008 DECODE_SIMULATE (0xf800, 0xe000, t16_simulate_branch),
1013 static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
1015 if (unlikely(in_it_block(cpsr)))
1016 return kprobe_condition_checks[current_cond(cpsr)](cpsr);
1020 static void __kprobes thumb16_singlestep(struct kprobe *p, struct pt_regs *regs)
1023 p->ainsn.insn_handler(p, regs);
1024 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
1027 static void __kprobes thumb32_singlestep(struct kprobe *p, struct pt_regs *regs)
1030 p->ainsn.insn_handler(p, regs);
1031 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
1034 enum kprobe_insn __kprobes
1035 thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1037 asi->insn_singlestep = thumb16_singlestep;
1038 asi->insn_check_cc = thumb_check_cc;
1039 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true);
1042 enum kprobe_insn __kprobes
1043 thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1045 asi->insn_singlestep = thumb32_singlestep;
1046 asi->insn_check_cc = thumb_check_cc;
1047 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb32_table, true);