2 * arch/arm/kernel/kprobes-thumb.c
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/kprobes.h>
18 * True if current instruction is in an IT block.
20 #define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000)
23 * Return the condition code to check for the currently executing instruction.
24 * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
25 * in_it_block returns true.
27 #define current_cond(cpsr) ((cpsr >> 12) & 0xf)
30 * Return the PC value for a probe in thumb code.
31 * This is the address of the probed instruction plus 4.
32 * We subtract one because the address will have bit zero set to indicate
33 * a pointer to thumb code.
35 static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p)
37 return (unsigned long)p->addr - 1 + 4;
41 t32_simulate_table_branch(struct kprobe *p, struct pt_regs *regs)
43 kprobe_opcode_t insn = p->opcode;
44 unsigned long pc = thumb_probe_pc(p);
45 int rn = (insn >> 16) & 0xf;
48 unsigned long rnv = (rn == 15) ? pc : regs->uregs[rn];
49 unsigned long rmv = regs->uregs[rm];
50 unsigned int halfwords;
53 halfwords = ((u16 *)rnv)[rmv];
55 halfwords = ((u8 *)rnv)[rmv];
57 regs->ARM_pc = pc + 2 * halfwords;
61 t32_simulate_mrs(struct kprobe *p, struct pt_regs *regs)
63 kprobe_opcode_t insn = p->opcode;
64 int rd = (insn >> 8) & 0xf;
65 unsigned long mask = 0xf8ff03df; /* Mask out execution state */
66 regs->uregs[rd] = regs->ARM_cpsr & mask;
69 static enum kprobe_insn __kprobes
70 t32_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
72 enum kprobe_insn ret = kprobe_decode_ldmstm(insn, asi);
74 /* Fixup modified instruction to have halfwords in correct order...*/
76 ((u16 *)asi->insn)[0] = insn >> 16;
77 ((u16 *)asi->insn)[1] = insn & 0xffff;
83 t32_emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
85 kprobe_opcode_t insn = p->opcode;
86 unsigned long pc = thumb_probe_pc(p) & ~3;
87 int rt1 = (insn >> 12) & 0xf;
88 int rt2 = (insn >> 8) & 0xf;
89 int rn = (insn >> 16) & 0xf;
91 register unsigned long rt1v asm("r0") = regs->uregs[rt1];
92 register unsigned long rt2v asm("r1") = regs->uregs[rt2];
93 register unsigned long rnv asm("r2") = (rn == 15) ? pc
96 __asm__ __volatile__ (
98 : "=r" (rt1v), "=r" (rt2v), "=r" (rnv)
99 : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (p->ainsn.insn_fn)
100 : "lr", "memory", "cc"
104 regs->uregs[rn] = rnv; /* Writeback base register */
105 regs->uregs[rt1] = rt1v;
106 regs->uregs[rt2] = rt2v;
109 static void __kprobes
110 t32_emulate_rd8rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
112 kprobe_opcode_t insn = p->opcode;
113 int rd = (insn >> 8) & 0xf;
114 int rn = (insn >> 16) & 0xf;
117 register unsigned long rdv asm("r1") = regs->uregs[rd];
118 register unsigned long rnv asm("r2") = regs->uregs[rn];
119 register unsigned long rmv asm("r3") = regs->uregs[rm];
120 unsigned long cpsr = regs->ARM_cpsr;
122 __asm__ __volatile__ (
123 "msr cpsr_fs, %[cpsr] \n\t"
125 "mrs %[cpsr], cpsr \n\t"
126 : "=r" (rdv), [cpsr] "=r" (cpsr)
127 : "0" (rdv), "r" (rnv), "r" (rmv),
128 "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
129 : "lr", "memory", "cc"
132 regs->uregs[rd] = rdv;
133 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
136 static void __kprobes
137 t32_emulate_rd8pc16_noflags(struct kprobe *p, struct pt_regs *regs)
139 kprobe_opcode_t insn = p->opcode;
140 unsigned long pc = thumb_probe_pc(p);
141 int rd = (insn >> 8) & 0xf;
143 register unsigned long rdv asm("r1") = regs->uregs[rd];
144 register unsigned long rnv asm("r2") = pc & ~3;
146 __asm__ __volatile__ (
149 : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
150 : "lr", "memory", "cc"
153 regs->uregs[rd] = rdv;
156 static void __kprobes
157 t32_emulate_rd8rn16_noflags(struct kprobe *p, struct pt_regs *regs)
159 kprobe_opcode_t insn = p->opcode;
160 int rd = (insn >> 8) & 0xf;
161 int rn = (insn >> 16) & 0xf;
163 register unsigned long rdv asm("r1") = regs->uregs[rd];
164 register unsigned long rnv asm("r2") = regs->uregs[rn];
166 __asm__ __volatile__ (
169 : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
170 : "lr", "memory", "cc"
173 regs->uregs[rd] = rdv;
176 static const union decode_item t32_table_1110_100x_x0xx[] = {
177 /* Load/store multiple instructions */
179 /* Rn is PC 1110 100x x0xx 1111 xxxx xxxx xxxx xxxx */
180 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
182 /* SRS 1110 1000 00x0 xxxx xxxx xxxx xxxx xxxx */
183 /* RFE 1110 1000 00x1 xxxx xxxx xxxx xxxx xxxx */
184 DECODE_REJECT (0xffc00000, 0xe8000000),
185 /* SRS 1110 1001 10x0 xxxx xxxx xxxx xxxx xxxx */
186 /* RFE 1110 1001 10x1 xxxx xxxx xxxx xxxx xxxx */
187 DECODE_REJECT (0xffc00000, 0xe9800000),
189 /* STM Rn, {...pc} 1110 100x x0x0 xxxx 1xxx xxxx xxxx xxxx */
190 DECODE_REJECT (0xfe508000, 0xe8008000),
191 /* LDM Rn, {...lr,pc} 1110 100x x0x1 xxxx 11xx xxxx xxxx xxxx */
192 DECODE_REJECT (0xfe50c000, 0xe810c000),
193 /* LDM/STM Rn, {...sp} 1110 100x x0xx xxxx xx1x xxxx xxxx xxxx */
194 DECODE_REJECT (0xfe402000, 0xe8002000),
196 /* STMIA 1110 1000 10x0 xxxx xxxx xxxx xxxx xxxx */
197 /* LDMIA 1110 1000 10x1 xxxx xxxx xxxx xxxx xxxx */
198 /* STMDB 1110 1001 00x0 xxxx xxxx xxxx xxxx xxxx */
199 /* LDMDB 1110 1001 00x1 xxxx xxxx xxxx xxxx xxxx */
200 DECODE_CUSTOM (0xfe400000, 0xe8000000, t32_decode_ldmstm),
205 static const union decode_item t32_table_1110_100x_x1xx[] = {
206 /* Load/store dual, load/store exclusive, table branch */
208 /* STRD (immediate) 1110 1000 x110 xxxx xxxx xxxx xxxx xxxx */
209 /* LDRD (immediate) 1110 1000 x111 xxxx xxxx xxxx xxxx xxxx */
210 DECODE_OR (0xff600000, 0xe8600000),
211 /* STRD (immediate) 1110 1001 x1x0 xxxx xxxx xxxx xxxx xxxx */
212 /* LDRD (immediate) 1110 1001 x1x1 xxxx xxxx xxxx xxxx xxxx */
213 DECODE_EMULATEX (0xff400000, 0xe9400000, t32_emulate_ldrdstrd,
214 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
216 /* TBB 1110 1000 1101 xxxx xxxx xxxx 0000 xxxx */
217 /* TBH 1110 1000 1101 xxxx xxxx xxxx 0001 xxxx */
218 DECODE_SIMULATEX(0xfff000e0, 0xe8d00000, t32_simulate_table_branch,
219 REGS(NOSP, 0, 0, 0, NOSPPC)),
221 /* STREX 1110 1000 0100 xxxx xxxx xxxx xxxx xxxx */
222 /* LDREX 1110 1000 0101 xxxx xxxx xxxx xxxx xxxx */
223 /* STREXB 1110 1000 1100 xxxx xxxx xxxx 0100 xxxx */
224 /* STREXH 1110 1000 1100 xxxx xxxx xxxx 0101 xxxx */
225 /* STREXD 1110 1000 1100 xxxx xxxx xxxx 0111 xxxx */
226 /* LDREXB 1110 1000 1101 xxxx xxxx xxxx 0100 xxxx */
227 /* LDREXH 1110 1000 1101 xxxx xxxx xxxx 0101 xxxx */
228 /* LDREXD 1110 1000 1101 xxxx xxxx xxxx 0111 xxxx */
229 /* And unallocated instructions... */
233 static const union decode_item t32_table_1110_101x[] = {
234 /* Data-processing (shifted register) */
236 /* TST 1110 1010 0001 xxxx xxxx 1111 xxxx xxxx */
237 /* TEQ 1110 1010 1001 xxxx xxxx 1111 xxxx xxxx */
238 DECODE_EMULATEX (0xff700f00, 0xea100f00, t32_emulate_rd8rn16rm0_rwflags,
239 REGS(NOSPPC, 0, 0, 0, NOSPPC)),
241 /* CMN 1110 1011 0001 xxxx xxxx 1111 xxxx xxxx */
242 DECODE_OR (0xfff00f00, 0xeb100f00),
243 /* CMP 1110 1011 1011 xxxx xxxx 1111 xxxx xxxx */
244 DECODE_EMULATEX (0xfff00f00, 0xebb00f00, t32_emulate_rd8rn16rm0_rwflags,
245 REGS(NOPC, 0, 0, 0, NOSPPC)),
247 /* MOV 1110 1010 010x 1111 xxxx xxxx xxxx xxxx */
248 /* MVN 1110 1010 011x 1111 xxxx xxxx xxxx xxxx */
249 DECODE_EMULATEX (0xffcf0000, 0xea4f0000, t32_emulate_rd8rn16rm0_rwflags,
250 REGS(0, 0, NOSPPC, 0, NOSPPC)),
252 /* ??? 1110 1010 101x xxxx xxxx xxxx xxxx xxxx */
253 /* ??? 1110 1010 111x xxxx xxxx xxxx xxxx xxxx */
254 DECODE_REJECT (0xffa00000, 0xeaa00000),
255 /* ??? 1110 1011 001x xxxx xxxx xxxx xxxx xxxx */
256 DECODE_REJECT (0xffe00000, 0xeb200000),
257 /* ??? 1110 1011 100x xxxx xxxx xxxx xxxx xxxx */
258 DECODE_REJECT (0xffe00000, 0xeb800000),
259 /* ??? 1110 1011 111x xxxx xxxx xxxx xxxx xxxx */
260 DECODE_REJECT (0xffe00000, 0xebe00000),
262 /* ADD/SUB SP, SP, Rm, LSL #0..3 */
263 /* 1110 1011 x0xx 1101 x000 1101 xx00 xxxx */
264 DECODE_EMULATEX (0xff4f7f30, 0xeb0d0d00, t32_emulate_rd8rn16rm0_rwflags,
265 REGS(SP, 0, SP, 0, NOSPPC)),
267 /* ADD/SUB SP, SP, Rm, shift */
268 /* 1110 1011 x0xx 1101 xxxx 1101 xxxx xxxx */
269 DECODE_REJECT (0xff4f0f00, 0xeb0d0d00),
271 /* ADD/SUB Rd, SP, Rm, shift */
272 /* 1110 1011 x0xx 1101 xxxx xxxx xxxx xxxx */
273 DECODE_EMULATEX (0xff4f0000, 0xeb0d0000, t32_emulate_rd8rn16rm0_rwflags,
274 REGS(SP, 0, NOPC, 0, NOSPPC)),
276 /* AND 1110 1010 000x xxxx xxxx xxxx xxxx xxxx */
277 /* BIC 1110 1010 001x xxxx xxxx xxxx xxxx xxxx */
278 /* ORR 1110 1010 010x xxxx xxxx xxxx xxxx xxxx */
279 /* ORN 1110 1010 011x xxxx xxxx xxxx xxxx xxxx */
280 /* EOR 1110 1010 100x xxxx xxxx xxxx xxxx xxxx */
281 /* PKH 1110 1010 110x xxxx xxxx xxxx xxxx xxxx */
282 /* ADD 1110 1011 000x xxxx xxxx xxxx xxxx xxxx */
283 /* ADC 1110 1011 010x xxxx xxxx xxxx xxxx xxxx */
284 /* SBC 1110 1011 011x xxxx xxxx xxxx xxxx xxxx */
285 /* SUB 1110 1011 101x xxxx xxxx xxxx xxxx xxxx */
286 /* RSB 1110 1011 110x xxxx xxxx xxxx xxxx xxxx */
287 DECODE_EMULATEX (0xfe000000, 0xea000000, t32_emulate_rd8rn16rm0_rwflags,
288 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
293 static const union decode_item t32_table_1111_0x0x___0[] = {
294 /* Data-processing (modified immediate) */
296 /* TST 1111 0x00 0001 xxxx 0xxx 1111 xxxx xxxx */
297 /* TEQ 1111 0x00 1001 xxxx 0xxx 1111 xxxx xxxx */
298 DECODE_EMULATEX (0xfb708f00, 0xf0100f00, t32_emulate_rd8rn16rm0_rwflags,
299 REGS(NOSPPC, 0, 0, 0, 0)),
301 /* CMN 1111 0x01 0001 xxxx 0xxx 1111 xxxx xxxx */
302 DECODE_OR (0xfbf08f00, 0xf1100f00),
303 /* CMP 1111 0x01 1011 xxxx 0xxx 1111 xxxx xxxx */
304 DECODE_EMULATEX (0xfbf08f00, 0xf1b00f00, t32_emulate_rd8rn16rm0_rwflags,
305 REGS(NOPC, 0, 0, 0, 0)),
307 /* MOV 1111 0x00 010x 1111 0xxx xxxx xxxx xxxx */
308 /* MVN 1111 0x00 011x 1111 0xxx xxxx xxxx xxxx */
309 DECODE_EMULATEX (0xfbcf8000, 0xf04f0000, t32_emulate_rd8rn16rm0_rwflags,
310 REGS(0, 0, NOSPPC, 0, 0)),
312 /* ??? 1111 0x00 101x xxxx 0xxx xxxx xxxx xxxx */
313 DECODE_REJECT (0xfbe08000, 0xf0a00000),
314 /* ??? 1111 0x00 110x xxxx 0xxx xxxx xxxx xxxx */
315 /* ??? 1111 0x00 111x xxxx 0xxx xxxx xxxx xxxx */
316 DECODE_REJECT (0xfbc08000, 0xf0c00000),
317 /* ??? 1111 0x01 001x xxxx 0xxx xxxx xxxx xxxx */
318 DECODE_REJECT (0xfbe08000, 0xf1200000),
319 /* ??? 1111 0x01 100x xxxx 0xxx xxxx xxxx xxxx */
320 DECODE_REJECT (0xfbe08000, 0xf1800000),
321 /* ??? 1111 0x01 111x xxxx 0xxx xxxx xxxx xxxx */
322 DECODE_REJECT (0xfbe08000, 0xf1e00000),
324 /* ADD Rd, SP, #imm 1111 0x01 000x 1101 0xxx xxxx xxxx xxxx */
325 /* SUB Rd, SP, #imm 1111 0x01 101x 1101 0xxx xxxx xxxx xxxx */
326 DECODE_EMULATEX (0xfb4f8000, 0xf10d0000, t32_emulate_rd8rn16rm0_rwflags,
327 REGS(SP, 0, NOPC, 0, 0)),
329 /* AND 1111 0x00 000x xxxx 0xxx xxxx xxxx xxxx */
330 /* BIC 1111 0x00 001x xxxx 0xxx xxxx xxxx xxxx */
331 /* ORR 1111 0x00 010x xxxx 0xxx xxxx xxxx xxxx */
332 /* ORN 1111 0x00 011x xxxx 0xxx xxxx xxxx xxxx */
333 /* EOR 1111 0x00 100x xxxx 0xxx xxxx xxxx xxxx */
334 /* ADD 1111 0x01 000x xxxx 0xxx xxxx xxxx xxxx */
335 /* ADC 1111 0x01 010x xxxx 0xxx xxxx xxxx xxxx */
336 /* SBC 1111 0x01 011x xxxx 0xxx xxxx xxxx xxxx */
337 /* SUB 1111 0x01 101x xxxx 0xxx xxxx xxxx xxxx */
338 /* RSB 1111 0x01 110x xxxx 0xxx xxxx xxxx xxxx */
339 DECODE_EMULATEX (0xfa008000, 0xf0000000, t32_emulate_rd8rn16rm0_rwflags,
340 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
345 static const union decode_item t32_table_1111_0x1x___0[] = {
346 /* Data-processing (plain binary immediate) */
348 /* ADDW Rd, PC, #imm 1111 0x10 0000 1111 0xxx xxxx xxxx xxxx */
349 DECODE_OR (0xfbff8000, 0xf20f0000),
350 /* SUBW Rd, PC, #imm 1111 0x10 1010 1111 0xxx xxxx xxxx xxxx */
351 DECODE_EMULATEX (0xfbff8000, 0xf2af0000, t32_emulate_rd8pc16_noflags,
352 REGS(PC, 0, NOSPPC, 0, 0)),
354 /* ADDW SP, SP, #imm 1111 0x10 0000 1101 0xxx 1101 xxxx xxxx */
355 DECODE_OR (0xfbff8f00, 0xf20d0d00),
356 /* SUBW SP, SP, #imm 1111 0x10 1010 1101 0xxx 1101 xxxx xxxx */
357 DECODE_EMULATEX (0xfbff8f00, 0xf2ad0d00, t32_emulate_rd8rn16_noflags,
358 REGS(SP, 0, SP, 0, 0)),
360 /* ADDW 1111 0x10 0000 xxxx 0xxx xxxx xxxx xxxx */
361 DECODE_OR (0xfbf08000, 0xf2000000),
362 /* SUBW 1111 0x10 1010 xxxx 0xxx xxxx xxxx xxxx */
363 DECODE_EMULATEX (0xfbf08000, 0xf2a00000, t32_emulate_rd8rn16_noflags,
364 REGS(NOPCX, 0, NOSPPC, 0, 0)),
366 /* MOVW 1111 0x10 0100 xxxx 0xxx xxxx xxxx xxxx */
367 /* MOVT 1111 0x10 1100 xxxx 0xxx xxxx xxxx xxxx */
368 DECODE_EMULATEX (0xfb708000, 0xf2400000, t32_emulate_rd8rn16_noflags,
369 REGS(0, 0, NOSPPC, 0, 0)),
371 /* SSAT16 1111 0x11 0010 xxxx 0000 xxxx 00xx xxxx */
372 /* SSAT 1111 0x11 00x0 xxxx 0xxx xxxx xxxx xxxx */
373 /* USAT16 1111 0x11 1010 xxxx 0000 xxxx 00xx xxxx */
374 /* USAT 1111 0x11 10x0 xxxx 0xxx xxxx xxxx xxxx */
375 DECODE_EMULATEX (0xfb508000, 0xf3000000, t32_emulate_rd8rn16rm0_rwflags,
376 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
378 /* SFBX 1111 0x11 0100 xxxx 0xxx xxxx xxxx xxxx */
379 /* UFBX 1111 0x11 1100 xxxx 0xxx xxxx xxxx xxxx */
380 DECODE_EMULATEX (0xfb708000, 0xf3400000, t32_emulate_rd8rn16_noflags,
381 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
383 /* BFC 1111 0x11 0110 1111 0xxx xxxx xxxx xxxx */
384 DECODE_EMULATEX (0xfbff8000, 0xf36f0000, t32_emulate_rd8rn16_noflags,
385 REGS(0, 0, NOSPPC, 0, 0)),
387 /* BFI 1111 0x11 0110 xxxx 0xxx xxxx xxxx xxxx */
388 DECODE_EMULATEX (0xfbf08000, 0xf3600000, t32_emulate_rd8rn16_noflags,
389 REGS(NOSPPCX, 0, NOSPPC, 0, 0)),
394 static const union decode_item t32_table_1111_0xxx___1[] = {
395 /* Branches and miscellaneous control */
397 /* YIELD 1111 0011 1010 xxxx 10x0 x000 0000 0001 */
398 DECODE_OR (0xfff0d7ff, 0xf3a08001),
399 /* SEV 1111 0011 1010 xxxx 10x0 x000 0000 0100 */
400 DECODE_EMULATE (0xfff0d7ff, 0xf3a08004, kprobe_emulate_none),
401 /* NOP 1111 0011 1010 xxxx 10x0 x000 0000 0000 */
402 /* WFE 1111 0011 1010 xxxx 10x0 x000 0000 0010 */
403 /* WFI 1111 0011 1010 xxxx 10x0 x000 0000 0011 */
404 DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, kprobe_simulate_nop),
406 /* MRS Rd, CPSR 1111 0011 1110 xxxx 10x0 xxxx xxxx xxxx */
407 DECODE_SIMULATEX(0xfff0d000, 0xf3e08000, t32_simulate_mrs,
408 REGS(0, 0, NOSPPC, 0, 0)),
411 * Unsupported instructions
412 * 1111 0x11 1xxx xxxx 10x0 xxxx xxxx xxxx
414 * MSR 1111 0011 100x xxxx 10x0 xxxx xxxx xxxx
415 * DBG hint 1111 0011 1010 xxxx 10x0 x000 1111 xxxx
416 * Unallocated hints 1111 0011 1010 xxxx 10x0 x000 xxxx xxxx
417 * CPS 1111 0011 1010 xxxx 10x0 xxxx xxxx xxxx
418 * CLREX/DSB/DMB/ISB 1111 0011 1011 xxxx 10x0 xxxx xxxx xxxx
419 * BXJ 1111 0011 1100 xxxx 10x0 xxxx xxxx xxxx
420 * SUBS PC,LR,#<imm8> 1111 0011 1101 xxxx 10x0 xxxx xxxx xxxx
421 * MRS Rd, SPSR 1111 0011 1111 xxxx 10x0 xxxx xxxx xxxx
422 * SMC 1111 0111 1111 xxxx 1000 xxxx xxxx xxxx
423 * UNDEFINED 1111 0111 1111 xxxx 1010 xxxx xxxx xxxx
424 * ??? 1111 0111 1xxx xxxx 1010 xxxx xxxx xxxx
426 DECODE_REJECT (0xfb80d000, 0xf3808000),
431 const union decode_item kprobe_decode_thumb32_table[] = {
434 * Load/store multiple instructions
435 * 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx
437 DECODE_TABLE (0xfe400000, 0xe8000000, t32_table_1110_100x_x0xx),
440 * Load/store dual, load/store exclusive, table branch
441 * 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx
443 DECODE_TABLE (0xfe400000, 0xe8400000, t32_table_1110_100x_x1xx),
446 * Data-processing (shifted register)
447 * 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx
449 DECODE_TABLE (0xfe000000, 0xea000000, t32_table_1110_101x),
452 * Data-processing (modified immediate)
453 * 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx
455 DECODE_TABLE (0xfa008000, 0xf0000000, t32_table_1111_0x0x___0),
458 * Data-processing (plain binary immediate)
459 * 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx
461 DECODE_TABLE (0xfa008000, 0xf2000000, t32_table_1111_0x1x___0),
464 * Branches and miscellaneous control
465 * 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx
467 DECODE_TABLE (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1),
472 static void __kprobes
473 t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
475 kprobe_opcode_t insn = p->opcode;
476 unsigned long pc = thumb_probe_pc(p);
477 int rm = (insn >> 3) & 0xf;
478 unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];
480 if (insn & (1 << 7)) /* BLX ? */
481 regs->ARM_lr = (unsigned long)p->addr + 2;
483 bx_write_pc(rmv, regs);
486 static void __kprobes
487 t16_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
489 kprobe_opcode_t insn = p->opcode;
490 unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3);
491 long index = insn & 0xff;
492 int rt = (insn >> 8) & 0x7;
493 regs->uregs[rt] = base[index];
496 static void __kprobes
497 t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs)
499 kprobe_opcode_t insn = p->opcode;
500 unsigned long* base = (unsigned long *)regs->ARM_sp;
501 long index = insn & 0xff;
502 int rt = (insn >> 8) & 0x7;
503 if (insn & 0x800) /* LDR */
504 regs->uregs[rt] = base[index];
506 base[index] = regs->uregs[rt];
509 static void __kprobes
510 t16_simulate_reladr(struct kprobe *p, struct pt_regs *regs)
512 kprobe_opcode_t insn = p->opcode;
513 unsigned long base = (insn & 0x800) ? regs->ARM_sp
514 : (thumb_probe_pc(p) & ~3);
515 long offset = insn & 0xff;
516 int rt = (insn >> 8) & 0x7;
517 regs->uregs[rt] = base + offset * 4;
520 static void __kprobes
521 t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs)
523 kprobe_opcode_t insn = p->opcode;
524 long imm = insn & 0x7f;
525 if (insn & 0x80) /* SUB */
526 regs->ARM_sp -= imm * 4;
528 regs->ARM_sp += imm * 4;
531 static void __kprobes
532 t16_simulate_cbz(struct kprobe *p, struct pt_regs *regs)
534 kprobe_opcode_t insn = p->opcode;
536 kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
537 if (nonzero & 0x800) {
538 long i = insn & 0x200;
539 long imm5 = insn & 0xf8;
540 unsigned long pc = thumb_probe_pc(p);
541 regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
545 static void __kprobes
546 t16_simulate_it(struct kprobe *p, struct pt_regs *regs)
549 * The 8 IT state bits are split into two parts in CPSR:
550 * ITSTATE<1:0> are in CPSR<26:25>
551 * ITSTATE<7:2> are in CPSR<15:10>
552 * The new IT state is in the lower byte of insn.
554 kprobe_opcode_t insn = p->opcode;
555 unsigned long cpsr = regs->ARM_cpsr;
556 cpsr &= ~PSR_IT_MASK;
557 cpsr |= (insn & 0xfc) << 8;
558 cpsr |= (insn & 0x03) << 25;
559 regs->ARM_cpsr = cpsr;
562 static void __kprobes
563 t16_singlestep_it(struct kprobe *p, struct pt_regs *regs)
566 t16_simulate_it(p, regs);
569 static enum kprobe_insn __kprobes
570 t16_decode_it(kprobe_opcode_t insn, struct arch_specific_insn *asi)
572 asi->insn_singlestep = t16_singlestep_it;
573 return INSN_GOOD_NO_SLOT;
576 static void __kprobes
577 t16_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
579 kprobe_opcode_t insn = p->opcode;
580 unsigned long pc = thumb_probe_pc(p);
581 long offset = insn & 0x7f;
582 offset -= insn & 0x80; /* Apply sign bit */
583 regs->ARM_pc = pc + (offset * 2);
586 static enum kprobe_insn __kprobes
587 t16_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
589 int cc = (insn >> 8) & 0xf;
590 asi->insn_check_cc = kprobe_condition_checks[cc];
591 asi->insn_handler = t16_simulate_cond_branch;
592 return INSN_GOOD_NO_SLOT;
595 static void __kprobes
596 t16_simulate_branch(struct kprobe *p, struct pt_regs *regs)
598 kprobe_opcode_t insn = p->opcode;
599 unsigned long pc = thumb_probe_pc(p);
600 long offset = insn & 0x3ff;
601 offset -= insn & 0x400; /* Apply sign bit */
602 regs->ARM_pc = pc + (offset * 2);
605 static unsigned long __kprobes
606 t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
608 unsigned long oldcpsr = regs->ARM_cpsr;
609 unsigned long newcpsr;
611 __asm__ __volatile__ (
612 "msr cpsr_fs, %[oldcpsr] \n\t"
613 "ldmia %[regs], {r0-r7} \n\t"
615 "stmia %[regs], {r0-r7} \n\t"
616 "mrs %[newcpsr], cpsr \n\t"
617 : [newcpsr] "=r" (newcpsr)
618 : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
619 [fn] "r" (p->ainsn.insn_fn)
620 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
624 return (oldcpsr & ~APSR_MASK) | (newcpsr & APSR_MASK);
627 static void __kprobes
628 t16_emulate_loregs_rwflags(struct kprobe *p, struct pt_regs *regs)
630 regs->ARM_cpsr = t16_emulate_loregs(p, regs);
633 static void __kprobes
634 t16_emulate_loregs_noitrwflags(struct kprobe *p, struct pt_regs *regs)
636 unsigned long cpsr = t16_emulate_loregs(p, regs);
637 if (!in_it_block(cpsr))
638 regs->ARM_cpsr = cpsr;
641 static void __kprobes
642 t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
644 kprobe_opcode_t insn = p->opcode;
645 unsigned long pc = thumb_probe_pc(p);
646 int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
647 int rm = (insn >> 3) & 0xf;
649 register unsigned long rdnv asm("r1");
650 register unsigned long rmv asm("r0");
651 unsigned long cpsr = regs->ARM_cpsr;
653 rdnv = (rdn == 15) ? pc : regs->uregs[rdn];
654 rmv = (rm == 15) ? pc : regs->uregs[rm];
656 __asm__ __volatile__ (
657 "msr cpsr_fs, %[cpsr] \n\t"
659 "mrs %[cpsr], cpsr \n\t"
660 : "=r" (rdnv), [cpsr] "=r" (cpsr)
661 : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
662 : "lr", "memory", "cc"
668 regs->uregs[rdn] = rdnv;
669 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
672 static enum kprobe_insn __kprobes
673 t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi)
676 insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
677 ((u16 *)asi->insn)[0] = insn;
678 asi->insn_handler = t16_emulate_hiregs;
682 static void __kprobes
683 t16_emulate_push(struct kprobe *p, struct pt_regs *regs)
685 __asm__ __volatile__ (
686 "ldr r9, [%[regs], #13*4] \n\t"
687 "ldr r8, [%[regs], #14*4] \n\t"
688 "ldmia %[regs], {r0-r7} \n\t"
690 "str r9, [%[regs], #13*4] \n\t"
692 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
693 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
698 static enum kprobe_insn __kprobes
699 t16_decode_push(kprobe_opcode_t insn, struct arch_specific_insn *asi)
702 * To simulate a PUSH we use a Thumb-2 "STMDB R9!, {registers}"
703 * and call it with R9=SP and LR in the register list represented
706 ((u16 *)asi->insn)[0] = 0xe929; /* 1st half STMDB R9!,{} */
707 ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
708 asi->insn_handler = t16_emulate_push;
712 static void __kprobes
713 t16_emulate_pop_nopc(struct kprobe *p, struct pt_regs *regs)
715 __asm__ __volatile__ (
716 "ldr r9, [%[regs], #13*4] \n\t"
717 "ldmia %[regs], {r0-r7} \n\t"
719 "stmia %[regs], {r0-r7} \n\t"
720 "str r9, [%[regs], #13*4] \n\t"
722 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
723 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
728 static void __kprobes
729 t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
731 register unsigned long pc asm("r8");
733 __asm__ __volatile__ (
734 "ldr r9, [%[regs], #13*4] \n\t"
735 "ldmia %[regs], {r0-r7} \n\t"
737 "stmia %[regs], {r0-r7} \n\t"
738 "str r9, [%[regs], #13*4] \n\t"
740 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
741 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
745 bx_write_pc(pc, regs);
748 static enum kprobe_insn __kprobes
749 t16_decode_pop(kprobe_opcode_t insn, struct arch_specific_insn *asi)
752 * To simulate a POP we use a Thumb-2 "LDMDB R9!, {registers}"
753 * and call it with R9=SP and PC in the register list represented
756 ((u16 *)asi->insn)[0] = 0xe8b9; /* 1st half LDMIA R9!,{} */
757 ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
758 asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc
759 : t16_emulate_pop_nopc;
763 static const union decode_item t16_table_1011[] = {
764 /* Miscellaneous 16-bit instructions */
766 /* ADD (SP plus immediate) 1011 0000 0xxx xxxx */
767 /* SUB (SP minus immediate) 1011 0000 1xxx xxxx */
768 DECODE_SIMULATE (0xff00, 0xb000, t16_simulate_add_sp_imm),
770 /* CBZ 1011 00x1 xxxx xxxx */
771 /* CBNZ 1011 10x1 xxxx xxxx */
772 DECODE_SIMULATE (0xf500, 0xb100, t16_simulate_cbz),
774 /* SXTH 1011 0010 00xx xxxx */
775 /* SXTB 1011 0010 01xx xxxx */
776 /* UXTH 1011 0010 10xx xxxx */
777 /* UXTB 1011 0010 11xx xxxx */
778 /* REV 1011 1010 00xx xxxx */
779 /* REV16 1011 1010 01xx xxxx */
780 /* ??? 1011 1010 10xx xxxx */
781 /* REVSH 1011 1010 11xx xxxx */
782 DECODE_REJECT (0xffc0, 0xba80),
783 DECODE_EMULATE (0xf500, 0xb000, t16_emulate_loregs_rwflags),
785 /* PUSH 1011 010x xxxx xxxx */
786 DECODE_CUSTOM (0xfe00, 0xb400, t16_decode_push),
787 /* POP 1011 110x xxxx xxxx */
788 DECODE_CUSTOM (0xfe00, 0xbc00, t16_decode_pop),
792 * 1011 1111 xxxx xxxx
795 /* YIELD 1011 1111 0001 0000 */
796 DECODE_OR (0xffff, 0xbf10),
797 /* SEV 1011 1111 0100 0000 */
798 DECODE_EMULATE (0xffff, 0xbf40, kprobe_emulate_none),
799 /* NOP 1011 1111 0000 0000 */
800 /* WFE 1011 1111 0010 0000 */
801 /* WFI 1011 1111 0011 0000 */
802 DECODE_SIMULATE (0xffcf, 0xbf00, kprobe_simulate_nop),
803 /* Unassigned hints 1011 1111 xxxx 0000 */
804 DECODE_REJECT (0xff0f, 0xbf00),
805 /* IT 1011 1111 xxxx xxxx */
806 DECODE_CUSTOM (0xff00, 0xbf00, t16_decode_it),
808 /* SETEND 1011 0110 010x xxxx */
809 /* CPS 1011 0110 011x xxxx */
810 /* BKPT 1011 1110 xxxx xxxx */
811 /* And unallocated instructions... */
815 const union decode_item kprobe_decode_thumb16_table[] = {
818 * Shift (immediate), add, subtract, move, and compare
819 * 00xx xxxx xxxx xxxx
822 /* CMP (immediate) 0010 1xxx xxxx xxxx */
823 DECODE_EMULATE (0xf800, 0x2800, t16_emulate_loregs_rwflags),
825 /* ADD (register) 0001 100x xxxx xxxx */
826 /* SUB (register) 0001 101x xxxx xxxx */
827 /* LSL (immediate) 0000 0xxx xxxx xxxx */
828 /* LSR (immediate) 0000 1xxx xxxx xxxx */
829 /* ASR (immediate) 0001 0xxx xxxx xxxx */
830 /* ADD (immediate, Thumb) 0001 110x xxxx xxxx */
831 /* SUB (immediate, Thumb) 0001 111x xxxx xxxx */
832 /* MOV (immediate) 0010 0xxx xxxx xxxx */
833 /* ADD (immediate, Thumb) 0011 0xxx xxxx xxxx */
834 /* SUB (immediate, Thumb) 0011 1xxx xxxx xxxx */
835 DECODE_EMULATE (0xc000, 0x0000, t16_emulate_loregs_noitrwflags),
838 * 16-bit Thumb data-processing instructions
839 * 0100 00xx xxxx xxxx
842 /* TST (register) 0100 0010 00xx xxxx */
843 DECODE_EMULATE (0xffc0, 0x4200, t16_emulate_loregs_rwflags),
844 /* CMP (register) 0100 0010 10xx xxxx */
845 /* CMN (register) 0100 0010 11xx xxxx */
846 DECODE_EMULATE (0xff80, 0x4280, t16_emulate_loregs_rwflags),
847 /* AND (register) 0100 0000 00xx xxxx */
848 /* EOR (register) 0100 0000 01xx xxxx */
849 /* LSL (register) 0100 0000 10xx xxxx */
850 /* LSR (register) 0100 0000 11xx xxxx */
851 /* ASR (register) 0100 0001 00xx xxxx */
852 /* ADC (register) 0100 0001 01xx xxxx */
853 /* SBC (register) 0100 0001 10xx xxxx */
854 /* ROR (register) 0100 0001 11xx xxxx */
855 /* RSB (immediate) 0100 0010 01xx xxxx */
856 /* ORR (register) 0100 0011 00xx xxxx */
857 /* MUL 0100 0011 00xx xxxx */
858 /* BIC (register) 0100 0011 10xx xxxx */
859 /* MVN (register) 0100 0011 10xx xxxx */
860 DECODE_EMULATE (0xfc00, 0x4000, t16_emulate_loregs_noitrwflags),
863 * Special data instructions and branch and exchange
864 * 0100 01xx xxxx xxxx
867 /* BLX pc 0100 0111 1111 1xxx */
868 DECODE_REJECT (0xfff8, 0x47f8),
870 /* BX (register) 0100 0111 0xxx xxxx */
871 /* BLX (register) 0100 0111 1xxx xxxx */
872 DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx),
874 /* ADD pc, pc 0100 0100 1111 1111 */
875 DECODE_REJECT (0xffff, 0x44ff),
877 /* ADD (register) 0100 0100 xxxx xxxx */
878 /* CMP (register) 0100 0101 xxxx xxxx */
879 /* MOV (register) 0100 0110 xxxx xxxx */
880 DECODE_CUSTOM (0xfc00, 0x4400, t16_decode_hiregs),
883 * Load from Literal Pool
884 * LDR (literal) 0100 1xxx xxxx xxxx
886 DECODE_SIMULATE (0xf800, 0x4800, t16_simulate_ldr_literal),
889 * 16-bit Thumb Load/store instructions
890 * 0101 xxxx xxxx xxxx
891 * 011x xxxx xxxx xxxx
892 * 100x xxxx xxxx xxxx
895 /* STR (register) 0101 000x xxxx xxxx */
896 /* STRH (register) 0101 001x xxxx xxxx */
897 /* STRB (register) 0101 010x xxxx xxxx */
898 /* LDRSB (register) 0101 011x xxxx xxxx */
899 /* LDR (register) 0101 100x xxxx xxxx */
900 /* LDRH (register) 0101 101x xxxx xxxx */
901 /* LDRB (register) 0101 110x xxxx xxxx */
902 /* LDRSH (register) 0101 111x xxxx xxxx */
903 /* STR (immediate, Thumb) 0110 0xxx xxxx xxxx */
904 /* LDR (immediate, Thumb) 0110 1xxx xxxx xxxx */
905 /* STRB (immediate, Thumb) 0111 0xxx xxxx xxxx */
906 /* LDRB (immediate, Thumb) 0111 1xxx xxxx xxxx */
907 DECODE_EMULATE (0xc000, 0x4000, t16_emulate_loregs_rwflags),
908 /* STRH (immediate, Thumb) 1000 0xxx xxxx xxxx */
909 /* LDRH (immediate, Thumb) 1000 1xxx xxxx xxxx */
910 DECODE_EMULATE (0xf000, 0x8000, t16_emulate_loregs_rwflags),
911 /* STR (immediate, Thumb) 1001 0xxx xxxx xxxx */
912 /* LDR (immediate, Thumb) 1001 1xxx xxxx xxxx */
913 DECODE_SIMULATE (0xf000, 0x9000, t16_simulate_ldrstr_sp_relative),
916 * Generate PC-/SP-relative address
917 * ADR (literal) 1010 0xxx xxxx xxxx
918 * ADD (SP plus immediate) 1010 1xxx xxxx xxxx
920 DECODE_SIMULATE (0xf000, 0xa000, t16_simulate_reladr),
923 * Miscellaneous 16-bit instructions
924 * 1011 xxxx xxxx xxxx
926 DECODE_TABLE (0xf000, 0xb000, t16_table_1011),
928 /* STM 1100 0xxx xxxx xxxx */
929 /* LDM 1100 1xxx xxxx xxxx */
930 DECODE_EMULATE (0xf000, 0xc000, t16_emulate_loregs_rwflags),
933 * Conditional branch, and Supervisor Call
936 /* Permanently UNDEFINED 1101 1110 xxxx xxxx */
937 /* SVC 1101 1111 xxxx xxxx */
938 DECODE_REJECT (0xfe00, 0xde00),
940 /* Conditional branch 1101 xxxx xxxx xxxx */
941 DECODE_CUSTOM (0xf000, 0xd000, t16_decode_cond_branch),
944 * Unconditional branch
945 * B 1110 0xxx xxxx xxxx
947 DECODE_SIMULATE (0xf800, 0xe000, t16_simulate_branch),
952 static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
954 if (unlikely(in_it_block(cpsr)))
955 return kprobe_condition_checks[current_cond(cpsr)](cpsr);
959 static void __kprobes thumb16_singlestep(struct kprobe *p, struct pt_regs *regs)
962 p->ainsn.insn_handler(p, regs);
963 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
966 static void __kprobes thumb32_singlestep(struct kprobe *p, struct pt_regs *regs)
969 p->ainsn.insn_handler(p, regs);
970 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
973 enum kprobe_insn __kprobes
974 thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
976 asi->insn_singlestep = thumb16_singlestep;
977 asi->insn_check_cc = thumb_check_cc;
978 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true);
981 enum kprobe_insn __kprobes
982 thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
984 asi->insn_singlestep = thumb32_singlestep;
985 asi->insn_check_cc = thumb_check_cc;
986 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb32_table, true);