2 * arch/arm/kernel/kprobes-thumb.c
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/kprobes.h>
18 * True if current instruction is in an IT block.
20 #define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000)
23 * Return the condition code to check for the currently executing instruction.
24 * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
25 * in_it_block returns true.
27 #define current_cond(cpsr) ((cpsr >> 12) & 0xf)
30 * Return the PC value for a probe in thumb code.
31 * This is the address of the probed instruction plus 4.
32 * We subtract one because the address will have bit zero set to indicate
33 * a pointer to thumb code.
35 static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p)
37 return (unsigned long)p->addr - 1 + 4;
41 t32_simulate_table_branch(struct kprobe *p, struct pt_regs *regs)
43 kprobe_opcode_t insn = p->opcode;
44 unsigned long pc = thumb_probe_pc(p);
45 int rn = (insn >> 16) & 0xf;
48 unsigned long rnv = (rn == 15) ? pc : regs->uregs[rn];
49 unsigned long rmv = regs->uregs[rm];
50 unsigned int halfwords;
52 if (insn & 0x10) /* TBH */
53 halfwords = ((u16 *)rnv)[rmv];
55 halfwords = ((u8 *)rnv)[rmv];
57 regs->ARM_pc = pc + 2 * halfwords;
61 t32_simulate_mrs(struct kprobe *p, struct pt_regs *regs)
63 kprobe_opcode_t insn = p->opcode;
64 int rd = (insn >> 8) & 0xf;
65 unsigned long mask = 0xf8ff03df; /* Mask out execution state */
66 regs->uregs[rd] = regs->ARM_cpsr & mask;
70 t32_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
72 kprobe_opcode_t insn = p->opcode;
73 unsigned long pc = thumb_probe_pc(p);
75 long offset = insn & 0x7ff; /* imm11 */
76 offset += (insn & 0x003f0000) >> 5; /* imm6 */
77 offset += (insn & 0x00002000) << 4; /* J1 */
78 offset += (insn & 0x00000800) << 7; /* J2 */
79 offset -= (insn & 0x04000000) >> 7; /* Apply sign bit */
81 regs->ARM_pc = pc + (offset * 2);
84 static enum kprobe_insn __kprobes
85 t32_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
87 int cc = (insn >> 22) & 0xf;
88 asi->insn_check_cc = kprobe_condition_checks[cc];
89 asi->insn_handler = t32_simulate_cond_branch;
90 return INSN_GOOD_NO_SLOT;
94 t32_simulate_branch(struct kprobe *p, struct pt_regs *regs)
96 kprobe_opcode_t insn = p->opcode;
97 unsigned long pc = thumb_probe_pc(p);
99 long offset = insn & 0x7ff; /* imm11 */
100 offset += (insn & 0x03ff0000) >> 5; /* imm10 */
101 offset += (insn & 0x00002000) << 9; /* J1 */
102 offset += (insn & 0x00000800) << 10; /* J2 */
103 if (insn & 0x04000000)
104 offset -= 0x00800000; /* Apply sign bit */
106 offset ^= 0x00600000; /* Invert J1 and J2 */
108 if (insn & (1 << 14)) {
110 regs->ARM_lr = (unsigned long)p->addr + 4;
111 if (!(insn & (1 << 12))) {
112 /* BLX so switch to ARM mode */
113 regs->ARM_cpsr &= ~PSR_T_BIT;
118 regs->ARM_pc = pc + (offset * 2);
121 static void __kprobes
122 t32_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
124 kprobe_opcode_t insn = p->opcode;
125 unsigned long addr = thumb_probe_pc(p) & ~3;
126 int rt = (insn >> 12) & 0xf;
129 long offset = insn & 0xfff;
130 if (insn & 0x00800000)
135 if (insn & 0x00400000) {
137 rtv = *(unsigned long *)addr;
139 bx_write_pc(rtv, regs);
142 } else if (insn & 0x00200000) {
144 if (insn & 0x01000000)
150 if (insn & 0x01000000)
156 regs->uregs[rt] = rtv;
159 static enum kprobe_insn __kprobes
160 t32_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
162 enum kprobe_insn ret = kprobe_decode_ldmstm(insn, asi);
164 /* Fixup modified instruction to have halfwords in correct order...*/
166 ((u16 *)asi->insn)[0] = insn >> 16;
167 ((u16 *)asi->insn)[1] = insn & 0xffff;
172 static void __kprobes
173 t32_emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
175 kprobe_opcode_t insn = p->opcode;
176 unsigned long pc = thumb_probe_pc(p) & ~3;
177 int rt1 = (insn >> 12) & 0xf;
178 int rt2 = (insn >> 8) & 0xf;
179 int rn = (insn >> 16) & 0xf;
181 register unsigned long rt1v asm("r0") = regs->uregs[rt1];
182 register unsigned long rt2v asm("r1") = regs->uregs[rt2];
183 register unsigned long rnv asm("r2") = (rn == 15) ? pc
186 __asm__ __volatile__ (
188 : "=r" (rt1v), "=r" (rt2v), "=r" (rnv)
189 : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (p->ainsn.insn_fn)
190 : "lr", "memory", "cc"
194 regs->uregs[rn] = rnv; /* Writeback base register */
195 regs->uregs[rt1] = rt1v;
196 regs->uregs[rt2] = rt2v;
199 static void __kprobes
200 t32_emulate_ldrstr(struct kprobe *p, struct pt_regs *regs)
202 kprobe_opcode_t insn = p->opcode;
203 int rt = (insn >> 12) & 0xf;
204 int rn = (insn >> 16) & 0xf;
207 register unsigned long rtv asm("r0") = regs->uregs[rt];
208 register unsigned long rnv asm("r2") = regs->uregs[rn];
209 register unsigned long rmv asm("r3") = regs->uregs[rm];
211 __asm__ __volatile__ (
213 : "=r" (rtv), "=r" (rnv)
214 : "0" (rtv), "1" (rnv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn)
215 : "lr", "memory", "cc"
218 regs->uregs[rn] = rnv; /* Writeback base register */
219 if (rt == 15) /* Can't be true for a STR as they aren't allowed */
220 bx_write_pc(rtv, regs);
222 regs->uregs[rt] = rtv;
225 static void __kprobes
226 t32_emulate_rd8rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
228 kprobe_opcode_t insn = p->opcode;
229 int rd = (insn >> 8) & 0xf;
230 int rn = (insn >> 16) & 0xf;
233 register unsigned long rdv asm("r1") = regs->uregs[rd];
234 register unsigned long rnv asm("r2") = regs->uregs[rn];
235 register unsigned long rmv asm("r3") = regs->uregs[rm];
236 unsigned long cpsr = regs->ARM_cpsr;
238 __asm__ __volatile__ (
239 "msr cpsr_fs, %[cpsr] \n\t"
241 "mrs %[cpsr], cpsr \n\t"
242 : "=r" (rdv), [cpsr] "=r" (cpsr)
243 : "0" (rdv), "r" (rnv), "r" (rmv),
244 "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
245 : "lr", "memory", "cc"
248 regs->uregs[rd] = rdv;
249 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
252 static void __kprobes
253 t32_emulate_rd8pc16_noflags(struct kprobe *p, struct pt_regs *regs)
255 kprobe_opcode_t insn = p->opcode;
256 unsigned long pc = thumb_probe_pc(p);
257 int rd = (insn >> 8) & 0xf;
259 register unsigned long rdv asm("r1") = regs->uregs[rd];
260 register unsigned long rnv asm("r2") = pc & ~3;
262 __asm__ __volatile__ (
265 : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
266 : "lr", "memory", "cc"
269 regs->uregs[rd] = rdv;
272 static void __kprobes
273 t32_emulate_rd8rn16_noflags(struct kprobe *p, struct pt_regs *regs)
275 kprobe_opcode_t insn = p->opcode;
276 int rd = (insn >> 8) & 0xf;
277 int rn = (insn >> 16) & 0xf;
279 register unsigned long rdv asm("r1") = regs->uregs[rd];
280 register unsigned long rnv asm("r2") = regs->uregs[rn];
282 __asm__ __volatile__ (
285 : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
286 : "lr", "memory", "cc"
289 regs->uregs[rd] = rdv;
292 static const union decode_item t32_table_1110_100x_x0xx[] = {
293 /* Load/store multiple instructions */
295 /* Rn is PC 1110 100x x0xx 1111 xxxx xxxx xxxx xxxx */
296 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
298 /* SRS 1110 1000 00x0 xxxx xxxx xxxx xxxx xxxx */
299 /* RFE 1110 1000 00x1 xxxx xxxx xxxx xxxx xxxx */
300 DECODE_REJECT (0xffc00000, 0xe8000000),
301 /* SRS 1110 1001 10x0 xxxx xxxx xxxx xxxx xxxx */
302 /* RFE 1110 1001 10x1 xxxx xxxx xxxx xxxx xxxx */
303 DECODE_REJECT (0xffc00000, 0xe9800000),
305 /* STM Rn, {...pc} 1110 100x x0x0 xxxx 1xxx xxxx xxxx xxxx */
306 DECODE_REJECT (0xfe508000, 0xe8008000),
307 /* LDM Rn, {...lr,pc} 1110 100x x0x1 xxxx 11xx xxxx xxxx xxxx */
308 DECODE_REJECT (0xfe50c000, 0xe810c000),
309 /* LDM/STM Rn, {...sp} 1110 100x x0xx xxxx xx1x xxxx xxxx xxxx */
310 DECODE_REJECT (0xfe402000, 0xe8002000),
312 /* STMIA 1110 1000 10x0 xxxx xxxx xxxx xxxx xxxx */
313 /* LDMIA 1110 1000 10x1 xxxx xxxx xxxx xxxx xxxx */
314 /* STMDB 1110 1001 00x0 xxxx xxxx xxxx xxxx xxxx */
315 /* LDMDB 1110 1001 00x1 xxxx xxxx xxxx xxxx xxxx */
316 DECODE_CUSTOM (0xfe400000, 0xe8000000, t32_decode_ldmstm),
321 static const union decode_item t32_table_1110_100x_x1xx[] = {
322 /* Load/store dual, load/store exclusive, table branch */
324 /* STRD (immediate) 1110 1000 x110 xxxx xxxx xxxx xxxx xxxx */
325 /* LDRD (immediate) 1110 1000 x111 xxxx xxxx xxxx xxxx xxxx */
326 DECODE_OR (0xff600000, 0xe8600000),
327 /* STRD (immediate) 1110 1001 x1x0 xxxx xxxx xxxx xxxx xxxx */
328 /* LDRD (immediate) 1110 1001 x1x1 xxxx xxxx xxxx xxxx xxxx */
329 DECODE_EMULATEX (0xff400000, 0xe9400000, t32_emulate_ldrdstrd,
330 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
332 /* TBB 1110 1000 1101 xxxx xxxx xxxx 0000 xxxx */
333 /* TBH 1110 1000 1101 xxxx xxxx xxxx 0001 xxxx */
334 DECODE_SIMULATEX(0xfff000e0, 0xe8d00000, t32_simulate_table_branch,
335 REGS(NOSP, 0, 0, 0, NOSPPC)),
337 /* STREX 1110 1000 0100 xxxx xxxx xxxx xxxx xxxx */
338 /* LDREX 1110 1000 0101 xxxx xxxx xxxx xxxx xxxx */
339 /* STREXB 1110 1000 1100 xxxx xxxx xxxx 0100 xxxx */
340 /* STREXH 1110 1000 1100 xxxx xxxx xxxx 0101 xxxx */
341 /* STREXD 1110 1000 1100 xxxx xxxx xxxx 0111 xxxx */
342 /* LDREXB 1110 1000 1101 xxxx xxxx xxxx 0100 xxxx */
343 /* LDREXH 1110 1000 1101 xxxx xxxx xxxx 0101 xxxx */
344 /* LDREXD 1110 1000 1101 xxxx xxxx xxxx 0111 xxxx */
345 /* And unallocated instructions... */
349 static const union decode_item t32_table_1110_101x[] = {
350 /* Data-processing (shifted register) */
352 /* TST 1110 1010 0001 xxxx xxxx 1111 xxxx xxxx */
353 /* TEQ 1110 1010 1001 xxxx xxxx 1111 xxxx xxxx */
354 DECODE_EMULATEX (0xff700f00, 0xea100f00, t32_emulate_rd8rn16rm0_rwflags,
355 REGS(NOSPPC, 0, 0, 0, NOSPPC)),
357 /* CMN 1110 1011 0001 xxxx xxxx 1111 xxxx xxxx */
358 DECODE_OR (0xfff00f00, 0xeb100f00),
359 /* CMP 1110 1011 1011 xxxx xxxx 1111 xxxx xxxx */
360 DECODE_EMULATEX (0xfff00f00, 0xebb00f00, t32_emulate_rd8rn16rm0_rwflags,
361 REGS(NOPC, 0, 0, 0, NOSPPC)),
363 /* MOV 1110 1010 010x 1111 xxxx xxxx xxxx xxxx */
364 /* MVN 1110 1010 011x 1111 xxxx xxxx xxxx xxxx */
365 DECODE_EMULATEX (0xffcf0000, 0xea4f0000, t32_emulate_rd8rn16rm0_rwflags,
366 REGS(0, 0, NOSPPC, 0, NOSPPC)),
368 /* ??? 1110 1010 101x xxxx xxxx xxxx xxxx xxxx */
369 /* ??? 1110 1010 111x xxxx xxxx xxxx xxxx xxxx */
370 DECODE_REJECT (0xffa00000, 0xeaa00000),
371 /* ??? 1110 1011 001x xxxx xxxx xxxx xxxx xxxx */
372 DECODE_REJECT (0xffe00000, 0xeb200000),
373 /* ??? 1110 1011 100x xxxx xxxx xxxx xxxx xxxx */
374 DECODE_REJECT (0xffe00000, 0xeb800000),
375 /* ??? 1110 1011 111x xxxx xxxx xxxx xxxx xxxx */
376 DECODE_REJECT (0xffe00000, 0xebe00000),
378 /* ADD/SUB SP, SP, Rm, LSL #0..3 */
379 /* 1110 1011 x0xx 1101 x000 1101 xx00 xxxx */
380 DECODE_EMULATEX (0xff4f7f30, 0xeb0d0d00, t32_emulate_rd8rn16rm0_rwflags,
381 REGS(SP, 0, SP, 0, NOSPPC)),
383 /* ADD/SUB SP, SP, Rm, shift */
384 /* 1110 1011 x0xx 1101 xxxx 1101 xxxx xxxx */
385 DECODE_REJECT (0xff4f0f00, 0xeb0d0d00),
387 /* ADD/SUB Rd, SP, Rm, shift */
388 /* 1110 1011 x0xx 1101 xxxx xxxx xxxx xxxx */
389 DECODE_EMULATEX (0xff4f0000, 0xeb0d0000, t32_emulate_rd8rn16rm0_rwflags,
390 REGS(SP, 0, NOPC, 0, NOSPPC)),
392 /* AND 1110 1010 000x xxxx xxxx xxxx xxxx xxxx */
393 /* BIC 1110 1010 001x xxxx xxxx xxxx xxxx xxxx */
394 /* ORR 1110 1010 010x xxxx xxxx xxxx xxxx xxxx */
395 /* ORN 1110 1010 011x xxxx xxxx xxxx xxxx xxxx */
396 /* EOR 1110 1010 100x xxxx xxxx xxxx xxxx xxxx */
397 /* PKH 1110 1010 110x xxxx xxxx xxxx xxxx xxxx */
398 /* ADD 1110 1011 000x xxxx xxxx xxxx xxxx xxxx */
399 /* ADC 1110 1011 010x xxxx xxxx xxxx xxxx xxxx */
400 /* SBC 1110 1011 011x xxxx xxxx xxxx xxxx xxxx */
401 /* SUB 1110 1011 101x xxxx xxxx xxxx xxxx xxxx */
402 /* RSB 1110 1011 110x xxxx xxxx xxxx xxxx xxxx */
403 DECODE_EMULATEX (0xfe000000, 0xea000000, t32_emulate_rd8rn16rm0_rwflags,
404 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
409 static const union decode_item t32_table_1111_0x0x___0[] = {
410 /* Data-processing (modified immediate) */
412 /* TST 1111 0x00 0001 xxxx 0xxx 1111 xxxx xxxx */
413 /* TEQ 1111 0x00 1001 xxxx 0xxx 1111 xxxx xxxx */
414 DECODE_EMULATEX (0xfb708f00, 0xf0100f00, t32_emulate_rd8rn16rm0_rwflags,
415 REGS(NOSPPC, 0, 0, 0, 0)),
417 /* CMN 1111 0x01 0001 xxxx 0xxx 1111 xxxx xxxx */
418 DECODE_OR (0xfbf08f00, 0xf1100f00),
419 /* CMP 1111 0x01 1011 xxxx 0xxx 1111 xxxx xxxx */
420 DECODE_EMULATEX (0xfbf08f00, 0xf1b00f00, t32_emulate_rd8rn16rm0_rwflags,
421 REGS(NOPC, 0, 0, 0, 0)),
423 /* MOV 1111 0x00 010x 1111 0xxx xxxx xxxx xxxx */
424 /* MVN 1111 0x00 011x 1111 0xxx xxxx xxxx xxxx */
425 DECODE_EMULATEX (0xfbcf8000, 0xf04f0000, t32_emulate_rd8rn16rm0_rwflags,
426 REGS(0, 0, NOSPPC, 0, 0)),
428 /* ??? 1111 0x00 101x xxxx 0xxx xxxx xxxx xxxx */
429 DECODE_REJECT (0xfbe08000, 0xf0a00000),
430 /* ??? 1111 0x00 110x xxxx 0xxx xxxx xxxx xxxx */
431 /* ??? 1111 0x00 111x xxxx 0xxx xxxx xxxx xxxx */
432 DECODE_REJECT (0xfbc08000, 0xf0c00000),
433 /* ??? 1111 0x01 001x xxxx 0xxx xxxx xxxx xxxx */
434 DECODE_REJECT (0xfbe08000, 0xf1200000),
435 /* ??? 1111 0x01 100x xxxx 0xxx xxxx xxxx xxxx */
436 DECODE_REJECT (0xfbe08000, 0xf1800000),
437 /* ??? 1111 0x01 111x xxxx 0xxx xxxx xxxx xxxx */
438 DECODE_REJECT (0xfbe08000, 0xf1e00000),
440 /* ADD Rd, SP, #imm 1111 0x01 000x 1101 0xxx xxxx xxxx xxxx */
441 /* SUB Rd, SP, #imm 1111 0x01 101x 1101 0xxx xxxx xxxx xxxx */
442 DECODE_EMULATEX (0xfb4f8000, 0xf10d0000, t32_emulate_rd8rn16rm0_rwflags,
443 REGS(SP, 0, NOPC, 0, 0)),
445 /* AND 1111 0x00 000x xxxx 0xxx xxxx xxxx xxxx */
446 /* BIC 1111 0x00 001x xxxx 0xxx xxxx xxxx xxxx */
447 /* ORR 1111 0x00 010x xxxx 0xxx xxxx xxxx xxxx */
448 /* ORN 1111 0x00 011x xxxx 0xxx xxxx xxxx xxxx */
449 /* EOR 1111 0x00 100x xxxx 0xxx xxxx xxxx xxxx */
450 /* ADD 1111 0x01 000x xxxx 0xxx xxxx xxxx xxxx */
451 /* ADC 1111 0x01 010x xxxx 0xxx xxxx xxxx xxxx */
452 /* SBC 1111 0x01 011x xxxx 0xxx xxxx xxxx xxxx */
453 /* SUB 1111 0x01 101x xxxx 0xxx xxxx xxxx xxxx */
454 /* RSB 1111 0x01 110x xxxx 0xxx xxxx xxxx xxxx */
455 DECODE_EMULATEX (0xfa008000, 0xf0000000, t32_emulate_rd8rn16rm0_rwflags,
456 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
461 static const union decode_item t32_table_1111_0x1x___0[] = {
462 /* Data-processing (plain binary immediate) */
464 /* ADDW Rd, PC, #imm 1111 0x10 0000 1111 0xxx xxxx xxxx xxxx */
465 DECODE_OR (0xfbff8000, 0xf20f0000),
466 /* SUBW Rd, PC, #imm 1111 0x10 1010 1111 0xxx xxxx xxxx xxxx */
467 DECODE_EMULATEX (0xfbff8000, 0xf2af0000, t32_emulate_rd8pc16_noflags,
468 REGS(PC, 0, NOSPPC, 0, 0)),
470 /* ADDW SP, SP, #imm 1111 0x10 0000 1101 0xxx 1101 xxxx xxxx */
471 DECODE_OR (0xfbff8f00, 0xf20d0d00),
472 /* SUBW SP, SP, #imm 1111 0x10 1010 1101 0xxx 1101 xxxx xxxx */
473 DECODE_EMULATEX (0xfbff8f00, 0xf2ad0d00, t32_emulate_rd8rn16_noflags,
474 REGS(SP, 0, SP, 0, 0)),
476 /* ADDW 1111 0x10 0000 xxxx 0xxx xxxx xxxx xxxx */
477 DECODE_OR (0xfbf08000, 0xf2000000),
478 /* SUBW 1111 0x10 1010 xxxx 0xxx xxxx xxxx xxxx */
479 DECODE_EMULATEX (0xfbf08000, 0xf2a00000, t32_emulate_rd8rn16_noflags,
480 REGS(NOPCX, 0, NOSPPC, 0, 0)),
482 /* MOVW 1111 0x10 0100 xxxx 0xxx xxxx xxxx xxxx */
483 /* MOVT 1111 0x10 1100 xxxx 0xxx xxxx xxxx xxxx */
484 DECODE_EMULATEX (0xfb708000, 0xf2400000, t32_emulate_rd8rn16_noflags,
485 REGS(0, 0, NOSPPC, 0, 0)),
487 /* SSAT16 1111 0x11 0010 xxxx 0000 xxxx 00xx xxxx */
488 /* SSAT 1111 0x11 00x0 xxxx 0xxx xxxx xxxx xxxx */
489 /* USAT16 1111 0x11 1010 xxxx 0000 xxxx 00xx xxxx */
490 /* USAT 1111 0x11 10x0 xxxx 0xxx xxxx xxxx xxxx */
491 DECODE_EMULATEX (0xfb508000, 0xf3000000, t32_emulate_rd8rn16rm0_rwflags,
492 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
494 /* SFBX 1111 0x11 0100 xxxx 0xxx xxxx xxxx xxxx */
495 /* UFBX 1111 0x11 1100 xxxx 0xxx xxxx xxxx xxxx */
496 DECODE_EMULATEX (0xfb708000, 0xf3400000, t32_emulate_rd8rn16_noflags,
497 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
499 /* BFC 1111 0x11 0110 1111 0xxx xxxx xxxx xxxx */
500 DECODE_EMULATEX (0xfbff8000, 0xf36f0000, t32_emulate_rd8rn16_noflags,
501 REGS(0, 0, NOSPPC, 0, 0)),
503 /* BFI 1111 0x11 0110 xxxx 0xxx xxxx xxxx xxxx */
504 DECODE_EMULATEX (0xfbf08000, 0xf3600000, t32_emulate_rd8rn16_noflags,
505 REGS(NOSPPCX, 0, NOSPPC, 0, 0)),
510 static const union decode_item t32_table_1111_0xxx___1[] = {
511 /* Branches and miscellaneous control */
513 /* YIELD 1111 0011 1010 xxxx 10x0 x000 0000 0001 */
514 DECODE_OR (0xfff0d7ff, 0xf3a08001),
515 /* SEV 1111 0011 1010 xxxx 10x0 x000 0000 0100 */
516 DECODE_EMULATE (0xfff0d7ff, 0xf3a08004, kprobe_emulate_none),
517 /* NOP 1111 0011 1010 xxxx 10x0 x000 0000 0000 */
518 /* WFE 1111 0011 1010 xxxx 10x0 x000 0000 0010 */
519 /* WFI 1111 0011 1010 xxxx 10x0 x000 0000 0011 */
520 DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, kprobe_simulate_nop),
522 /* MRS Rd, CPSR 1111 0011 1110 xxxx 10x0 xxxx xxxx xxxx */
523 DECODE_SIMULATEX(0xfff0d000, 0xf3e08000, t32_simulate_mrs,
524 REGS(0, 0, NOSPPC, 0, 0)),
527 * Unsupported instructions
528 * 1111 0x11 1xxx xxxx 10x0 xxxx xxxx xxxx
530 * MSR 1111 0011 100x xxxx 10x0 xxxx xxxx xxxx
531 * DBG hint 1111 0011 1010 xxxx 10x0 x000 1111 xxxx
532 * Unallocated hints 1111 0011 1010 xxxx 10x0 x000 xxxx xxxx
533 * CPS 1111 0011 1010 xxxx 10x0 xxxx xxxx xxxx
534 * CLREX/DSB/DMB/ISB 1111 0011 1011 xxxx 10x0 xxxx xxxx xxxx
535 * BXJ 1111 0011 1100 xxxx 10x0 xxxx xxxx xxxx
536 * SUBS PC,LR,#<imm8> 1111 0011 1101 xxxx 10x0 xxxx xxxx xxxx
537 * MRS Rd, SPSR 1111 0011 1111 xxxx 10x0 xxxx xxxx xxxx
538 * SMC 1111 0111 1111 xxxx 1000 xxxx xxxx xxxx
539 * UNDEFINED 1111 0111 1111 xxxx 1010 xxxx xxxx xxxx
540 * ??? 1111 0111 1xxx xxxx 1010 xxxx xxxx xxxx
542 DECODE_REJECT (0xfb80d000, 0xf3808000),
544 /* Bcc 1111 0xxx xxxx xxxx 10x0 xxxx xxxx xxxx */
545 DECODE_CUSTOM (0xf800d000, 0xf0008000, t32_decode_cond_branch),
547 /* BLX 1111 0xxx xxxx xxxx 11x0 xxxx xxxx xxx0 */
548 DECODE_OR (0xf800d001, 0xf000c000),
549 /* B 1111 0xxx xxxx xxxx 10x1 xxxx xxxx xxxx */
550 /* BL 1111 0xxx xxxx xxxx 11x1 xxxx xxxx xxxx */
551 DECODE_SIMULATE (0xf8009000, 0xf0009000, t32_simulate_branch),
556 static const union decode_item t32_table_1111_100x_x0x1__1111[] = {
559 /* PLD (literal) 1111 1000 x001 1111 1111 xxxx xxxx xxxx */
560 /* PLI (literal) 1111 1001 x001 1111 1111 xxxx xxxx xxxx */
561 DECODE_SIMULATE (0xfe7ff000, 0xf81ff000, kprobe_simulate_nop),
563 /* PLD{W} (immediate) 1111 1000 10x1 xxxx 1111 xxxx xxxx xxxx */
564 DECODE_OR (0xffd0f000, 0xf890f000),
565 /* PLD{W} (immediate) 1111 1000 00x1 xxxx 1111 1100 xxxx xxxx */
566 DECODE_OR (0xffd0ff00, 0xf810fc00),
567 /* PLI (immediate) 1111 1001 1001 xxxx 1111 xxxx xxxx xxxx */
568 DECODE_OR (0xfff0f000, 0xf990f000),
569 /* PLI (immediate) 1111 1001 0001 xxxx 1111 1100 xxxx xxxx */
570 DECODE_SIMULATEX(0xfff0ff00, 0xf910fc00, kprobe_simulate_nop,
571 REGS(NOPCX, 0, 0, 0, 0)),
573 /* PLD{W} (register) 1111 1000 00x1 xxxx 1111 0000 00xx xxxx */
574 DECODE_OR (0xffd0ffc0, 0xf810f000),
575 /* PLI (register) 1111 1001 0001 xxxx 1111 0000 00xx xxxx */
576 DECODE_SIMULATEX(0xfff0ffc0, 0xf910f000, kprobe_simulate_nop,
577 REGS(NOPCX, 0, 0, 0, NOSPPC)),
579 /* Other unallocated instructions... */
583 static const union decode_item t32_table_1111_100x[] = {
584 /* Store/Load single data item */
586 /* ??? 1111 100x x11x xxxx xxxx xxxx xxxx xxxx */
587 DECODE_REJECT (0xfe600000, 0xf8600000),
589 /* ??? 1111 1001 0101 xxxx xxxx xxxx xxxx xxxx */
590 DECODE_REJECT (0xfff00000, 0xf9500000),
592 /* ??? 1111 100x 0xxx xxxx xxxx 10x0 xxxx xxxx */
593 DECODE_REJECT (0xfe800d00, 0xf8000800),
595 /* STRBT 1111 1000 0000 xxxx xxxx 1110 xxxx xxxx */
596 /* STRHT 1111 1000 0010 xxxx xxxx 1110 xxxx xxxx */
597 /* STRT 1111 1000 0100 xxxx xxxx 1110 xxxx xxxx */
598 /* LDRBT 1111 1000 0001 xxxx xxxx 1110 xxxx xxxx */
599 /* LDRSBT 1111 1001 0001 xxxx xxxx 1110 xxxx xxxx */
600 /* LDRHT 1111 1000 0011 xxxx xxxx 1110 xxxx xxxx */
601 /* LDRSHT 1111 1001 0011 xxxx xxxx 1110 xxxx xxxx */
602 /* LDRT 1111 1000 0101 xxxx xxxx 1110 xxxx xxxx */
603 DECODE_REJECT (0xfe800f00, 0xf8000e00),
605 /* STR{,B,H} Rn,[PC...] 1111 1000 xxx0 1111 xxxx xxxx xxxx xxxx */
606 DECODE_REJECT (0xff1f0000, 0xf80f0000),
608 /* STR{,B,H} PC,[Rn...] 1111 1000 xxx0 xxxx 1111 xxxx xxxx xxxx */
609 DECODE_REJECT (0xff10f000, 0xf800f000),
611 /* LDR (literal) 1111 1000 x101 1111 xxxx xxxx xxxx xxxx */
612 DECODE_SIMULATEX(0xff7f0000, 0xf85f0000, t32_simulate_ldr_literal,
613 REGS(PC, ANY, 0, 0, 0)),
615 /* STR (immediate) 1111 1000 0100 xxxx xxxx 1xxx xxxx xxxx */
616 /* LDR (immediate) 1111 1000 0101 xxxx xxxx 1xxx xxxx xxxx */
617 DECODE_OR (0xffe00800, 0xf8400800),
618 /* STR (immediate) 1111 1000 1100 xxxx xxxx xxxx xxxx xxxx */
619 /* LDR (immediate) 1111 1000 1101 xxxx xxxx xxxx xxxx xxxx */
620 DECODE_EMULATEX (0xffe00000, 0xf8c00000, t32_emulate_ldrstr,
621 REGS(NOPCX, ANY, 0, 0, 0)),
623 /* STR (register) 1111 1000 0100 xxxx xxxx 0000 00xx xxxx */
624 /* LDR (register) 1111 1000 0101 xxxx xxxx 0000 00xx xxxx */
625 DECODE_EMULATEX (0xffe00fc0, 0xf8400000, t32_emulate_ldrstr,
626 REGS(NOPCX, ANY, 0, 0, NOSPPC)),
628 /* LDRB (literal) 1111 1000 x001 1111 xxxx xxxx xxxx xxxx */
629 /* LDRSB (literal) 1111 1001 x001 1111 xxxx xxxx xxxx xxxx */
630 /* LDRH (literal) 1111 1000 x011 1111 xxxx xxxx xxxx xxxx */
631 /* LDRSH (literal) 1111 1001 x011 1111 xxxx xxxx xxxx xxxx */
632 DECODE_EMULATEX (0xfe5f0000, 0xf81f0000, t32_simulate_ldr_literal,
633 REGS(PC, NOSPPCX, 0, 0, 0)),
635 /* STRB (immediate) 1111 1000 0000 xxxx xxxx 1xxx xxxx xxxx */
636 /* STRH (immediate) 1111 1000 0010 xxxx xxxx 1xxx xxxx xxxx */
637 /* LDRB (immediate) 1111 1000 0001 xxxx xxxx 1xxx xxxx xxxx */
638 /* LDRSB (immediate) 1111 1001 0001 xxxx xxxx 1xxx xxxx xxxx */
639 /* LDRH (immediate) 1111 1000 0011 xxxx xxxx 1xxx xxxx xxxx */
640 /* LDRSH (immediate) 1111 1001 0011 xxxx xxxx 1xxx xxxx xxxx */
641 DECODE_OR (0xfec00800, 0xf8000800),
642 /* STRB (immediate) 1111 1000 1000 xxxx xxxx xxxx xxxx xxxx */
643 /* STRH (immediate) 1111 1000 1010 xxxx xxxx xxxx xxxx xxxx */
644 /* LDRB (immediate) 1111 1000 1001 xxxx xxxx xxxx xxxx xxxx */
645 /* LDRSB (immediate) 1111 1001 1001 xxxx xxxx xxxx xxxx xxxx */
646 /* LDRH (immediate) 1111 1000 1011 xxxx xxxx xxxx xxxx xxxx */
647 /* LDRSH (immediate) 1111 1001 1011 xxxx xxxx xxxx xxxx xxxx */
648 DECODE_EMULATEX (0xfec00000, 0xf8800000, t32_emulate_ldrstr,
649 REGS(NOPCX, NOSPPCX, 0, 0, 0)),
651 /* STRB (register) 1111 1000 0000 xxxx xxxx 0000 00xx xxxx */
652 /* STRH (register) 1111 1000 0010 xxxx xxxx 0000 00xx xxxx */
653 /* LDRB (register) 1111 1000 0001 xxxx xxxx 0000 00xx xxxx */
654 /* LDRSB (register) 1111 1001 0001 xxxx xxxx 0000 00xx xxxx */
655 /* LDRH (register) 1111 1000 0011 xxxx xxxx 0000 00xx xxxx */
656 /* LDRSH (register) 1111 1001 0011 xxxx xxxx 0000 00xx xxxx */
657 DECODE_EMULATEX (0xfe800fc0, 0xf8000000, t32_emulate_ldrstr,
658 REGS(NOPCX, NOSPPCX, 0, 0, NOSPPC)),
660 /* Other unallocated instructions... */
664 static const union decode_item t32_table_1111_1010___1111[] = {
665 /* Data-processing (register) */
667 /* ??? 1111 1010 011x xxxx 1111 xxxx 1xxx xxxx */
668 DECODE_REJECT (0xffe0f080, 0xfa60f080),
670 /* SXTH 1111 1010 0000 1111 1111 xxxx 1xxx xxxx */
671 /* UXTH 1111 1010 0001 1111 1111 xxxx 1xxx xxxx */
672 /* SXTB16 1111 1010 0010 1111 1111 xxxx 1xxx xxxx */
673 /* UXTB16 1111 1010 0011 1111 1111 xxxx 1xxx xxxx */
674 /* SXTB 1111 1010 0100 1111 1111 xxxx 1xxx xxxx */
675 /* UXTB 1111 1010 0101 1111 1111 xxxx 1xxx xxxx */
676 DECODE_EMULATEX (0xff8ff080, 0xfa0ff080, t32_emulate_rd8rn16rm0_rwflags,
677 REGS(0, 0, NOSPPC, 0, NOSPPC)),
680 /* ??? 1111 1010 1xxx xxxx 1111 xxxx 0x11 xxxx */
681 DECODE_REJECT (0xff80f0b0, 0xfa80f030),
682 /* ??? 1111 1010 1x11 xxxx 1111 xxxx 0xxx xxxx */
683 DECODE_REJECT (0xffb0f080, 0xfab0f000),
685 /* SADD16 1111 1010 1001 xxxx 1111 xxxx 0000 xxxx */
686 /* SASX 1111 1010 1010 xxxx 1111 xxxx 0000 xxxx */
687 /* SSAX 1111 1010 1110 xxxx 1111 xxxx 0000 xxxx */
688 /* SSUB16 1111 1010 1101 xxxx 1111 xxxx 0000 xxxx */
689 /* SADD8 1111 1010 1000 xxxx 1111 xxxx 0000 xxxx */
690 /* SSUB8 1111 1010 1100 xxxx 1111 xxxx 0000 xxxx */
692 /* QADD16 1111 1010 1001 xxxx 1111 xxxx 0001 xxxx */
693 /* QASX 1111 1010 1010 xxxx 1111 xxxx 0001 xxxx */
694 /* QSAX 1111 1010 1110 xxxx 1111 xxxx 0001 xxxx */
695 /* QSUB16 1111 1010 1101 xxxx 1111 xxxx 0001 xxxx */
696 /* QADD8 1111 1010 1000 xxxx 1111 xxxx 0001 xxxx */
697 /* QSUB8 1111 1010 1100 xxxx 1111 xxxx 0001 xxxx */
699 /* SHADD16 1111 1010 1001 xxxx 1111 xxxx 0010 xxxx */
700 /* SHASX 1111 1010 1010 xxxx 1111 xxxx 0010 xxxx */
701 /* SHSAX 1111 1010 1110 xxxx 1111 xxxx 0010 xxxx */
702 /* SHSUB16 1111 1010 1101 xxxx 1111 xxxx 0010 xxxx */
703 /* SHADD8 1111 1010 1000 xxxx 1111 xxxx 0010 xxxx */
704 /* SHSUB8 1111 1010 1100 xxxx 1111 xxxx 0010 xxxx */
706 /* UADD16 1111 1010 1001 xxxx 1111 xxxx 0100 xxxx */
707 /* UASX 1111 1010 1010 xxxx 1111 xxxx 0100 xxxx */
708 /* USAX 1111 1010 1110 xxxx 1111 xxxx 0100 xxxx */
709 /* USUB16 1111 1010 1101 xxxx 1111 xxxx 0100 xxxx */
710 /* UADD8 1111 1010 1000 xxxx 1111 xxxx 0100 xxxx */
711 /* USUB8 1111 1010 1100 xxxx 1111 xxxx 0100 xxxx */
713 /* UQADD16 1111 1010 1001 xxxx 1111 xxxx 0101 xxxx */
714 /* UQASX 1111 1010 1010 xxxx 1111 xxxx 0101 xxxx */
715 /* UQSAX 1111 1010 1110 xxxx 1111 xxxx 0101 xxxx */
716 /* UQSUB16 1111 1010 1101 xxxx 1111 xxxx 0101 xxxx */
717 /* UQADD8 1111 1010 1000 xxxx 1111 xxxx 0101 xxxx */
718 /* UQSUB8 1111 1010 1100 xxxx 1111 xxxx 0101 xxxx */
720 /* UHADD16 1111 1010 1001 xxxx 1111 xxxx 0110 xxxx */
721 /* UHASX 1111 1010 1010 xxxx 1111 xxxx 0110 xxxx */
722 /* UHSAX 1111 1010 1110 xxxx 1111 xxxx 0110 xxxx */
723 /* UHSUB16 1111 1010 1101 xxxx 1111 xxxx 0110 xxxx */
724 /* UHADD8 1111 1010 1000 xxxx 1111 xxxx 0110 xxxx */
725 /* UHSUB8 1111 1010 1100 xxxx 1111 xxxx 0110 xxxx */
726 DECODE_OR (0xff80f080, 0xfa80f000),
728 /* SXTAH 1111 1010 0000 xxxx 1111 xxxx 1xxx xxxx */
729 /* UXTAH 1111 1010 0001 xxxx 1111 xxxx 1xxx xxxx */
730 /* SXTAB16 1111 1010 0010 xxxx 1111 xxxx 1xxx xxxx */
731 /* UXTAB16 1111 1010 0011 xxxx 1111 xxxx 1xxx xxxx */
732 /* SXTAB 1111 1010 0100 xxxx 1111 xxxx 1xxx xxxx */
733 /* UXTAB 1111 1010 0101 xxxx 1111 xxxx 1xxx xxxx */
734 DECODE_OR (0xff80f080, 0xfa00f080),
736 /* QADD 1111 1010 1000 xxxx 1111 xxxx 1000 xxxx */
737 /* QDADD 1111 1010 1000 xxxx 1111 xxxx 1001 xxxx */
738 /* QSUB 1111 1010 1000 xxxx 1111 xxxx 1010 xxxx */
739 /* QDSUB 1111 1010 1000 xxxx 1111 xxxx 1011 xxxx */
740 DECODE_OR (0xfff0f0c0, 0xfa80f080),
742 /* SEL 1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */
743 DECODE_OR (0xfff0f0f0, 0xfaa0f080),
745 /* LSL 1111 1010 000x xxxx 1111 xxxx 0000 xxxx */
746 /* LSR 1111 1010 001x xxxx 1111 xxxx 0000 xxxx */
747 /* ASR 1111 1010 010x xxxx 1111 xxxx 0000 xxxx */
748 /* ROR 1111 1010 011x xxxx 1111 xxxx 0000 xxxx */
749 DECODE_EMULATEX (0xff80f0f0, 0xfa00f000, t32_emulate_rd8rn16rm0_rwflags,
750 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
752 /* CLZ 1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */
753 DECODE_OR (0xfff0f0f0, 0xfab0f080),
755 /* REV 1111 1010 1001 xxxx 1111 xxxx 1000 xxxx */
756 /* REV16 1111 1010 1001 xxxx 1111 xxxx 1001 xxxx */
757 /* RBIT 1111 1010 1001 xxxx 1111 xxxx 1010 xxxx */
758 /* REVSH 1111 1010 1001 xxxx 1111 xxxx 1011 xxxx */
759 DECODE_EMULATEX (0xfff0f0c0, 0xfa90f080, t32_emulate_rd8rn16_noflags,
760 REGS(NOSPPC, 0, NOSPPC, 0, SAMEAS16)),
762 /* Other unallocated instructions... */
766 const union decode_item kprobe_decode_thumb32_table[] = {
769 * Load/store multiple instructions
770 * 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx
772 DECODE_TABLE (0xfe400000, 0xe8000000, t32_table_1110_100x_x0xx),
775 * Load/store dual, load/store exclusive, table branch
776 * 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx
778 DECODE_TABLE (0xfe400000, 0xe8400000, t32_table_1110_100x_x1xx),
781 * Data-processing (shifted register)
782 * 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx
784 DECODE_TABLE (0xfe000000, 0xea000000, t32_table_1110_101x),
787 * Coprocessor instructions
788 * 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx
790 DECODE_REJECT (0xfc000000, 0xec000000),
793 * Data-processing (modified immediate)
794 * 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx
796 DECODE_TABLE (0xfa008000, 0xf0000000, t32_table_1111_0x0x___0),
799 * Data-processing (plain binary immediate)
800 * 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx
802 DECODE_TABLE (0xfa008000, 0xf2000000, t32_table_1111_0x1x___0),
805 * Branches and miscellaneous control
806 * 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx
808 DECODE_TABLE (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1),
811 * Advanced SIMD element or structure load/store instructions
812 * 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx
814 DECODE_REJECT (0xff100000, 0xf9000000),
818 * 1111 100x x0x1 xxxx 1111 xxxx xxxx xxxx
820 DECODE_TABLE (0xfe50f000, 0xf810f000, t32_table_1111_100x_x0x1__1111),
823 * Store single data item
824 * 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx
825 * Load single data items
826 * 1111 100x xxx1 xxxx xxxx xxxx xxxx xxxx
828 DECODE_TABLE (0xfe000000, 0xf8000000, t32_table_1111_100x),
831 * Data-processing (register)
832 * 1111 1010 xxxx xxxx 1111 xxxx xxxx xxxx
834 DECODE_TABLE (0xff00f000, 0xfa00f000, t32_table_1111_1010___1111),
837 * Coprocessor instructions
838 * 1111 11xx xxxx xxxx xxxx xxxx xxxx xxxx
843 static void __kprobes
844 t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
846 kprobe_opcode_t insn = p->opcode;
847 unsigned long pc = thumb_probe_pc(p);
848 int rm = (insn >> 3) & 0xf;
849 unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];
851 if (insn & (1 << 7)) /* BLX ? */
852 regs->ARM_lr = (unsigned long)p->addr + 2;
854 bx_write_pc(rmv, regs);
857 static void __kprobes
858 t16_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
860 kprobe_opcode_t insn = p->opcode;
861 unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3);
862 long index = insn & 0xff;
863 int rt = (insn >> 8) & 0x7;
864 regs->uregs[rt] = base[index];
867 static void __kprobes
868 t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs)
870 kprobe_opcode_t insn = p->opcode;
871 unsigned long* base = (unsigned long *)regs->ARM_sp;
872 long index = insn & 0xff;
873 int rt = (insn >> 8) & 0x7;
874 if (insn & 0x800) /* LDR */
875 regs->uregs[rt] = base[index];
877 base[index] = regs->uregs[rt];
880 static void __kprobes
881 t16_simulate_reladr(struct kprobe *p, struct pt_regs *regs)
883 kprobe_opcode_t insn = p->opcode;
884 unsigned long base = (insn & 0x800) ? regs->ARM_sp
885 : (thumb_probe_pc(p) & ~3);
886 long offset = insn & 0xff;
887 int rt = (insn >> 8) & 0x7;
888 regs->uregs[rt] = base + offset * 4;
891 static void __kprobes
892 t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs)
894 kprobe_opcode_t insn = p->opcode;
895 long imm = insn & 0x7f;
896 if (insn & 0x80) /* SUB */
897 regs->ARM_sp -= imm * 4;
899 regs->ARM_sp += imm * 4;
902 static void __kprobes
903 t16_simulate_cbz(struct kprobe *p, struct pt_regs *regs)
905 kprobe_opcode_t insn = p->opcode;
907 kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
908 if (nonzero & 0x800) {
909 long i = insn & 0x200;
910 long imm5 = insn & 0xf8;
911 unsigned long pc = thumb_probe_pc(p);
912 regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
916 static void __kprobes
917 t16_simulate_it(struct kprobe *p, struct pt_regs *regs)
920 * The 8 IT state bits are split into two parts in CPSR:
921 * ITSTATE<1:0> are in CPSR<26:25>
922 * ITSTATE<7:2> are in CPSR<15:10>
923 * The new IT state is in the lower byte of insn.
925 kprobe_opcode_t insn = p->opcode;
926 unsigned long cpsr = regs->ARM_cpsr;
927 cpsr &= ~PSR_IT_MASK;
928 cpsr |= (insn & 0xfc) << 8;
929 cpsr |= (insn & 0x03) << 25;
930 regs->ARM_cpsr = cpsr;
933 static void __kprobes
934 t16_singlestep_it(struct kprobe *p, struct pt_regs *regs)
937 t16_simulate_it(p, regs);
940 static enum kprobe_insn __kprobes
941 t16_decode_it(kprobe_opcode_t insn, struct arch_specific_insn *asi)
943 asi->insn_singlestep = t16_singlestep_it;
944 return INSN_GOOD_NO_SLOT;
947 static void __kprobes
948 t16_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
950 kprobe_opcode_t insn = p->opcode;
951 unsigned long pc = thumb_probe_pc(p);
952 long offset = insn & 0x7f;
953 offset -= insn & 0x80; /* Apply sign bit */
954 regs->ARM_pc = pc + (offset * 2);
957 static enum kprobe_insn __kprobes
958 t16_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
960 int cc = (insn >> 8) & 0xf;
961 asi->insn_check_cc = kprobe_condition_checks[cc];
962 asi->insn_handler = t16_simulate_cond_branch;
963 return INSN_GOOD_NO_SLOT;
966 static void __kprobes
967 t16_simulate_branch(struct kprobe *p, struct pt_regs *regs)
969 kprobe_opcode_t insn = p->opcode;
970 unsigned long pc = thumb_probe_pc(p);
971 long offset = insn & 0x3ff;
972 offset -= insn & 0x400; /* Apply sign bit */
973 regs->ARM_pc = pc + (offset * 2);
976 static unsigned long __kprobes
977 t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
979 unsigned long oldcpsr = regs->ARM_cpsr;
980 unsigned long newcpsr;
982 __asm__ __volatile__ (
983 "msr cpsr_fs, %[oldcpsr] \n\t"
984 "ldmia %[regs], {r0-r7} \n\t"
986 "stmia %[regs], {r0-r7} \n\t"
987 "mrs %[newcpsr], cpsr \n\t"
988 : [newcpsr] "=r" (newcpsr)
989 : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
990 [fn] "r" (p->ainsn.insn_fn)
991 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
995 return (oldcpsr & ~APSR_MASK) | (newcpsr & APSR_MASK);
998 static void __kprobes
999 t16_emulate_loregs_rwflags(struct kprobe *p, struct pt_regs *regs)
1001 regs->ARM_cpsr = t16_emulate_loregs(p, regs);
1004 static void __kprobes
1005 t16_emulate_loregs_noitrwflags(struct kprobe *p, struct pt_regs *regs)
1007 unsigned long cpsr = t16_emulate_loregs(p, regs);
1008 if (!in_it_block(cpsr))
1009 regs->ARM_cpsr = cpsr;
1012 static void __kprobes
1013 t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
1015 kprobe_opcode_t insn = p->opcode;
1016 unsigned long pc = thumb_probe_pc(p);
1017 int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
1018 int rm = (insn >> 3) & 0xf;
1020 register unsigned long rdnv asm("r1");
1021 register unsigned long rmv asm("r0");
1022 unsigned long cpsr = regs->ARM_cpsr;
1024 rdnv = (rdn == 15) ? pc : regs->uregs[rdn];
1025 rmv = (rm == 15) ? pc : regs->uregs[rm];
1027 __asm__ __volatile__ (
1028 "msr cpsr_fs, %[cpsr] \n\t"
1030 "mrs %[cpsr], cpsr \n\t"
1031 : "=r" (rdnv), [cpsr] "=r" (cpsr)
1032 : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
1033 : "lr", "memory", "cc"
1039 regs->uregs[rdn] = rdnv;
1040 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
1043 static enum kprobe_insn __kprobes
1044 t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1047 insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
1048 ((u16 *)asi->insn)[0] = insn;
1049 asi->insn_handler = t16_emulate_hiregs;
1053 static void __kprobes
1054 t16_emulate_push(struct kprobe *p, struct pt_regs *regs)
1056 __asm__ __volatile__ (
1057 "ldr r9, [%[regs], #13*4] \n\t"
1058 "ldr r8, [%[regs], #14*4] \n\t"
1059 "ldmia %[regs], {r0-r7} \n\t"
1061 "str r9, [%[regs], #13*4] \n\t"
1063 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
1064 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
1065 "lr", "memory", "cc"
1069 static enum kprobe_insn __kprobes
1070 t16_decode_push(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1073 * To simulate a PUSH we use a Thumb-2 "STMDB R9!, {registers}"
1074 * and call it with R9=SP and LR in the register list represented
1077 ((u16 *)asi->insn)[0] = 0xe929; /* 1st half STMDB R9!,{} */
1078 ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
1079 asi->insn_handler = t16_emulate_push;
1083 static void __kprobes
1084 t16_emulate_pop_nopc(struct kprobe *p, struct pt_regs *regs)
1086 __asm__ __volatile__ (
1087 "ldr r9, [%[regs], #13*4] \n\t"
1088 "ldmia %[regs], {r0-r7} \n\t"
1090 "stmia %[regs], {r0-r7} \n\t"
1091 "str r9, [%[regs], #13*4] \n\t"
1093 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
1094 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
1095 "lr", "memory", "cc"
1099 static void __kprobes
1100 t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
1102 register unsigned long pc asm("r8");
1104 __asm__ __volatile__ (
1105 "ldr r9, [%[regs], #13*4] \n\t"
1106 "ldmia %[regs], {r0-r7} \n\t"
1108 "stmia %[regs], {r0-r7} \n\t"
1109 "str r9, [%[regs], #13*4] \n\t"
1111 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
1112 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
1113 "lr", "memory", "cc"
1116 bx_write_pc(pc, regs);
1119 static enum kprobe_insn __kprobes
1120 t16_decode_pop(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1123 * To simulate a POP we use a Thumb-2 "LDMDB R9!, {registers}"
1124 * and call it with R9=SP and PC in the register list represented
1127 ((u16 *)asi->insn)[0] = 0xe8b9; /* 1st half LDMIA R9!,{} */
1128 ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
1129 asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc
1130 : t16_emulate_pop_nopc;
1134 static const union decode_item t16_table_1011[] = {
1135 /* Miscellaneous 16-bit instructions */
1137 /* ADD (SP plus immediate) 1011 0000 0xxx xxxx */
1138 /* SUB (SP minus immediate) 1011 0000 1xxx xxxx */
1139 DECODE_SIMULATE (0xff00, 0xb000, t16_simulate_add_sp_imm),
1141 /* CBZ 1011 00x1 xxxx xxxx */
1142 /* CBNZ 1011 10x1 xxxx xxxx */
1143 DECODE_SIMULATE (0xf500, 0xb100, t16_simulate_cbz),
1145 /* SXTH 1011 0010 00xx xxxx */
1146 /* SXTB 1011 0010 01xx xxxx */
1147 /* UXTH 1011 0010 10xx xxxx */
1148 /* UXTB 1011 0010 11xx xxxx */
1149 /* REV 1011 1010 00xx xxxx */
1150 /* REV16 1011 1010 01xx xxxx */
1151 /* ??? 1011 1010 10xx xxxx */
1152 /* REVSH 1011 1010 11xx xxxx */
1153 DECODE_REJECT (0xffc0, 0xba80),
1154 DECODE_EMULATE (0xf500, 0xb000, t16_emulate_loregs_rwflags),
1156 /* PUSH 1011 010x xxxx xxxx */
1157 DECODE_CUSTOM (0xfe00, 0xb400, t16_decode_push),
1158 /* POP 1011 110x xxxx xxxx */
1159 DECODE_CUSTOM (0xfe00, 0xbc00, t16_decode_pop),
1162 * If-Then, and hints
1163 * 1011 1111 xxxx xxxx
1166 /* YIELD 1011 1111 0001 0000 */
1167 DECODE_OR (0xffff, 0xbf10),
1168 /* SEV 1011 1111 0100 0000 */
1169 DECODE_EMULATE (0xffff, 0xbf40, kprobe_emulate_none),
1170 /* NOP 1011 1111 0000 0000 */
1171 /* WFE 1011 1111 0010 0000 */
1172 /* WFI 1011 1111 0011 0000 */
1173 DECODE_SIMULATE (0xffcf, 0xbf00, kprobe_simulate_nop),
1174 /* Unassigned hints 1011 1111 xxxx 0000 */
1175 DECODE_REJECT (0xff0f, 0xbf00),
1176 /* IT 1011 1111 xxxx xxxx */
1177 DECODE_CUSTOM (0xff00, 0xbf00, t16_decode_it),
1179 /* SETEND 1011 0110 010x xxxx */
1180 /* CPS 1011 0110 011x xxxx */
1181 /* BKPT 1011 1110 xxxx xxxx */
1182 /* And unallocated instructions... */
1186 const union decode_item kprobe_decode_thumb16_table[] = {
1189 * Shift (immediate), add, subtract, move, and compare
1190 * 00xx xxxx xxxx xxxx
1193 /* CMP (immediate) 0010 1xxx xxxx xxxx */
1194 DECODE_EMULATE (0xf800, 0x2800, t16_emulate_loregs_rwflags),
1196 /* ADD (register) 0001 100x xxxx xxxx */
1197 /* SUB (register) 0001 101x xxxx xxxx */
1198 /* LSL (immediate) 0000 0xxx xxxx xxxx */
1199 /* LSR (immediate) 0000 1xxx xxxx xxxx */
1200 /* ASR (immediate) 0001 0xxx xxxx xxxx */
1201 /* ADD (immediate, Thumb) 0001 110x xxxx xxxx */
1202 /* SUB (immediate, Thumb) 0001 111x xxxx xxxx */
1203 /* MOV (immediate) 0010 0xxx xxxx xxxx */
1204 /* ADD (immediate, Thumb) 0011 0xxx xxxx xxxx */
1205 /* SUB (immediate, Thumb) 0011 1xxx xxxx xxxx */
1206 DECODE_EMULATE (0xc000, 0x0000, t16_emulate_loregs_noitrwflags),
1209 * 16-bit Thumb data-processing instructions
1210 * 0100 00xx xxxx xxxx
1213 /* TST (register) 0100 0010 00xx xxxx */
1214 DECODE_EMULATE (0xffc0, 0x4200, t16_emulate_loregs_rwflags),
1215 /* CMP (register) 0100 0010 10xx xxxx */
1216 /* CMN (register) 0100 0010 11xx xxxx */
1217 DECODE_EMULATE (0xff80, 0x4280, t16_emulate_loregs_rwflags),
1218 /* AND (register) 0100 0000 00xx xxxx */
1219 /* EOR (register) 0100 0000 01xx xxxx */
1220 /* LSL (register) 0100 0000 10xx xxxx */
1221 /* LSR (register) 0100 0000 11xx xxxx */
1222 /* ASR (register) 0100 0001 00xx xxxx */
1223 /* ADC (register) 0100 0001 01xx xxxx */
1224 /* SBC (register) 0100 0001 10xx xxxx */
1225 /* ROR (register) 0100 0001 11xx xxxx */
1226 /* RSB (immediate) 0100 0010 01xx xxxx */
1227 /* ORR (register) 0100 0011 00xx xxxx */
1228 /* MUL 0100 0011 00xx xxxx */
1229 /* BIC (register) 0100 0011 10xx xxxx */
1230 /* MVN (register) 0100 0011 10xx xxxx */
1231 DECODE_EMULATE (0xfc00, 0x4000, t16_emulate_loregs_noitrwflags),
1234 * Special data instructions and branch and exchange
1235 * 0100 01xx xxxx xxxx
1238 /* BLX pc 0100 0111 1111 1xxx */
1239 DECODE_REJECT (0xfff8, 0x47f8),
1241 /* BX (register) 0100 0111 0xxx xxxx */
1242 /* BLX (register) 0100 0111 1xxx xxxx */
1243 DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx),
1245 /* ADD pc, pc 0100 0100 1111 1111 */
1246 DECODE_REJECT (0xffff, 0x44ff),
1248 /* ADD (register) 0100 0100 xxxx xxxx */
1249 /* CMP (register) 0100 0101 xxxx xxxx */
1250 /* MOV (register) 0100 0110 xxxx xxxx */
1251 DECODE_CUSTOM (0xfc00, 0x4400, t16_decode_hiregs),
1254 * Load from Literal Pool
1255 * LDR (literal) 0100 1xxx xxxx xxxx
1257 DECODE_SIMULATE (0xf800, 0x4800, t16_simulate_ldr_literal),
1260 * 16-bit Thumb Load/store instructions
1261 * 0101 xxxx xxxx xxxx
1262 * 011x xxxx xxxx xxxx
1263 * 100x xxxx xxxx xxxx
1266 /* STR (register) 0101 000x xxxx xxxx */
1267 /* STRH (register) 0101 001x xxxx xxxx */
1268 /* STRB (register) 0101 010x xxxx xxxx */
1269 /* LDRSB (register) 0101 011x xxxx xxxx */
1270 /* LDR (register) 0101 100x xxxx xxxx */
1271 /* LDRH (register) 0101 101x xxxx xxxx */
1272 /* LDRB (register) 0101 110x xxxx xxxx */
1273 /* LDRSH (register) 0101 111x xxxx xxxx */
1274 /* STR (immediate, Thumb) 0110 0xxx xxxx xxxx */
1275 /* LDR (immediate, Thumb) 0110 1xxx xxxx xxxx */
1276 /* STRB (immediate, Thumb) 0111 0xxx xxxx xxxx */
1277 /* LDRB (immediate, Thumb) 0111 1xxx xxxx xxxx */
1278 DECODE_EMULATE (0xc000, 0x4000, t16_emulate_loregs_rwflags),
1279 /* STRH (immediate, Thumb) 1000 0xxx xxxx xxxx */
1280 /* LDRH (immediate, Thumb) 1000 1xxx xxxx xxxx */
1281 DECODE_EMULATE (0xf000, 0x8000, t16_emulate_loregs_rwflags),
1282 /* STR (immediate, Thumb) 1001 0xxx xxxx xxxx */
1283 /* LDR (immediate, Thumb) 1001 1xxx xxxx xxxx */
1284 DECODE_SIMULATE (0xf000, 0x9000, t16_simulate_ldrstr_sp_relative),
1287 * Generate PC-/SP-relative address
1288 * ADR (literal) 1010 0xxx xxxx xxxx
1289 * ADD (SP plus immediate) 1010 1xxx xxxx xxxx
1291 DECODE_SIMULATE (0xf000, 0xa000, t16_simulate_reladr),
1294 * Miscellaneous 16-bit instructions
1295 * 1011 xxxx xxxx xxxx
1297 DECODE_TABLE (0xf000, 0xb000, t16_table_1011),
1299 /* STM 1100 0xxx xxxx xxxx */
1300 /* LDM 1100 1xxx xxxx xxxx */
1301 DECODE_EMULATE (0xf000, 0xc000, t16_emulate_loregs_rwflags),
1304 * Conditional branch, and Supervisor Call
1307 /* Permanently UNDEFINED 1101 1110 xxxx xxxx */
1308 /* SVC 1101 1111 xxxx xxxx */
1309 DECODE_REJECT (0xfe00, 0xde00),
1311 /* Conditional branch 1101 xxxx xxxx xxxx */
1312 DECODE_CUSTOM (0xf000, 0xd000, t16_decode_cond_branch),
1315 * Unconditional branch
1316 * B 1110 0xxx xxxx xxxx
1318 DECODE_SIMULATE (0xf800, 0xe000, t16_simulate_branch),
1323 static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
1325 if (unlikely(in_it_block(cpsr)))
1326 return kprobe_condition_checks[current_cond(cpsr)](cpsr);
1330 static void __kprobes thumb16_singlestep(struct kprobe *p, struct pt_regs *regs)
1333 p->ainsn.insn_handler(p, regs);
1334 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
1337 static void __kprobes thumb32_singlestep(struct kprobe *p, struct pt_regs *regs)
1340 p->ainsn.insn_handler(p, regs);
1341 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
1344 enum kprobe_insn __kprobes
1345 thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1347 asi->insn_singlestep = thumb16_singlestep;
1348 asi->insn_check_cc = thumb_check_cc;
1349 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true);
1352 enum kprobe_insn __kprobes
1353 thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1355 asi->insn_singlestep = thumb32_singlestep;
1356 asi->insn_check_cc = thumb_check_cc;
1357 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb32_table, true);