2 * arch/arm/kernel/kprobes-thumb.c
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/kprobes.h>
18 * True if current instruction is in an IT block.
20 #define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000)
23 * Return the condition code to check for the currently executing instruction.
24 * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
25 * in_it_block returns true.
27 #define current_cond(cpsr) ((cpsr >> 12) & 0xf)
30 * Return the PC value for a probe in thumb code.
31 * This is the address of the probed instruction plus 4.
32 * We subtract one because the address will have bit zero set to indicate
33 * a pointer to thumb code.
35 static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p)
37 return (unsigned long)p->addr - 1 + 4;
41 t32_simulate_table_branch(struct kprobe *p, struct pt_regs *regs)
43 kprobe_opcode_t insn = p->opcode;
44 unsigned long pc = thumb_probe_pc(p);
45 int rn = (insn >> 16) & 0xf;
48 unsigned long rnv = (rn == 15) ? pc : regs->uregs[rn];
49 unsigned long rmv = regs->uregs[rm];
50 unsigned int halfwords;
52 if (insn & 0x10) /* TBH */
53 halfwords = ((u16 *)rnv)[rmv];
55 halfwords = ((u8 *)rnv)[rmv];
57 regs->ARM_pc = pc + 2 * halfwords;
61 t32_simulate_mrs(struct kprobe *p, struct pt_regs *regs)
63 kprobe_opcode_t insn = p->opcode;
64 int rd = (insn >> 8) & 0xf;
65 unsigned long mask = 0xf8ff03df; /* Mask out execution state */
66 regs->uregs[rd] = regs->ARM_cpsr & mask;
70 t32_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
72 kprobe_opcode_t insn = p->opcode;
73 unsigned long pc = thumb_probe_pc(p);
75 long offset = insn & 0x7ff; /* imm11 */
76 offset += (insn & 0x003f0000) >> 5; /* imm6 */
77 offset += (insn & 0x00002000) << 4; /* J1 */
78 offset += (insn & 0x00000800) << 7; /* J2 */
79 offset -= (insn & 0x04000000) >> 7; /* Apply sign bit */
81 regs->ARM_pc = pc + (offset * 2);
84 static enum kprobe_insn __kprobes
85 t32_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
87 int cc = (insn >> 22) & 0xf;
88 asi->insn_check_cc = kprobe_condition_checks[cc];
89 asi->insn_handler = t32_simulate_cond_branch;
90 return INSN_GOOD_NO_SLOT;
94 t32_simulate_branch(struct kprobe *p, struct pt_regs *regs)
96 kprobe_opcode_t insn = p->opcode;
97 unsigned long pc = thumb_probe_pc(p);
99 long offset = insn & 0x7ff; /* imm11 */
100 offset += (insn & 0x03ff0000) >> 5; /* imm10 */
101 offset += (insn & 0x00002000) << 9; /* J1 */
102 offset += (insn & 0x00000800) << 10; /* J2 */
103 if (insn & 0x04000000)
104 offset -= 0x00800000; /* Apply sign bit */
106 offset ^= 0x00600000; /* Invert J1 and J2 */
108 if (insn & (1 << 14)) {
110 regs->ARM_lr = (unsigned long)p->addr + 4;
111 if (!(insn & (1 << 12))) {
112 /* BLX so switch to ARM mode */
113 regs->ARM_cpsr &= ~PSR_T_BIT;
118 regs->ARM_pc = pc + (offset * 2);
121 static void __kprobes
122 t32_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
124 kprobe_opcode_t insn = p->opcode;
125 unsigned long addr = thumb_probe_pc(p) & ~3;
126 int rt = (insn >> 12) & 0xf;
129 long offset = insn & 0xfff;
130 if (insn & 0x00800000)
135 if (insn & 0x00400000) {
137 rtv = *(unsigned long *)addr;
139 bx_write_pc(rtv, regs);
142 } else if (insn & 0x00200000) {
144 if (insn & 0x01000000)
150 if (insn & 0x01000000)
156 regs->uregs[rt] = rtv;
159 static enum kprobe_insn __kprobes
160 t32_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
162 enum kprobe_insn ret = kprobe_decode_ldmstm(insn, asi);
164 /* Fixup modified instruction to have halfwords in correct order...*/
166 ((u16 *)asi->insn)[0] = insn >> 16;
167 ((u16 *)asi->insn)[1] = insn & 0xffff;
172 static void __kprobes
173 t32_emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
175 kprobe_opcode_t insn = p->opcode;
176 unsigned long pc = thumb_probe_pc(p) & ~3;
177 int rt1 = (insn >> 12) & 0xf;
178 int rt2 = (insn >> 8) & 0xf;
179 int rn = (insn >> 16) & 0xf;
181 register unsigned long rt1v asm("r0") = regs->uregs[rt1];
182 register unsigned long rt2v asm("r1") = regs->uregs[rt2];
183 register unsigned long rnv asm("r2") = (rn == 15) ? pc
186 __asm__ __volatile__ (
188 : "=r" (rt1v), "=r" (rt2v), "=r" (rnv)
189 : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (p->ainsn.insn_fn)
190 : "lr", "memory", "cc"
194 regs->uregs[rn] = rnv; /* Writeback base register */
195 regs->uregs[rt1] = rt1v;
196 regs->uregs[rt2] = rt2v;
199 static void __kprobes
200 t32_emulate_ldrstr(struct kprobe *p, struct pt_regs *regs)
202 kprobe_opcode_t insn = p->opcode;
203 int rt = (insn >> 12) & 0xf;
204 int rn = (insn >> 16) & 0xf;
207 register unsigned long rtv asm("r0") = regs->uregs[rt];
208 register unsigned long rnv asm("r2") = regs->uregs[rn];
209 register unsigned long rmv asm("r3") = regs->uregs[rm];
211 __asm__ __volatile__ (
213 : "=r" (rtv), "=r" (rnv)
214 : "0" (rtv), "1" (rnv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn)
215 : "lr", "memory", "cc"
218 regs->uregs[rn] = rnv; /* Writeback base register */
219 if (rt == 15) /* Can't be true for a STR as they aren't allowed */
220 bx_write_pc(rtv, regs);
222 regs->uregs[rt] = rtv;
225 static void __kprobes
226 t32_emulate_rd8rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
228 kprobe_opcode_t insn = p->opcode;
229 int rd = (insn >> 8) & 0xf;
230 int rn = (insn >> 16) & 0xf;
233 register unsigned long rdv asm("r1") = regs->uregs[rd];
234 register unsigned long rnv asm("r2") = regs->uregs[rn];
235 register unsigned long rmv asm("r3") = regs->uregs[rm];
236 unsigned long cpsr = regs->ARM_cpsr;
238 __asm__ __volatile__ (
239 "msr cpsr_fs, %[cpsr] \n\t"
241 "mrs %[cpsr], cpsr \n\t"
242 : "=r" (rdv), [cpsr] "=r" (cpsr)
243 : "0" (rdv), "r" (rnv), "r" (rmv),
244 "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
245 : "lr", "memory", "cc"
248 regs->uregs[rd] = rdv;
249 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
252 static void __kprobes
253 t32_emulate_rd8pc16_noflags(struct kprobe *p, struct pt_regs *regs)
255 kprobe_opcode_t insn = p->opcode;
256 unsigned long pc = thumb_probe_pc(p);
257 int rd = (insn >> 8) & 0xf;
259 register unsigned long rdv asm("r1") = regs->uregs[rd];
260 register unsigned long rnv asm("r2") = pc & ~3;
262 __asm__ __volatile__ (
265 : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
266 : "lr", "memory", "cc"
269 regs->uregs[rd] = rdv;
272 static void __kprobes
273 t32_emulate_rd8rn16_noflags(struct kprobe *p, struct pt_regs *regs)
275 kprobe_opcode_t insn = p->opcode;
276 int rd = (insn >> 8) & 0xf;
277 int rn = (insn >> 16) & 0xf;
279 register unsigned long rdv asm("r1") = regs->uregs[rd];
280 register unsigned long rnv asm("r2") = regs->uregs[rn];
282 __asm__ __volatile__ (
285 : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
286 : "lr", "memory", "cc"
289 regs->uregs[rd] = rdv;
292 static void __kprobes
293 t32_emulate_rdlo12rdhi8rn16rm0_noflags(struct kprobe *p, struct pt_regs *regs)
295 kprobe_opcode_t insn = p->opcode;
296 int rdlo = (insn >> 12) & 0xf;
297 int rdhi = (insn >> 8) & 0xf;
298 int rn = (insn >> 16) & 0xf;
301 register unsigned long rdlov asm("r0") = regs->uregs[rdlo];
302 register unsigned long rdhiv asm("r1") = regs->uregs[rdhi];
303 register unsigned long rnv asm("r2") = regs->uregs[rn];
304 register unsigned long rmv asm("r3") = regs->uregs[rm];
306 __asm__ __volatile__ (
308 : "=r" (rdlov), "=r" (rdhiv)
309 : "0" (rdlov), "1" (rdhiv), "r" (rnv), "r" (rmv),
310 [fn] "r" (p->ainsn.insn_fn)
311 : "lr", "memory", "cc"
314 regs->uregs[rdlo] = rdlov;
315 regs->uregs[rdhi] = rdhiv;
318 static const union decode_item t32_table_1110_100x_x0xx[] = {
319 /* Load/store multiple instructions */
321 /* Rn is PC 1110 100x x0xx 1111 xxxx xxxx xxxx xxxx */
322 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
324 /* SRS 1110 1000 00x0 xxxx xxxx xxxx xxxx xxxx */
325 /* RFE 1110 1000 00x1 xxxx xxxx xxxx xxxx xxxx */
326 DECODE_REJECT (0xffc00000, 0xe8000000),
327 /* SRS 1110 1001 10x0 xxxx xxxx xxxx xxxx xxxx */
328 /* RFE 1110 1001 10x1 xxxx xxxx xxxx xxxx xxxx */
329 DECODE_REJECT (0xffc00000, 0xe9800000),
331 /* STM Rn, {...pc} 1110 100x x0x0 xxxx 1xxx xxxx xxxx xxxx */
332 DECODE_REJECT (0xfe508000, 0xe8008000),
333 /* LDM Rn, {...lr,pc} 1110 100x x0x1 xxxx 11xx xxxx xxxx xxxx */
334 DECODE_REJECT (0xfe50c000, 0xe810c000),
335 /* LDM/STM Rn, {...sp} 1110 100x x0xx xxxx xx1x xxxx xxxx xxxx */
336 DECODE_REJECT (0xfe402000, 0xe8002000),
338 /* STMIA 1110 1000 10x0 xxxx xxxx xxxx xxxx xxxx */
339 /* LDMIA 1110 1000 10x1 xxxx xxxx xxxx xxxx xxxx */
340 /* STMDB 1110 1001 00x0 xxxx xxxx xxxx xxxx xxxx */
341 /* LDMDB 1110 1001 00x1 xxxx xxxx xxxx xxxx xxxx */
342 DECODE_CUSTOM (0xfe400000, 0xe8000000, t32_decode_ldmstm),
347 static const union decode_item t32_table_1110_100x_x1xx[] = {
348 /* Load/store dual, load/store exclusive, table branch */
350 /* STRD (immediate) 1110 1000 x110 xxxx xxxx xxxx xxxx xxxx */
351 /* LDRD (immediate) 1110 1000 x111 xxxx xxxx xxxx xxxx xxxx */
352 DECODE_OR (0xff600000, 0xe8600000),
353 /* STRD (immediate) 1110 1001 x1x0 xxxx xxxx xxxx xxxx xxxx */
354 /* LDRD (immediate) 1110 1001 x1x1 xxxx xxxx xxxx xxxx xxxx */
355 DECODE_EMULATEX (0xff400000, 0xe9400000, t32_emulate_ldrdstrd,
356 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
358 /* TBB 1110 1000 1101 xxxx xxxx xxxx 0000 xxxx */
359 /* TBH 1110 1000 1101 xxxx xxxx xxxx 0001 xxxx */
360 DECODE_SIMULATEX(0xfff000e0, 0xe8d00000, t32_simulate_table_branch,
361 REGS(NOSP, 0, 0, 0, NOSPPC)),
363 /* STREX 1110 1000 0100 xxxx xxxx xxxx xxxx xxxx */
364 /* LDREX 1110 1000 0101 xxxx xxxx xxxx xxxx xxxx */
365 /* STREXB 1110 1000 1100 xxxx xxxx xxxx 0100 xxxx */
366 /* STREXH 1110 1000 1100 xxxx xxxx xxxx 0101 xxxx */
367 /* STREXD 1110 1000 1100 xxxx xxxx xxxx 0111 xxxx */
368 /* LDREXB 1110 1000 1101 xxxx xxxx xxxx 0100 xxxx */
369 /* LDREXH 1110 1000 1101 xxxx xxxx xxxx 0101 xxxx */
370 /* LDREXD 1110 1000 1101 xxxx xxxx xxxx 0111 xxxx */
371 /* And unallocated instructions... */
375 static const union decode_item t32_table_1110_101x[] = {
376 /* Data-processing (shifted register) */
378 /* TST 1110 1010 0001 xxxx xxxx 1111 xxxx xxxx */
379 /* TEQ 1110 1010 1001 xxxx xxxx 1111 xxxx xxxx */
380 DECODE_EMULATEX (0xff700f00, 0xea100f00, t32_emulate_rd8rn16rm0_rwflags,
381 REGS(NOSPPC, 0, 0, 0, NOSPPC)),
383 /* CMN 1110 1011 0001 xxxx xxxx 1111 xxxx xxxx */
384 DECODE_OR (0xfff00f00, 0xeb100f00),
385 /* CMP 1110 1011 1011 xxxx xxxx 1111 xxxx xxxx */
386 DECODE_EMULATEX (0xfff00f00, 0xebb00f00, t32_emulate_rd8rn16rm0_rwflags,
387 REGS(NOPC, 0, 0, 0, NOSPPC)),
389 /* MOV 1110 1010 010x 1111 xxxx xxxx xxxx xxxx */
390 /* MVN 1110 1010 011x 1111 xxxx xxxx xxxx xxxx */
391 DECODE_EMULATEX (0xffcf0000, 0xea4f0000, t32_emulate_rd8rn16rm0_rwflags,
392 REGS(0, 0, NOSPPC, 0, NOSPPC)),
394 /* ??? 1110 1010 101x xxxx xxxx xxxx xxxx xxxx */
395 /* ??? 1110 1010 111x xxxx xxxx xxxx xxxx xxxx */
396 DECODE_REJECT (0xffa00000, 0xeaa00000),
397 /* ??? 1110 1011 001x xxxx xxxx xxxx xxxx xxxx */
398 DECODE_REJECT (0xffe00000, 0xeb200000),
399 /* ??? 1110 1011 100x xxxx xxxx xxxx xxxx xxxx */
400 DECODE_REJECT (0xffe00000, 0xeb800000),
401 /* ??? 1110 1011 111x xxxx xxxx xxxx xxxx xxxx */
402 DECODE_REJECT (0xffe00000, 0xebe00000),
404 /* ADD/SUB SP, SP, Rm, LSL #0..3 */
405 /* 1110 1011 x0xx 1101 x000 1101 xx00 xxxx */
406 DECODE_EMULATEX (0xff4f7f30, 0xeb0d0d00, t32_emulate_rd8rn16rm0_rwflags,
407 REGS(SP, 0, SP, 0, NOSPPC)),
409 /* ADD/SUB SP, SP, Rm, shift */
410 /* 1110 1011 x0xx 1101 xxxx 1101 xxxx xxxx */
411 DECODE_REJECT (0xff4f0f00, 0xeb0d0d00),
413 /* ADD/SUB Rd, SP, Rm, shift */
414 /* 1110 1011 x0xx 1101 xxxx xxxx xxxx xxxx */
415 DECODE_EMULATEX (0xff4f0000, 0xeb0d0000, t32_emulate_rd8rn16rm0_rwflags,
416 REGS(SP, 0, NOPC, 0, NOSPPC)),
418 /* AND 1110 1010 000x xxxx xxxx xxxx xxxx xxxx */
419 /* BIC 1110 1010 001x xxxx xxxx xxxx xxxx xxxx */
420 /* ORR 1110 1010 010x xxxx xxxx xxxx xxxx xxxx */
421 /* ORN 1110 1010 011x xxxx xxxx xxxx xxxx xxxx */
422 /* EOR 1110 1010 100x xxxx xxxx xxxx xxxx xxxx */
423 /* PKH 1110 1010 110x xxxx xxxx xxxx xxxx xxxx */
424 /* ADD 1110 1011 000x xxxx xxxx xxxx xxxx xxxx */
425 /* ADC 1110 1011 010x xxxx xxxx xxxx xxxx xxxx */
426 /* SBC 1110 1011 011x xxxx xxxx xxxx xxxx xxxx */
427 /* SUB 1110 1011 101x xxxx xxxx xxxx xxxx xxxx */
428 /* RSB 1110 1011 110x xxxx xxxx xxxx xxxx xxxx */
429 DECODE_EMULATEX (0xfe000000, 0xea000000, t32_emulate_rd8rn16rm0_rwflags,
430 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
435 static const union decode_item t32_table_1111_0x0x___0[] = {
436 /* Data-processing (modified immediate) */
438 /* TST 1111 0x00 0001 xxxx 0xxx 1111 xxxx xxxx */
439 /* TEQ 1111 0x00 1001 xxxx 0xxx 1111 xxxx xxxx */
440 DECODE_EMULATEX (0xfb708f00, 0xf0100f00, t32_emulate_rd8rn16rm0_rwflags,
441 REGS(NOSPPC, 0, 0, 0, 0)),
443 /* CMN 1111 0x01 0001 xxxx 0xxx 1111 xxxx xxxx */
444 DECODE_OR (0xfbf08f00, 0xf1100f00),
445 /* CMP 1111 0x01 1011 xxxx 0xxx 1111 xxxx xxxx */
446 DECODE_EMULATEX (0xfbf08f00, 0xf1b00f00, t32_emulate_rd8rn16rm0_rwflags,
447 REGS(NOPC, 0, 0, 0, 0)),
449 /* MOV 1111 0x00 010x 1111 0xxx xxxx xxxx xxxx */
450 /* MVN 1111 0x00 011x 1111 0xxx xxxx xxxx xxxx */
451 DECODE_EMULATEX (0xfbcf8000, 0xf04f0000, t32_emulate_rd8rn16rm0_rwflags,
452 REGS(0, 0, NOSPPC, 0, 0)),
454 /* ??? 1111 0x00 101x xxxx 0xxx xxxx xxxx xxxx */
455 DECODE_REJECT (0xfbe08000, 0xf0a00000),
456 /* ??? 1111 0x00 110x xxxx 0xxx xxxx xxxx xxxx */
457 /* ??? 1111 0x00 111x xxxx 0xxx xxxx xxxx xxxx */
458 DECODE_REJECT (0xfbc08000, 0xf0c00000),
459 /* ??? 1111 0x01 001x xxxx 0xxx xxxx xxxx xxxx */
460 DECODE_REJECT (0xfbe08000, 0xf1200000),
461 /* ??? 1111 0x01 100x xxxx 0xxx xxxx xxxx xxxx */
462 DECODE_REJECT (0xfbe08000, 0xf1800000),
463 /* ??? 1111 0x01 111x xxxx 0xxx xxxx xxxx xxxx */
464 DECODE_REJECT (0xfbe08000, 0xf1e00000),
466 /* ADD Rd, SP, #imm 1111 0x01 000x 1101 0xxx xxxx xxxx xxxx */
467 /* SUB Rd, SP, #imm 1111 0x01 101x 1101 0xxx xxxx xxxx xxxx */
468 DECODE_EMULATEX (0xfb4f8000, 0xf10d0000, t32_emulate_rd8rn16rm0_rwflags,
469 REGS(SP, 0, NOPC, 0, 0)),
471 /* AND 1111 0x00 000x xxxx 0xxx xxxx xxxx xxxx */
472 /* BIC 1111 0x00 001x xxxx 0xxx xxxx xxxx xxxx */
473 /* ORR 1111 0x00 010x xxxx 0xxx xxxx xxxx xxxx */
474 /* ORN 1111 0x00 011x xxxx 0xxx xxxx xxxx xxxx */
475 /* EOR 1111 0x00 100x xxxx 0xxx xxxx xxxx xxxx */
476 /* ADD 1111 0x01 000x xxxx 0xxx xxxx xxxx xxxx */
477 /* ADC 1111 0x01 010x xxxx 0xxx xxxx xxxx xxxx */
478 /* SBC 1111 0x01 011x xxxx 0xxx xxxx xxxx xxxx */
479 /* SUB 1111 0x01 101x xxxx 0xxx xxxx xxxx xxxx */
480 /* RSB 1111 0x01 110x xxxx 0xxx xxxx xxxx xxxx */
481 DECODE_EMULATEX (0xfa008000, 0xf0000000, t32_emulate_rd8rn16rm0_rwflags,
482 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
487 static const union decode_item t32_table_1111_0x1x___0[] = {
488 /* Data-processing (plain binary immediate) */
490 /* ADDW Rd, PC, #imm 1111 0x10 0000 1111 0xxx xxxx xxxx xxxx */
491 DECODE_OR (0xfbff8000, 0xf20f0000),
492 /* SUBW Rd, PC, #imm 1111 0x10 1010 1111 0xxx xxxx xxxx xxxx */
493 DECODE_EMULATEX (0xfbff8000, 0xf2af0000, t32_emulate_rd8pc16_noflags,
494 REGS(PC, 0, NOSPPC, 0, 0)),
496 /* ADDW SP, SP, #imm 1111 0x10 0000 1101 0xxx 1101 xxxx xxxx */
497 DECODE_OR (0xfbff8f00, 0xf20d0d00),
498 /* SUBW SP, SP, #imm 1111 0x10 1010 1101 0xxx 1101 xxxx xxxx */
499 DECODE_EMULATEX (0xfbff8f00, 0xf2ad0d00, t32_emulate_rd8rn16_noflags,
500 REGS(SP, 0, SP, 0, 0)),
502 /* ADDW 1111 0x10 0000 xxxx 0xxx xxxx xxxx xxxx */
503 DECODE_OR (0xfbf08000, 0xf2000000),
504 /* SUBW 1111 0x10 1010 xxxx 0xxx xxxx xxxx xxxx */
505 DECODE_EMULATEX (0xfbf08000, 0xf2a00000, t32_emulate_rd8rn16_noflags,
506 REGS(NOPCX, 0, NOSPPC, 0, 0)),
508 /* MOVW 1111 0x10 0100 xxxx 0xxx xxxx xxxx xxxx */
509 /* MOVT 1111 0x10 1100 xxxx 0xxx xxxx xxxx xxxx */
510 DECODE_EMULATEX (0xfb708000, 0xf2400000, t32_emulate_rd8rn16_noflags,
511 REGS(0, 0, NOSPPC, 0, 0)),
513 /* SSAT16 1111 0x11 0010 xxxx 0000 xxxx 00xx xxxx */
514 /* SSAT 1111 0x11 00x0 xxxx 0xxx xxxx xxxx xxxx */
515 /* USAT16 1111 0x11 1010 xxxx 0000 xxxx 00xx xxxx */
516 /* USAT 1111 0x11 10x0 xxxx 0xxx xxxx xxxx xxxx */
517 DECODE_EMULATEX (0xfb508000, 0xf3000000, t32_emulate_rd8rn16rm0_rwflags,
518 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
520 /* SFBX 1111 0x11 0100 xxxx 0xxx xxxx xxxx xxxx */
521 /* UFBX 1111 0x11 1100 xxxx 0xxx xxxx xxxx xxxx */
522 DECODE_EMULATEX (0xfb708000, 0xf3400000, t32_emulate_rd8rn16_noflags,
523 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
525 /* BFC 1111 0x11 0110 1111 0xxx xxxx xxxx xxxx */
526 DECODE_EMULATEX (0xfbff8000, 0xf36f0000, t32_emulate_rd8rn16_noflags,
527 REGS(0, 0, NOSPPC, 0, 0)),
529 /* BFI 1111 0x11 0110 xxxx 0xxx xxxx xxxx xxxx */
530 DECODE_EMULATEX (0xfbf08000, 0xf3600000, t32_emulate_rd8rn16_noflags,
531 REGS(NOSPPCX, 0, NOSPPC, 0, 0)),
536 static const union decode_item t32_table_1111_0xxx___1[] = {
537 /* Branches and miscellaneous control */
539 /* YIELD 1111 0011 1010 xxxx 10x0 x000 0000 0001 */
540 DECODE_OR (0xfff0d7ff, 0xf3a08001),
541 /* SEV 1111 0011 1010 xxxx 10x0 x000 0000 0100 */
542 DECODE_EMULATE (0xfff0d7ff, 0xf3a08004, kprobe_emulate_none),
543 /* NOP 1111 0011 1010 xxxx 10x0 x000 0000 0000 */
544 /* WFE 1111 0011 1010 xxxx 10x0 x000 0000 0010 */
545 /* WFI 1111 0011 1010 xxxx 10x0 x000 0000 0011 */
546 DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, kprobe_simulate_nop),
548 /* MRS Rd, CPSR 1111 0011 1110 xxxx 10x0 xxxx xxxx xxxx */
549 DECODE_SIMULATEX(0xfff0d000, 0xf3e08000, t32_simulate_mrs,
550 REGS(0, 0, NOSPPC, 0, 0)),
553 * Unsupported instructions
554 * 1111 0x11 1xxx xxxx 10x0 xxxx xxxx xxxx
556 * MSR 1111 0011 100x xxxx 10x0 xxxx xxxx xxxx
557 * DBG hint 1111 0011 1010 xxxx 10x0 x000 1111 xxxx
558 * Unallocated hints 1111 0011 1010 xxxx 10x0 x000 xxxx xxxx
559 * CPS 1111 0011 1010 xxxx 10x0 xxxx xxxx xxxx
560 * CLREX/DSB/DMB/ISB 1111 0011 1011 xxxx 10x0 xxxx xxxx xxxx
561 * BXJ 1111 0011 1100 xxxx 10x0 xxxx xxxx xxxx
562 * SUBS PC,LR,#<imm8> 1111 0011 1101 xxxx 10x0 xxxx xxxx xxxx
563 * MRS Rd, SPSR 1111 0011 1111 xxxx 10x0 xxxx xxxx xxxx
564 * SMC 1111 0111 1111 xxxx 1000 xxxx xxxx xxxx
565 * UNDEFINED 1111 0111 1111 xxxx 1010 xxxx xxxx xxxx
566 * ??? 1111 0111 1xxx xxxx 1010 xxxx xxxx xxxx
568 DECODE_REJECT (0xfb80d000, 0xf3808000),
570 /* Bcc 1111 0xxx xxxx xxxx 10x0 xxxx xxxx xxxx */
571 DECODE_CUSTOM (0xf800d000, 0xf0008000, t32_decode_cond_branch),
573 /* BLX 1111 0xxx xxxx xxxx 11x0 xxxx xxxx xxx0 */
574 DECODE_OR (0xf800d001, 0xf000c000),
575 /* B 1111 0xxx xxxx xxxx 10x1 xxxx xxxx xxxx */
576 /* BL 1111 0xxx xxxx xxxx 11x1 xxxx xxxx xxxx */
577 DECODE_SIMULATE (0xf8009000, 0xf0009000, t32_simulate_branch),
582 static const union decode_item t32_table_1111_100x_x0x1__1111[] = {
585 /* PLD (literal) 1111 1000 x001 1111 1111 xxxx xxxx xxxx */
586 /* PLI (literal) 1111 1001 x001 1111 1111 xxxx xxxx xxxx */
587 DECODE_SIMULATE (0xfe7ff000, 0xf81ff000, kprobe_simulate_nop),
589 /* PLD{W} (immediate) 1111 1000 10x1 xxxx 1111 xxxx xxxx xxxx */
590 DECODE_OR (0xffd0f000, 0xf890f000),
591 /* PLD{W} (immediate) 1111 1000 00x1 xxxx 1111 1100 xxxx xxxx */
592 DECODE_OR (0xffd0ff00, 0xf810fc00),
593 /* PLI (immediate) 1111 1001 1001 xxxx 1111 xxxx xxxx xxxx */
594 DECODE_OR (0xfff0f000, 0xf990f000),
595 /* PLI (immediate) 1111 1001 0001 xxxx 1111 1100 xxxx xxxx */
596 DECODE_SIMULATEX(0xfff0ff00, 0xf910fc00, kprobe_simulate_nop,
597 REGS(NOPCX, 0, 0, 0, 0)),
599 /* PLD{W} (register) 1111 1000 00x1 xxxx 1111 0000 00xx xxxx */
600 DECODE_OR (0xffd0ffc0, 0xf810f000),
601 /* PLI (register) 1111 1001 0001 xxxx 1111 0000 00xx xxxx */
602 DECODE_SIMULATEX(0xfff0ffc0, 0xf910f000, kprobe_simulate_nop,
603 REGS(NOPCX, 0, 0, 0, NOSPPC)),
605 /* Other unallocated instructions... */
609 static const union decode_item t32_table_1111_100x[] = {
610 /* Store/Load single data item */
612 /* ??? 1111 100x x11x xxxx xxxx xxxx xxxx xxxx */
613 DECODE_REJECT (0xfe600000, 0xf8600000),
615 /* ??? 1111 1001 0101 xxxx xxxx xxxx xxxx xxxx */
616 DECODE_REJECT (0xfff00000, 0xf9500000),
618 /* ??? 1111 100x 0xxx xxxx xxxx 10x0 xxxx xxxx */
619 DECODE_REJECT (0xfe800d00, 0xf8000800),
621 /* STRBT 1111 1000 0000 xxxx xxxx 1110 xxxx xxxx */
622 /* STRHT 1111 1000 0010 xxxx xxxx 1110 xxxx xxxx */
623 /* STRT 1111 1000 0100 xxxx xxxx 1110 xxxx xxxx */
624 /* LDRBT 1111 1000 0001 xxxx xxxx 1110 xxxx xxxx */
625 /* LDRSBT 1111 1001 0001 xxxx xxxx 1110 xxxx xxxx */
626 /* LDRHT 1111 1000 0011 xxxx xxxx 1110 xxxx xxxx */
627 /* LDRSHT 1111 1001 0011 xxxx xxxx 1110 xxxx xxxx */
628 /* LDRT 1111 1000 0101 xxxx xxxx 1110 xxxx xxxx */
629 DECODE_REJECT (0xfe800f00, 0xf8000e00),
631 /* STR{,B,H} Rn,[PC...] 1111 1000 xxx0 1111 xxxx xxxx xxxx xxxx */
632 DECODE_REJECT (0xff1f0000, 0xf80f0000),
634 /* STR{,B,H} PC,[Rn...] 1111 1000 xxx0 xxxx 1111 xxxx xxxx xxxx */
635 DECODE_REJECT (0xff10f000, 0xf800f000),
637 /* LDR (literal) 1111 1000 x101 1111 xxxx xxxx xxxx xxxx */
638 DECODE_SIMULATEX(0xff7f0000, 0xf85f0000, t32_simulate_ldr_literal,
639 REGS(PC, ANY, 0, 0, 0)),
641 /* STR (immediate) 1111 1000 0100 xxxx xxxx 1xxx xxxx xxxx */
642 /* LDR (immediate) 1111 1000 0101 xxxx xxxx 1xxx xxxx xxxx */
643 DECODE_OR (0xffe00800, 0xf8400800),
644 /* STR (immediate) 1111 1000 1100 xxxx xxxx xxxx xxxx xxxx */
645 /* LDR (immediate) 1111 1000 1101 xxxx xxxx xxxx xxxx xxxx */
646 DECODE_EMULATEX (0xffe00000, 0xf8c00000, t32_emulate_ldrstr,
647 REGS(NOPCX, ANY, 0, 0, 0)),
649 /* STR (register) 1111 1000 0100 xxxx xxxx 0000 00xx xxxx */
650 /* LDR (register) 1111 1000 0101 xxxx xxxx 0000 00xx xxxx */
651 DECODE_EMULATEX (0xffe00fc0, 0xf8400000, t32_emulate_ldrstr,
652 REGS(NOPCX, ANY, 0, 0, NOSPPC)),
654 /* LDRB (literal) 1111 1000 x001 1111 xxxx xxxx xxxx xxxx */
655 /* LDRSB (literal) 1111 1001 x001 1111 xxxx xxxx xxxx xxxx */
656 /* LDRH (literal) 1111 1000 x011 1111 xxxx xxxx xxxx xxxx */
657 /* LDRSH (literal) 1111 1001 x011 1111 xxxx xxxx xxxx xxxx */
658 DECODE_EMULATEX (0xfe5f0000, 0xf81f0000, t32_simulate_ldr_literal,
659 REGS(PC, NOSPPCX, 0, 0, 0)),
661 /* STRB (immediate) 1111 1000 0000 xxxx xxxx 1xxx xxxx xxxx */
662 /* STRH (immediate) 1111 1000 0010 xxxx xxxx 1xxx xxxx xxxx */
663 /* LDRB (immediate) 1111 1000 0001 xxxx xxxx 1xxx xxxx xxxx */
664 /* LDRSB (immediate) 1111 1001 0001 xxxx xxxx 1xxx xxxx xxxx */
665 /* LDRH (immediate) 1111 1000 0011 xxxx xxxx 1xxx xxxx xxxx */
666 /* LDRSH (immediate) 1111 1001 0011 xxxx xxxx 1xxx xxxx xxxx */
667 DECODE_OR (0xfec00800, 0xf8000800),
668 /* STRB (immediate) 1111 1000 1000 xxxx xxxx xxxx xxxx xxxx */
669 /* STRH (immediate) 1111 1000 1010 xxxx xxxx xxxx xxxx xxxx */
670 /* LDRB (immediate) 1111 1000 1001 xxxx xxxx xxxx xxxx xxxx */
671 /* LDRSB (immediate) 1111 1001 1001 xxxx xxxx xxxx xxxx xxxx */
672 /* LDRH (immediate) 1111 1000 1011 xxxx xxxx xxxx xxxx xxxx */
673 /* LDRSH (immediate) 1111 1001 1011 xxxx xxxx xxxx xxxx xxxx */
674 DECODE_EMULATEX (0xfec00000, 0xf8800000, t32_emulate_ldrstr,
675 REGS(NOPCX, NOSPPCX, 0, 0, 0)),
677 /* STRB (register) 1111 1000 0000 xxxx xxxx 0000 00xx xxxx */
678 /* STRH (register) 1111 1000 0010 xxxx xxxx 0000 00xx xxxx */
679 /* LDRB (register) 1111 1000 0001 xxxx xxxx 0000 00xx xxxx */
680 /* LDRSB (register) 1111 1001 0001 xxxx xxxx 0000 00xx xxxx */
681 /* LDRH (register) 1111 1000 0011 xxxx xxxx 0000 00xx xxxx */
682 /* LDRSH (register) 1111 1001 0011 xxxx xxxx 0000 00xx xxxx */
683 DECODE_EMULATEX (0xfe800fc0, 0xf8000000, t32_emulate_ldrstr,
684 REGS(NOPCX, NOSPPCX, 0, 0, NOSPPC)),
686 /* Other unallocated instructions... */
690 static const union decode_item t32_table_1111_1010___1111[] = {
691 /* Data-processing (register) */
693 /* ??? 1111 1010 011x xxxx 1111 xxxx 1xxx xxxx */
694 DECODE_REJECT (0xffe0f080, 0xfa60f080),
696 /* SXTH 1111 1010 0000 1111 1111 xxxx 1xxx xxxx */
697 /* UXTH 1111 1010 0001 1111 1111 xxxx 1xxx xxxx */
698 /* SXTB16 1111 1010 0010 1111 1111 xxxx 1xxx xxxx */
699 /* UXTB16 1111 1010 0011 1111 1111 xxxx 1xxx xxxx */
700 /* SXTB 1111 1010 0100 1111 1111 xxxx 1xxx xxxx */
701 /* UXTB 1111 1010 0101 1111 1111 xxxx 1xxx xxxx */
702 DECODE_EMULATEX (0xff8ff080, 0xfa0ff080, t32_emulate_rd8rn16rm0_rwflags,
703 REGS(0, 0, NOSPPC, 0, NOSPPC)),
706 /* ??? 1111 1010 1xxx xxxx 1111 xxxx 0x11 xxxx */
707 DECODE_REJECT (0xff80f0b0, 0xfa80f030),
708 /* ??? 1111 1010 1x11 xxxx 1111 xxxx 0xxx xxxx */
709 DECODE_REJECT (0xffb0f080, 0xfab0f000),
711 /* SADD16 1111 1010 1001 xxxx 1111 xxxx 0000 xxxx */
712 /* SASX 1111 1010 1010 xxxx 1111 xxxx 0000 xxxx */
713 /* SSAX 1111 1010 1110 xxxx 1111 xxxx 0000 xxxx */
714 /* SSUB16 1111 1010 1101 xxxx 1111 xxxx 0000 xxxx */
715 /* SADD8 1111 1010 1000 xxxx 1111 xxxx 0000 xxxx */
716 /* SSUB8 1111 1010 1100 xxxx 1111 xxxx 0000 xxxx */
718 /* QADD16 1111 1010 1001 xxxx 1111 xxxx 0001 xxxx */
719 /* QASX 1111 1010 1010 xxxx 1111 xxxx 0001 xxxx */
720 /* QSAX 1111 1010 1110 xxxx 1111 xxxx 0001 xxxx */
721 /* QSUB16 1111 1010 1101 xxxx 1111 xxxx 0001 xxxx */
722 /* QADD8 1111 1010 1000 xxxx 1111 xxxx 0001 xxxx */
723 /* QSUB8 1111 1010 1100 xxxx 1111 xxxx 0001 xxxx */
725 /* SHADD16 1111 1010 1001 xxxx 1111 xxxx 0010 xxxx */
726 /* SHASX 1111 1010 1010 xxxx 1111 xxxx 0010 xxxx */
727 /* SHSAX 1111 1010 1110 xxxx 1111 xxxx 0010 xxxx */
728 /* SHSUB16 1111 1010 1101 xxxx 1111 xxxx 0010 xxxx */
729 /* SHADD8 1111 1010 1000 xxxx 1111 xxxx 0010 xxxx */
730 /* SHSUB8 1111 1010 1100 xxxx 1111 xxxx 0010 xxxx */
732 /* UADD16 1111 1010 1001 xxxx 1111 xxxx 0100 xxxx */
733 /* UASX 1111 1010 1010 xxxx 1111 xxxx 0100 xxxx */
734 /* USAX 1111 1010 1110 xxxx 1111 xxxx 0100 xxxx */
735 /* USUB16 1111 1010 1101 xxxx 1111 xxxx 0100 xxxx */
736 /* UADD8 1111 1010 1000 xxxx 1111 xxxx 0100 xxxx */
737 /* USUB8 1111 1010 1100 xxxx 1111 xxxx 0100 xxxx */
739 /* UQADD16 1111 1010 1001 xxxx 1111 xxxx 0101 xxxx */
740 /* UQASX 1111 1010 1010 xxxx 1111 xxxx 0101 xxxx */
741 /* UQSAX 1111 1010 1110 xxxx 1111 xxxx 0101 xxxx */
742 /* UQSUB16 1111 1010 1101 xxxx 1111 xxxx 0101 xxxx */
743 /* UQADD8 1111 1010 1000 xxxx 1111 xxxx 0101 xxxx */
744 /* UQSUB8 1111 1010 1100 xxxx 1111 xxxx 0101 xxxx */
746 /* UHADD16 1111 1010 1001 xxxx 1111 xxxx 0110 xxxx */
747 /* UHASX 1111 1010 1010 xxxx 1111 xxxx 0110 xxxx */
748 /* UHSAX 1111 1010 1110 xxxx 1111 xxxx 0110 xxxx */
749 /* UHSUB16 1111 1010 1101 xxxx 1111 xxxx 0110 xxxx */
750 /* UHADD8 1111 1010 1000 xxxx 1111 xxxx 0110 xxxx */
751 /* UHSUB8 1111 1010 1100 xxxx 1111 xxxx 0110 xxxx */
752 DECODE_OR (0xff80f080, 0xfa80f000),
754 /* SXTAH 1111 1010 0000 xxxx 1111 xxxx 1xxx xxxx */
755 /* UXTAH 1111 1010 0001 xxxx 1111 xxxx 1xxx xxxx */
756 /* SXTAB16 1111 1010 0010 xxxx 1111 xxxx 1xxx xxxx */
757 /* UXTAB16 1111 1010 0011 xxxx 1111 xxxx 1xxx xxxx */
758 /* SXTAB 1111 1010 0100 xxxx 1111 xxxx 1xxx xxxx */
759 /* UXTAB 1111 1010 0101 xxxx 1111 xxxx 1xxx xxxx */
760 DECODE_OR (0xff80f080, 0xfa00f080),
762 /* QADD 1111 1010 1000 xxxx 1111 xxxx 1000 xxxx */
763 /* QDADD 1111 1010 1000 xxxx 1111 xxxx 1001 xxxx */
764 /* QSUB 1111 1010 1000 xxxx 1111 xxxx 1010 xxxx */
765 /* QDSUB 1111 1010 1000 xxxx 1111 xxxx 1011 xxxx */
766 DECODE_OR (0xfff0f0c0, 0xfa80f080),
768 /* SEL 1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */
769 DECODE_OR (0xfff0f0f0, 0xfaa0f080),
771 /* LSL 1111 1010 000x xxxx 1111 xxxx 0000 xxxx */
772 /* LSR 1111 1010 001x xxxx 1111 xxxx 0000 xxxx */
773 /* ASR 1111 1010 010x xxxx 1111 xxxx 0000 xxxx */
774 /* ROR 1111 1010 011x xxxx 1111 xxxx 0000 xxxx */
775 DECODE_EMULATEX (0xff80f0f0, 0xfa00f000, t32_emulate_rd8rn16rm0_rwflags,
776 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
778 /* CLZ 1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */
779 DECODE_OR (0xfff0f0f0, 0xfab0f080),
781 /* REV 1111 1010 1001 xxxx 1111 xxxx 1000 xxxx */
782 /* REV16 1111 1010 1001 xxxx 1111 xxxx 1001 xxxx */
783 /* RBIT 1111 1010 1001 xxxx 1111 xxxx 1010 xxxx */
784 /* REVSH 1111 1010 1001 xxxx 1111 xxxx 1011 xxxx */
785 DECODE_EMULATEX (0xfff0f0c0, 0xfa90f080, t32_emulate_rd8rn16_noflags,
786 REGS(NOSPPC, 0, NOSPPC, 0, SAMEAS16)),
788 /* Other unallocated instructions... */
792 static const union decode_item t32_table_1111_1011_1[] = {
793 /* Long multiply, long multiply accumulate, and divide */
795 /* UMAAL 1111 1011 1110 xxxx xxxx xxxx 0110 xxxx */
796 DECODE_OR (0xfff000f0, 0xfbe00060),
797 /* SMLALxy 1111 1011 1100 xxxx xxxx xxxx 10xx xxxx */
798 DECODE_OR (0xfff000c0, 0xfbc00080),
799 /* SMLALD{X} 1111 1011 1100 xxxx xxxx xxxx 110x xxxx */
800 /* SMLSLD{X} 1111 1011 1101 xxxx xxxx xxxx 110x xxxx */
801 DECODE_OR (0xffe000e0, 0xfbc000c0),
802 /* SMULL 1111 1011 1000 xxxx xxxx xxxx 0000 xxxx */
803 /* UMULL 1111 1011 1010 xxxx xxxx xxxx 0000 xxxx */
804 /* SMLAL 1111 1011 1100 xxxx xxxx xxxx 0000 xxxx */
805 /* UMLAL 1111 1011 1110 xxxx xxxx xxxx 0000 xxxx */
806 DECODE_EMULATEX (0xff9000f0, 0xfb800000, t32_emulate_rdlo12rdhi8rn16rm0_noflags,
807 REGS(NOSPPC, NOSPPC, NOSPPC, 0, NOSPPC)),
809 /* SDIV 1111 1011 1001 xxxx xxxx xxxx 1111 xxxx */
810 /* UDIV 1111 1011 1011 xxxx xxxx xxxx 1111 xxxx */
811 /* Other unallocated instructions... */
815 const union decode_item kprobe_decode_thumb32_table[] = {
818 * Load/store multiple instructions
819 * 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx
821 DECODE_TABLE (0xfe400000, 0xe8000000, t32_table_1110_100x_x0xx),
824 * Load/store dual, load/store exclusive, table branch
825 * 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx
827 DECODE_TABLE (0xfe400000, 0xe8400000, t32_table_1110_100x_x1xx),
830 * Data-processing (shifted register)
831 * 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx
833 DECODE_TABLE (0xfe000000, 0xea000000, t32_table_1110_101x),
836 * Coprocessor instructions
837 * 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx
839 DECODE_REJECT (0xfc000000, 0xec000000),
842 * Data-processing (modified immediate)
843 * 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx
845 DECODE_TABLE (0xfa008000, 0xf0000000, t32_table_1111_0x0x___0),
848 * Data-processing (plain binary immediate)
849 * 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx
851 DECODE_TABLE (0xfa008000, 0xf2000000, t32_table_1111_0x1x___0),
854 * Branches and miscellaneous control
855 * 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx
857 DECODE_TABLE (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1),
860 * Advanced SIMD element or structure load/store instructions
861 * 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx
863 DECODE_REJECT (0xff100000, 0xf9000000),
867 * 1111 100x x0x1 xxxx 1111 xxxx xxxx xxxx
869 DECODE_TABLE (0xfe50f000, 0xf810f000, t32_table_1111_100x_x0x1__1111),
872 * Store single data item
873 * 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx
874 * Load single data items
875 * 1111 100x xxx1 xxxx xxxx xxxx xxxx xxxx
877 DECODE_TABLE (0xfe000000, 0xf8000000, t32_table_1111_100x),
880 * Data-processing (register)
881 * 1111 1010 xxxx xxxx 1111 xxxx xxxx xxxx
883 DECODE_TABLE (0xff00f000, 0xfa00f000, t32_table_1111_1010___1111),
886 * Long multiply, long multiply accumulate, and divide
887 * 1111 1011 1xxx xxxx xxxx xxxx xxxx xxxx
889 DECODE_TABLE (0xff800000, 0xfb800000, t32_table_1111_1011_1),
892 * Coprocessor instructions
893 * 1111 11xx xxxx xxxx xxxx xxxx xxxx xxxx
898 static void __kprobes
899 t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
901 kprobe_opcode_t insn = p->opcode;
902 unsigned long pc = thumb_probe_pc(p);
903 int rm = (insn >> 3) & 0xf;
904 unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];
906 if (insn & (1 << 7)) /* BLX ? */
907 regs->ARM_lr = (unsigned long)p->addr + 2;
909 bx_write_pc(rmv, regs);
912 static void __kprobes
913 t16_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
915 kprobe_opcode_t insn = p->opcode;
916 unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3);
917 long index = insn & 0xff;
918 int rt = (insn >> 8) & 0x7;
919 regs->uregs[rt] = base[index];
922 static void __kprobes
923 t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs)
925 kprobe_opcode_t insn = p->opcode;
926 unsigned long* base = (unsigned long *)regs->ARM_sp;
927 long index = insn & 0xff;
928 int rt = (insn >> 8) & 0x7;
929 if (insn & 0x800) /* LDR */
930 regs->uregs[rt] = base[index];
932 base[index] = regs->uregs[rt];
935 static void __kprobes
936 t16_simulate_reladr(struct kprobe *p, struct pt_regs *regs)
938 kprobe_opcode_t insn = p->opcode;
939 unsigned long base = (insn & 0x800) ? regs->ARM_sp
940 : (thumb_probe_pc(p) & ~3);
941 long offset = insn & 0xff;
942 int rt = (insn >> 8) & 0x7;
943 regs->uregs[rt] = base + offset * 4;
946 static void __kprobes
947 t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs)
949 kprobe_opcode_t insn = p->opcode;
950 long imm = insn & 0x7f;
951 if (insn & 0x80) /* SUB */
952 regs->ARM_sp -= imm * 4;
954 regs->ARM_sp += imm * 4;
957 static void __kprobes
958 t16_simulate_cbz(struct kprobe *p, struct pt_regs *regs)
960 kprobe_opcode_t insn = p->opcode;
962 kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
963 if (nonzero & 0x800) {
964 long i = insn & 0x200;
965 long imm5 = insn & 0xf8;
966 unsigned long pc = thumb_probe_pc(p);
967 regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
971 static void __kprobes
972 t16_simulate_it(struct kprobe *p, struct pt_regs *regs)
975 * The 8 IT state bits are split into two parts in CPSR:
976 * ITSTATE<1:0> are in CPSR<26:25>
977 * ITSTATE<7:2> are in CPSR<15:10>
978 * The new IT state is in the lower byte of insn.
980 kprobe_opcode_t insn = p->opcode;
981 unsigned long cpsr = regs->ARM_cpsr;
982 cpsr &= ~PSR_IT_MASK;
983 cpsr |= (insn & 0xfc) << 8;
984 cpsr |= (insn & 0x03) << 25;
985 regs->ARM_cpsr = cpsr;
988 static void __kprobes
989 t16_singlestep_it(struct kprobe *p, struct pt_regs *regs)
992 t16_simulate_it(p, regs);
995 static enum kprobe_insn __kprobes
996 t16_decode_it(kprobe_opcode_t insn, struct arch_specific_insn *asi)
998 asi->insn_singlestep = t16_singlestep_it;
999 return INSN_GOOD_NO_SLOT;
1002 static void __kprobes
1003 t16_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
1005 kprobe_opcode_t insn = p->opcode;
1006 unsigned long pc = thumb_probe_pc(p);
1007 long offset = insn & 0x7f;
1008 offset -= insn & 0x80; /* Apply sign bit */
1009 regs->ARM_pc = pc + (offset * 2);
1012 static enum kprobe_insn __kprobes
1013 t16_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1015 int cc = (insn >> 8) & 0xf;
1016 asi->insn_check_cc = kprobe_condition_checks[cc];
1017 asi->insn_handler = t16_simulate_cond_branch;
1018 return INSN_GOOD_NO_SLOT;
1021 static void __kprobes
1022 t16_simulate_branch(struct kprobe *p, struct pt_regs *regs)
1024 kprobe_opcode_t insn = p->opcode;
1025 unsigned long pc = thumb_probe_pc(p);
1026 long offset = insn & 0x3ff;
1027 offset -= insn & 0x400; /* Apply sign bit */
1028 regs->ARM_pc = pc + (offset * 2);
1031 static unsigned long __kprobes
1032 t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
1034 unsigned long oldcpsr = regs->ARM_cpsr;
1035 unsigned long newcpsr;
1037 __asm__ __volatile__ (
1038 "msr cpsr_fs, %[oldcpsr] \n\t"
1039 "ldmia %[regs], {r0-r7} \n\t"
1041 "stmia %[regs], {r0-r7} \n\t"
1042 "mrs %[newcpsr], cpsr \n\t"
1043 : [newcpsr] "=r" (newcpsr)
1044 : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
1045 [fn] "r" (p->ainsn.insn_fn)
1046 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1047 "lr", "memory", "cc"
1050 return (oldcpsr & ~APSR_MASK) | (newcpsr & APSR_MASK);
1053 static void __kprobes
1054 t16_emulate_loregs_rwflags(struct kprobe *p, struct pt_regs *regs)
1056 regs->ARM_cpsr = t16_emulate_loregs(p, regs);
1059 static void __kprobes
1060 t16_emulate_loregs_noitrwflags(struct kprobe *p, struct pt_regs *regs)
1062 unsigned long cpsr = t16_emulate_loregs(p, regs);
1063 if (!in_it_block(cpsr))
1064 regs->ARM_cpsr = cpsr;
1067 static void __kprobes
1068 t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
1070 kprobe_opcode_t insn = p->opcode;
1071 unsigned long pc = thumb_probe_pc(p);
1072 int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
1073 int rm = (insn >> 3) & 0xf;
1075 register unsigned long rdnv asm("r1");
1076 register unsigned long rmv asm("r0");
1077 unsigned long cpsr = regs->ARM_cpsr;
1079 rdnv = (rdn == 15) ? pc : regs->uregs[rdn];
1080 rmv = (rm == 15) ? pc : regs->uregs[rm];
1082 __asm__ __volatile__ (
1083 "msr cpsr_fs, %[cpsr] \n\t"
1085 "mrs %[cpsr], cpsr \n\t"
1086 : "=r" (rdnv), [cpsr] "=r" (cpsr)
1087 : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
1088 : "lr", "memory", "cc"
1094 regs->uregs[rdn] = rdnv;
1095 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
1098 static enum kprobe_insn __kprobes
1099 t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1102 insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
1103 ((u16 *)asi->insn)[0] = insn;
1104 asi->insn_handler = t16_emulate_hiregs;
1108 static void __kprobes
1109 t16_emulate_push(struct kprobe *p, struct pt_regs *regs)
1111 __asm__ __volatile__ (
1112 "ldr r9, [%[regs], #13*4] \n\t"
1113 "ldr r8, [%[regs], #14*4] \n\t"
1114 "ldmia %[regs], {r0-r7} \n\t"
1116 "str r9, [%[regs], #13*4] \n\t"
1118 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
1119 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
1120 "lr", "memory", "cc"
1124 static enum kprobe_insn __kprobes
1125 t16_decode_push(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1128 * To simulate a PUSH we use a Thumb-2 "STMDB R9!, {registers}"
1129 * and call it with R9=SP and LR in the register list represented
1132 ((u16 *)asi->insn)[0] = 0xe929; /* 1st half STMDB R9!,{} */
1133 ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
1134 asi->insn_handler = t16_emulate_push;
1138 static void __kprobes
1139 t16_emulate_pop_nopc(struct kprobe *p, struct pt_regs *regs)
1141 __asm__ __volatile__ (
1142 "ldr r9, [%[regs], #13*4] \n\t"
1143 "ldmia %[regs], {r0-r7} \n\t"
1145 "stmia %[regs], {r0-r7} \n\t"
1146 "str r9, [%[regs], #13*4] \n\t"
1148 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
1149 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
1150 "lr", "memory", "cc"
1154 static void __kprobes
1155 t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
1157 register unsigned long pc asm("r8");
1159 __asm__ __volatile__ (
1160 "ldr r9, [%[regs], #13*4] \n\t"
1161 "ldmia %[regs], {r0-r7} \n\t"
1163 "stmia %[regs], {r0-r7} \n\t"
1164 "str r9, [%[regs], #13*4] \n\t"
1166 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
1167 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
1168 "lr", "memory", "cc"
1171 bx_write_pc(pc, regs);
1174 static enum kprobe_insn __kprobes
1175 t16_decode_pop(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1178 * To simulate a POP we use a Thumb-2 "LDMDB R9!, {registers}"
1179 * and call it with R9=SP and PC in the register list represented
1182 ((u16 *)asi->insn)[0] = 0xe8b9; /* 1st half LDMIA R9!,{} */
1183 ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
1184 asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc
1185 : t16_emulate_pop_nopc;
1189 static const union decode_item t16_table_1011[] = {
1190 /* Miscellaneous 16-bit instructions */
1192 /* ADD (SP plus immediate) 1011 0000 0xxx xxxx */
1193 /* SUB (SP minus immediate) 1011 0000 1xxx xxxx */
1194 DECODE_SIMULATE (0xff00, 0xb000, t16_simulate_add_sp_imm),
1196 /* CBZ 1011 00x1 xxxx xxxx */
1197 /* CBNZ 1011 10x1 xxxx xxxx */
1198 DECODE_SIMULATE (0xf500, 0xb100, t16_simulate_cbz),
1200 /* SXTH 1011 0010 00xx xxxx */
1201 /* SXTB 1011 0010 01xx xxxx */
1202 /* UXTH 1011 0010 10xx xxxx */
1203 /* UXTB 1011 0010 11xx xxxx */
1204 /* REV 1011 1010 00xx xxxx */
1205 /* REV16 1011 1010 01xx xxxx */
1206 /* ??? 1011 1010 10xx xxxx */
1207 /* REVSH 1011 1010 11xx xxxx */
1208 DECODE_REJECT (0xffc0, 0xba80),
1209 DECODE_EMULATE (0xf500, 0xb000, t16_emulate_loregs_rwflags),
1211 /* PUSH 1011 010x xxxx xxxx */
1212 DECODE_CUSTOM (0xfe00, 0xb400, t16_decode_push),
1213 /* POP 1011 110x xxxx xxxx */
1214 DECODE_CUSTOM (0xfe00, 0xbc00, t16_decode_pop),
1217 * If-Then, and hints
1218 * 1011 1111 xxxx xxxx
1221 /* YIELD 1011 1111 0001 0000 */
1222 DECODE_OR (0xffff, 0xbf10),
1223 /* SEV 1011 1111 0100 0000 */
1224 DECODE_EMULATE (0xffff, 0xbf40, kprobe_emulate_none),
1225 /* NOP 1011 1111 0000 0000 */
1226 /* WFE 1011 1111 0010 0000 */
1227 /* WFI 1011 1111 0011 0000 */
1228 DECODE_SIMULATE (0xffcf, 0xbf00, kprobe_simulate_nop),
1229 /* Unassigned hints 1011 1111 xxxx 0000 */
1230 DECODE_REJECT (0xff0f, 0xbf00),
1231 /* IT 1011 1111 xxxx xxxx */
1232 DECODE_CUSTOM (0xff00, 0xbf00, t16_decode_it),
1234 /* SETEND 1011 0110 010x xxxx */
1235 /* CPS 1011 0110 011x xxxx */
1236 /* BKPT 1011 1110 xxxx xxxx */
1237 /* And unallocated instructions... */
1241 const union decode_item kprobe_decode_thumb16_table[] = {
1244 * Shift (immediate), add, subtract, move, and compare
1245 * 00xx xxxx xxxx xxxx
1248 /* CMP (immediate) 0010 1xxx xxxx xxxx */
1249 DECODE_EMULATE (0xf800, 0x2800, t16_emulate_loregs_rwflags),
1251 /* ADD (register) 0001 100x xxxx xxxx */
1252 /* SUB (register) 0001 101x xxxx xxxx */
1253 /* LSL (immediate) 0000 0xxx xxxx xxxx */
1254 /* LSR (immediate) 0000 1xxx xxxx xxxx */
1255 /* ASR (immediate) 0001 0xxx xxxx xxxx */
1256 /* ADD (immediate, Thumb) 0001 110x xxxx xxxx */
1257 /* SUB (immediate, Thumb) 0001 111x xxxx xxxx */
1258 /* MOV (immediate) 0010 0xxx xxxx xxxx */
1259 /* ADD (immediate, Thumb) 0011 0xxx xxxx xxxx */
1260 /* SUB (immediate, Thumb) 0011 1xxx xxxx xxxx */
1261 DECODE_EMULATE (0xc000, 0x0000, t16_emulate_loregs_noitrwflags),
1264 * 16-bit Thumb data-processing instructions
1265 * 0100 00xx xxxx xxxx
1268 /* TST (register) 0100 0010 00xx xxxx */
1269 DECODE_EMULATE (0xffc0, 0x4200, t16_emulate_loregs_rwflags),
1270 /* CMP (register) 0100 0010 10xx xxxx */
1271 /* CMN (register) 0100 0010 11xx xxxx */
1272 DECODE_EMULATE (0xff80, 0x4280, t16_emulate_loregs_rwflags),
1273 /* AND (register) 0100 0000 00xx xxxx */
1274 /* EOR (register) 0100 0000 01xx xxxx */
1275 /* LSL (register) 0100 0000 10xx xxxx */
1276 /* LSR (register) 0100 0000 11xx xxxx */
1277 /* ASR (register) 0100 0001 00xx xxxx */
1278 /* ADC (register) 0100 0001 01xx xxxx */
1279 /* SBC (register) 0100 0001 10xx xxxx */
1280 /* ROR (register) 0100 0001 11xx xxxx */
1281 /* RSB (immediate) 0100 0010 01xx xxxx */
1282 /* ORR (register) 0100 0011 00xx xxxx */
1283 /* MUL 0100 0011 00xx xxxx */
1284 /* BIC (register) 0100 0011 10xx xxxx */
1285 /* MVN (register) 0100 0011 10xx xxxx */
1286 DECODE_EMULATE (0xfc00, 0x4000, t16_emulate_loregs_noitrwflags),
1289 * Special data instructions and branch and exchange
1290 * 0100 01xx xxxx xxxx
1293 /* BLX pc 0100 0111 1111 1xxx */
1294 DECODE_REJECT (0xfff8, 0x47f8),
1296 /* BX (register) 0100 0111 0xxx xxxx */
1297 /* BLX (register) 0100 0111 1xxx xxxx */
1298 DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx),
1300 /* ADD pc, pc 0100 0100 1111 1111 */
1301 DECODE_REJECT (0xffff, 0x44ff),
1303 /* ADD (register) 0100 0100 xxxx xxxx */
1304 /* CMP (register) 0100 0101 xxxx xxxx */
1305 /* MOV (register) 0100 0110 xxxx xxxx */
1306 DECODE_CUSTOM (0xfc00, 0x4400, t16_decode_hiregs),
1309 * Load from Literal Pool
1310 * LDR (literal) 0100 1xxx xxxx xxxx
1312 DECODE_SIMULATE (0xf800, 0x4800, t16_simulate_ldr_literal),
1315 * 16-bit Thumb Load/store instructions
1316 * 0101 xxxx xxxx xxxx
1317 * 011x xxxx xxxx xxxx
1318 * 100x xxxx xxxx xxxx
1321 /* STR (register) 0101 000x xxxx xxxx */
1322 /* STRH (register) 0101 001x xxxx xxxx */
1323 /* STRB (register) 0101 010x xxxx xxxx */
1324 /* LDRSB (register) 0101 011x xxxx xxxx */
1325 /* LDR (register) 0101 100x xxxx xxxx */
1326 /* LDRH (register) 0101 101x xxxx xxxx */
1327 /* LDRB (register) 0101 110x xxxx xxxx */
1328 /* LDRSH (register) 0101 111x xxxx xxxx */
1329 /* STR (immediate, Thumb) 0110 0xxx xxxx xxxx */
1330 /* LDR (immediate, Thumb) 0110 1xxx xxxx xxxx */
1331 /* STRB (immediate, Thumb) 0111 0xxx xxxx xxxx */
1332 /* LDRB (immediate, Thumb) 0111 1xxx xxxx xxxx */
1333 DECODE_EMULATE (0xc000, 0x4000, t16_emulate_loregs_rwflags),
1334 /* STRH (immediate, Thumb) 1000 0xxx xxxx xxxx */
1335 /* LDRH (immediate, Thumb) 1000 1xxx xxxx xxxx */
1336 DECODE_EMULATE (0xf000, 0x8000, t16_emulate_loregs_rwflags),
1337 /* STR (immediate, Thumb) 1001 0xxx xxxx xxxx */
1338 /* LDR (immediate, Thumb) 1001 1xxx xxxx xxxx */
1339 DECODE_SIMULATE (0xf000, 0x9000, t16_simulate_ldrstr_sp_relative),
1342 * Generate PC-/SP-relative address
1343 * ADR (literal) 1010 0xxx xxxx xxxx
1344 * ADD (SP plus immediate) 1010 1xxx xxxx xxxx
1346 DECODE_SIMULATE (0xf000, 0xa000, t16_simulate_reladr),
1349 * Miscellaneous 16-bit instructions
1350 * 1011 xxxx xxxx xxxx
1352 DECODE_TABLE (0xf000, 0xb000, t16_table_1011),
1354 /* STM 1100 0xxx xxxx xxxx */
1355 /* LDM 1100 1xxx xxxx xxxx */
1356 DECODE_EMULATE (0xf000, 0xc000, t16_emulate_loregs_rwflags),
1359 * Conditional branch, and Supervisor Call
1362 /* Permanently UNDEFINED 1101 1110 xxxx xxxx */
1363 /* SVC 1101 1111 xxxx xxxx */
1364 DECODE_REJECT (0xfe00, 0xde00),
1366 /* Conditional branch 1101 xxxx xxxx xxxx */
1367 DECODE_CUSTOM (0xf000, 0xd000, t16_decode_cond_branch),
1370 * Unconditional branch
1371 * B 1110 0xxx xxxx xxxx
1373 DECODE_SIMULATE (0xf800, 0xe000, t16_simulate_branch),
1378 static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
1380 if (unlikely(in_it_block(cpsr)))
1381 return kprobe_condition_checks[current_cond(cpsr)](cpsr);
1385 static void __kprobes thumb16_singlestep(struct kprobe *p, struct pt_regs *regs)
1388 p->ainsn.insn_handler(p, regs);
1389 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
1392 static void __kprobes thumb32_singlestep(struct kprobe *p, struct pt_regs *regs)
1395 p->ainsn.insn_handler(p, regs);
1396 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
1399 enum kprobe_insn __kprobes
1400 thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1402 asi->insn_singlestep = thumb16_singlestep;
1403 asi->insn_check_cc = thumb_check_cc;
1404 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true);
1407 enum kprobe_insn __kprobes
1408 thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1410 asi->insn_singlestep = thumb32_singlestep;
1411 asi->insn_check_cc = thumb_check_cc;
1412 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb32_table, true);