2 * arch/arm/kernel/kprobes-decode.c
4 * Copyright (C) 2006, 2007 Motorola Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
17 * We do not have hardware single-stepping on ARM, This
18 * effort is further complicated by the ARM not having a
19 * "next PC" register. Instructions that change the PC
20 * can't be safely single-stepped in a MP environment, so
21 * we have a lot of work to do:
23 * In the prepare phase:
24 * *) If it is an instruction that does anything
25 * with the CPU mode, we reject it for a kprobe.
26 * (This is out of laziness rather than need. The
27 * instructions could be simulated.)
29 * *) Otherwise, decode the instruction rewriting its
30 * registers to take fixed, ordered registers and
31 * setting a handler for it to run the instruction.
33 * In the execution phase by an instruction's handler:
35 * *) If the PC is written to by the instruction, the
36 * instruction must be fully simulated in software.
37 * If it is a conditional instruction, the handler
38 * will use insn[0] to copy its condition code to
39 * set r0 to 1 and insn[1] to "mov pc, lr" to return.
41 * *) Otherwise, a modified form of the instruction is
42 * directly executed. Its handler calls the
43 * instruction in insn[0]. In insn[1] is a
44 * "mov pc, lr" to return.
46 * Before calling, load up the reordered registers
47 * from the original instruction's registers. If one
48 * of the original input registers is the PC, compute
49 * and adjust the appropriate input register.
51 * After call completes, copy the output registers to
52 * the original instruction's original registers.
54 * We don't use a real breakpoint instruction since that
55 * would have us in the kernel go from SVC mode to SVC
56 * mode losing the link register. Instead we use an
57 * undefined instruction. To simplify processing, the
58 * undefined instruction used for kprobes must be reserved
59 * exclusively for kprobes use.
61 * TODO: ifdef out some instruction decoding based on architecture.
64 #include <linux/kernel.h>
65 #include <linux/kprobes.h>
67 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
69 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
71 #define PSR_fs (PSR_f|PSR_s)
73 #define KPROBE_RETURN_INSTRUCTION 0xe1a0f00e /* mov pc, lr */
74 #define SET_R0_TRUE_INSTRUCTION 0xe3a00001 /* mov r0, #1 */
76 #define truecc_insn(insn) (((insn) & 0xf0000000) | \
77 (SET_R0_TRUE_INSTRUCTION & 0x0fffffff))
79 typedef long (insn_0arg_fn_t)(void);
80 typedef long (insn_1arg_fn_t)(long);
81 typedef long (insn_2arg_fn_t)(long, long);
82 typedef long (insn_3arg_fn_t)(long, long, long);
83 typedef long (insn_4arg_fn_t)(long, long, long, long);
84 typedef long long (insn_llret_0arg_fn_t)(void);
85 typedef long long (insn_llret_3arg_fn_t)(long, long, long);
86 typedef long long (insn_llret_4arg_fn_t)(long, long, long, long);
90 #ifdef __LITTLE_ENDIAN
91 struct { long r0, r1; };
93 struct { long r1, r0; };
98 * For STR and STM instructions, an ARM core may choose to use either
99 * a +8 or a +12 displacement from the current instruction's address.
100 * Whichever value is chosen for a given core, it must be the same for
101 * both instructions and may not change. This function measures it.
104 static int str_pc_offset;
106 static void __init find_str_pc_offset(void)
108 int addr, scratch, ret;
111 "sub %[ret], pc, #4 \n\t"
112 "str pc, %[addr] \n\t"
113 "ldr %[scr], %[addr] \n\t"
114 "sub %[ret], %[scr], %[ret] \n\t"
115 : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
121 * The insnslot_?arg_r[w]flags() functions below are to keep the
122 * msr -> *fn -> mrs instruction sequences indivisible so that
123 * the state of the CPSR flags aren't inadvertently modified
124 * just before or just after the call.
127 static inline long __kprobes
128 insnslot_0arg_rflags(long cpsr, insn_0arg_fn_t *fn)
130 register long ret asm("r0");
132 __asm__ __volatile__ (
133 "msr cpsr_fs, %[cpsr] \n\t"
137 : [cpsr] "r" (cpsr), [fn] "r" (fn)
143 static inline long long __kprobes
144 insnslot_llret_0arg_rflags(long cpsr, insn_llret_0arg_fn_t *fn)
146 register long ret0 asm("r0");
147 register long ret1 asm("r1");
150 __asm__ __volatile__ (
151 "msr cpsr_fs, %[cpsr] \n\t"
154 : "=r" (ret0), "=r" (ret1)
155 : [cpsr] "r" (cpsr), [fn] "r" (fn)
163 static inline long __kprobes
164 insnslot_1arg_rflags(long r0, long cpsr, insn_1arg_fn_t *fn)
166 register long rr0 asm("r0") = r0;
167 register long ret asm("r0");
169 __asm__ __volatile__ (
170 "msr cpsr_fs, %[cpsr] \n\t"
174 : "0" (rr0), [cpsr] "r" (cpsr), [fn] "r" (fn)
180 static inline long __kprobes
181 insnslot_2arg_rflags(long r0, long r1, long cpsr, insn_2arg_fn_t *fn)
183 register long rr0 asm("r0") = r0;
184 register long rr1 asm("r1") = r1;
185 register long ret asm("r0");
187 __asm__ __volatile__ (
188 "msr cpsr_fs, %[cpsr] \n\t"
192 : "0" (rr0), "r" (rr1),
193 [cpsr] "r" (cpsr), [fn] "r" (fn)
199 static inline long __kprobes
200 insnslot_3arg_rflags(long r0, long r1, long r2, long cpsr, insn_3arg_fn_t *fn)
202 register long rr0 asm("r0") = r0;
203 register long rr1 asm("r1") = r1;
204 register long rr2 asm("r2") = r2;
205 register long ret asm("r0");
207 __asm__ __volatile__ (
208 "msr cpsr_fs, %[cpsr] \n\t"
212 : "0" (rr0), "r" (rr1), "r" (rr2),
213 [cpsr] "r" (cpsr), [fn] "r" (fn)
219 static inline long long __kprobes
220 insnslot_llret_3arg_rflags(long r0, long r1, long r2, long cpsr,
221 insn_llret_3arg_fn_t *fn)
223 register long rr0 asm("r0") = r0;
224 register long rr1 asm("r1") = r1;
225 register long rr2 asm("r2") = r2;
226 register long ret0 asm("r0");
227 register long ret1 asm("r1");
230 __asm__ __volatile__ (
231 "msr cpsr_fs, %[cpsr] \n\t"
234 : "=r" (ret0), "=r" (ret1)
235 : "0" (rr0), "r" (rr1), "r" (rr2),
236 [cpsr] "r" (cpsr), [fn] "r" (fn)
244 static inline long __kprobes
245 insnslot_4arg_rflags(long r0, long r1, long r2, long r3, long cpsr,
248 register long rr0 asm("r0") = r0;
249 register long rr1 asm("r1") = r1;
250 register long rr2 asm("r2") = r2;
251 register long rr3 asm("r3") = r3;
252 register long ret asm("r0");
254 __asm__ __volatile__ (
255 "msr cpsr_fs, %[cpsr] \n\t"
259 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
260 [cpsr] "r" (cpsr), [fn] "r" (fn)
266 static inline long __kprobes
267 insnslot_1arg_rwflags(long r0, long *cpsr, insn_1arg_fn_t *fn)
269 register long rr0 asm("r0") = r0;
270 register long ret asm("r0");
271 long oldcpsr = *cpsr;
274 __asm__ __volatile__ (
275 "msr cpsr_fs, %[oldcpsr] \n\t"
278 "mrs %[newcpsr], cpsr \n\t"
279 : "=r" (ret), [newcpsr] "=r" (newcpsr)
280 : "0" (rr0), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
283 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
287 static inline long __kprobes
288 insnslot_2arg_rwflags(long r0, long r1, long *cpsr, insn_2arg_fn_t *fn)
290 register long rr0 asm("r0") = r0;
291 register long rr1 asm("r1") = r1;
292 register long ret asm("r0");
293 long oldcpsr = *cpsr;
296 __asm__ __volatile__ (
297 "msr cpsr_fs, %[oldcpsr] \n\t"
300 "mrs %[newcpsr], cpsr \n\t"
301 : "=r" (ret), [newcpsr] "=r" (newcpsr)
302 : "0" (rr0), "r" (rr1), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
305 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
309 static inline long __kprobes
310 insnslot_3arg_rwflags(long r0, long r1, long r2, long *cpsr,
313 register long rr0 asm("r0") = r0;
314 register long rr1 asm("r1") = r1;
315 register long rr2 asm("r2") = r2;
316 register long ret asm("r0");
317 long oldcpsr = *cpsr;
320 __asm__ __volatile__ (
321 "msr cpsr_fs, %[oldcpsr] \n\t"
324 "mrs %[newcpsr], cpsr \n\t"
325 : "=r" (ret), [newcpsr] "=r" (newcpsr)
326 : "0" (rr0), "r" (rr1), "r" (rr2),
327 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
330 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
334 static inline long __kprobes
335 insnslot_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
338 register long rr0 asm("r0") = r0;
339 register long rr1 asm("r1") = r1;
340 register long rr2 asm("r2") = r2;
341 register long rr3 asm("r3") = r3;
342 register long ret asm("r0");
343 long oldcpsr = *cpsr;
346 __asm__ __volatile__ (
347 "msr cpsr_fs, %[oldcpsr] \n\t"
350 "mrs %[newcpsr], cpsr \n\t"
351 : "=r" (ret), [newcpsr] "=r" (newcpsr)
352 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
353 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
356 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
360 static inline long long __kprobes
361 insnslot_llret_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
362 insn_llret_4arg_fn_t *fn)
364 register long rr0 asm("r0") = r0;
365 register long rr1 asm("r1") = r1;
366 register long rr2 asm("r2") = r2;
367 register long rr3 asm("r3") = r3;
368 register long ret0 asm("r0");
369 register long ret1 asm("r1");
370 long oldcpsr = *cpsr;
374 __asm__ __volatile__ (
375 "msr cpsr_fs, %[oldcpsr] \n\t"
378 "mrs %[newcpsr], cpsr \n\t"
379 : "=r" (ret0), "=r" (ret1), [newcpsr] "=r" (newcpsr)
380 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
381 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
384 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
391 * To avoid the complications of mimicing single-stepping on a
392 * processor without a Next-PC or a single-step mode, and to
393 * avoid having to deal with the side-effects of boosting, we
394 * simulate or emulate (almost) all ARM instructions.
396 * "Simulation" is where the instruction's behavior is duplicated in
397 * C code. "Emulation" is where the original instruction is rewritten
398 * and executed, often by altering its registers.
400 * By having all behavior of the kprobe'd instruction completed before
401 * returning from the kprobe_handler(), all locks (scheduler and
402 * interrupt) can safely be released. There is no need for secondary
403 * breakpoints, no race with MP or preemptable kernels, nor having to
404 * clean up resources counts at a later time impacting overall system
405 * performance. By rewriting the instruction, only the minimum registers
406 * need to be loaded and saved back optimizing performance.
408 * Calling the insnslot_*_rwflags version of a function doesn't hurt
409 * anything even when the CPSR flags aren't updated by the
410 * instruction. It's just a little slower in return for saving
411 * a little space by not having a duplicate function that doesn't
412 * update the flags. (The same optimization can be said for
413 * instructions that do or don't perform register writeback)
414 * Also, instructions can either read the flags, only write the
415 * flags, or read and write the flags. To save combinations
416 * rather than for sheer performance, flag functions just assume
417 * read and write of flags.
420 static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs)
422 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
423 kprobe_opcode_t insn = p->opcode;
424 long iaddr = (long)p->addr;
425 int disp = branch_displacement(insn);
427 if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
430 if (insn & (1 << 24))
431 regs->ARM_lr = iaddr + 4;
433 regs->ARM_pc = iaddr + 8 + disp;
436 static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs)
438 kprobe_opcode_t insn = p->opcode;
439 long iaddr = (long)p->addr;
440 int disp = branch_displacement(insn);
442 regs->ARM_lr = iaddr + 4;
443 regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
444 regs->ARM_cpsr |= PSR_T_BIT;
447 static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs)
449 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
450 kprobe_opcode_t insn = p->opcode;
452 long rmv = regs->uregs[rm];
454 if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
458 regs->ARM_lr = (long)p->addr + 4;
460 regs->ARM_pc = rmv & ~0x1;
461 regs->ARM_cpsr &= ~PSR_T_BIT;
463 regs->ARM_cpsr |= PSR_T_BIT;
466 static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
468 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
469 kprobe_opcode_t insn = p->opcode;
470 int rn = (insn >> 16) & 0xf;
471 int lbit = insn & (1 << 20);
472 int wbit = insn & (1 << 21);
473 int ubit = insn & (1 << 23);
474 int pbit = insn & (1 << 24);
475 long *addr = (long *)regs->uregs[rn];
479 if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
483 reg_bit_vector = insn & 0xffff;
484 while (reg_bit_vector) {
485 reg_bit_vector &= (reg_bit_vector - 1);
491 addr += (!pbit == !ubit);
493 reg_bit_vector = insn & 0xffff;
494 while (reg_bit_vector) {
495 int reg = __ffs(reg_bit_vector);
496 reg_bit_vector &= (reg_bit_vector - 1);
498 regs->uregs[reg] = *addr++;
500 *addr++ = regs->uregs[reg];
506 addr -= (!pbit == !ubit);
507 regs->uregs[rn] = (long)addr;
511 static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs)
513 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
515 if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
518 regs->ARM_pc = (long)p->addr + str_pc_offset;
519 simulate_ldm1stm1(p, regs);
520 regs->ARM_pc = (long)p->addr + 4;
523 static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs)
525 regs->uregs[12] = regs->uregs[13];
528 static void __kprobes emulate_ldcstc(struct kprobe *p, struct pt_regs *regs)
530 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
531 kprobe_opcode_t insn = p->opcode;
532 int rn = (insn >> 16) & 0xf;
533 long rnv = regs->uregs[rn];
535 /* Save Rn in case of writeback. */
536 regs->uregs[rn] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
539 static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs)
541 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
542 kprobe_opcode_t insn = p->opcode;
543 long ppc = (long)p->addr + 8;
544 int rd = (insn >> 12) & 0xf;
545 int rn = (insn >> 16) & 0xf;
546 int rm = insn & 0xf; /* rm may be invalid, don't care. */
547 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
548 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
550 /* Not following the C calling convention here, so need asm(). */
551 __asm__ __volatile__ (
554 "msr cpsr_fs, %[cpsr]\n\t"
556 "mov pc, %[i_fn] \n\t"
557 "str r0, %[rn] \n\t" /* in case of writeback */
558 "str r2, %[rd0] \n\t"
559 "str r3, %[rd1] \n\t"
561 [rd0] "=m" (regs->uregs[rd]),
562 [rd1] "=m" (regs->uregs[rd+1])
564 [cpsr] "r" (regs->ARM_cpsr),
566 : "r0", "r1", "r2", "r3", "lr", "cc"
569 regs->uregs[rn] = rnv; /* Save Rn in case of writeback. */
572 static void __kprobes emulate_strd(struct kprobe *p, struct pt_regs *regs)
574 insn_4arg_fn_t *i_fn = (insn_4arg_fn_t *)&p->ainsn.insn[0];
575 kprobe_opcode_t insn = p->opcode;
576 long ppc = (long)p->addr + 8;
577 int rd = (insn >> 12) & 0xf;
578 int rn = (insn >> 16) & 0xf;
580 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
581 /* rm/rmv may be invalid, don't care. */
582 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
585 rnv_wb = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd],
587 regs->ARM_cpsr, i_fn);
589 regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */
592 static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs)
594 insn_llret_3arg_fn_t *i_fn = (insn_llret_3arg_fn_t *)&p->ainsn.insn[0];
595 kprobe_opcode_t insn = p->opcode;
596 long ppc = (long)p->addr + 8;
598 int rd = (insn >> 12) & 0xf;
599 int rn = (insn >> 16) & 0xf;
602 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
603 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
604 long cpsr = regs->ARM_cpsr;
606 fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn);
608 regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */
612 #if __LINUX_ARM_ARCH__ >= 5
616 regs->ARM_cpsr = cpsr;
622 regs->uregs[rd] = rdv;
625 static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs)
627 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
628 kprobe_opcode_t insn = p->opcode;
629 long iaddr = (long)p->addr;
630 int rd = (insn >> 12) & 0xf;
631 int rn = (insn >> 16) & 0xf;
633 long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd];
634 long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn];
635 long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */
638 rnv_wb = insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn);
640 regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */
643 static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs)
645 insn_llret_0arg_fn_t *i_fn = (insn_llret_0arg_fn_t *)&p->ainsn.insn[0];
646 kprobe_opcode_t insn = p->opcode;
648 int rd = (insn >> 12) & 0xf;
649 int rn = (insn >> 16) & 0xf;
651 fnr.dr = insnslot_llret_0arg_rflags(regs->ARM_cpsr, i_fn);
652 regs->uregs[rn] = fnr.r0;
653 regs->uregs[rd] = fnr.r1;
656 static void __kprobes emulate_mcrr(struct kprobe *p, struct pt_regs *regs)
658 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
659 kprobe_opcode_t insn = p->opcode;
660 int rd = (insn >> 12) & 0xf;
661 int rn = (insn >> 16) & 0xf;
662 long rnv = regs->uregs[rn];
663 long rdv = regs->uregs[rd];
665 insnslot_2arg_rflags(rnv, rdv, regs->ARM_cpsr, i_fn);
668 static void __kprobes emulate_sat(struct kprobe *p, struct pt_regs *regs)
670 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
671 kprobe_opcode_t insn = p->opcode;
672 int rd = (insn >> 12) & 0xf;
674 long rmv = regs->uregs[rm];
677 regs->uregs[rd] = insnslot_1arg_rwflags(rmv, ®s->ARM_cpsr, i_fn);
680 static void __kprobes emulate_sel(struct kprobe *p, struct pt_regs *regs)
682 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
683 kprobe_opcode_t insn = p->opcode;
684 int rd = (insn >> 12) & 0xf;
685 int rn = (insn >> 16) & 0xf;
687 long rnv = regs->uregs[rn];
688 long rmv = regs->uregs[rm];
691 regs->uregs[rd] = insnslot_2arg_rflags(rnv, rmv, regs->ARM_cpsr, i_fn);
694 static void __kprobes emulate_none(struct kprobe *p, struct pt_regs *regs)
696 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
698 insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
701 static void __kprobes emulate_rd12(struct kprobe *p, struct pt_regs *regs)
703 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
704 kprobe_opcode_t insn = p->opcode;
705 int rd = (insn >> 12) & 0xf;
707 regs->uregs[rd] = insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
710 static void __kprobes emulate_ird12(struct kprobe *p, struct pt_regs *regs)
712 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
713 kprobe_opcode_t insn = p->opcode;
714 int ird = (insn >> 12) & 0xf;
716 insnslot_1arg_rflags(regs->uregs[ird], regs->ARM_cpsr, i_fn);
719 static void __kprobes emulate_rn16(struct kprobe *p, struct pt_regs *regs)
721 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
722 kprobe_opcode_t insn = p->opcode;
723 int rn = (insn >> 16) & 0xf;
724 long rnv = regs->uregs[rn];
726 insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
729 static void __kprobes emulate_rd12rm0(struct kprobe *p, struct pt_regs *regs)
731 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
732 kprobe_opcode_t insn = p->opcode;
733 int rd = (insn >> 12) & 0xf;
735 long rmv = regs->uregs[rm];
737 regs->uregs[rd] = insnslot_1arg_rflags(rmv, regs->ARM_cpsr, i_fn);
740 static void __kprobes
741 emulate_rd12rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
743 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
744 kprobe_opcode_t insn = p->opcode;
745 int rd = (insn >> 12) & 0xf;
746 int rn = (insn >> 16) & 0xf;
748 long rnv = regs->uregs[rn];
749 long rmv = regs->uregs[rm];
752 insnslot_2arg_rwflags(rnv, rmv, ®s->ARM_cpsr, i_fn);
755 static void __kprobes
756 emulate_rd16rn12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
758 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
759 kprobe_opcode_t insn = p->opcode;
760 int rd = (insn >> 16) & 0xf;
761 int rn = (insn >> 12) & 0xf;
762 int rs = (insn >> 8) & 0xf;
764 long rnv = regs->uregs[rn];
765 long rsv = regs->uregs[rs];
766 long rmv = regs->uregs[rm];
769 insnslot_3arg_rwflags(rnv, rsv, rmv, ®s->ARM_cpsr, i_fn);
772 static void __kprobes
773 emulate_rd16rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
775 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
776 kprobe_opcode_t insn = p->opcode;
777 int rd = (insn >> 16) & 0xf;
778 int rs = (insn >> 8) & 0xf;
780 long rsv = regs->uregs[rs];
781 long rmv = regs->uregs[rm];
784 insnslot_2arg_rwflags(rsv, rmv, ®s->ARM_cpsr, i_fn);
787 static void __kprobes
788 emulate_rdhi16rdlo12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
790 insn_llret_4arg_fn_t *i_fn = (insn_llret_4arg_fn_t *)&p->ainsn.insn[0];
791 kprobe_opcode_t insn = p->opcode;
793 int rdhi = (insn >> 16) & 0xf;
794 int rdlo = (insn >> 12) & 0xf;
795 int rs = (insn >> 8) & 0xf;
797 long rsv = regs->uregs[rs];
798 long rmv = regs->uregs[rm];
800 fnr.dr = insnslot_llret_4arg_rwflags(regs->uregs[rdhi],
801 regs->uregs[rdlo], rsv, rmv,
802 ®s->ARM_cpsr, i_fn);
803 regs->uregs[rdhi] = fnr.r0;
804 regs->uregs[rdlo] = fnr.r1;
807 static void __kprobes
808 emulate_alu_imm_rflags(struct kprobe *p, struct pt_regs *regs)
810 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
811 kprobe_opcode_t insn = p->opcode;
812 int rd = (insn >> 12) & 0xf;
813 int rn = (insn >> 16) & 0xf;
814 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
816 regs->uregs[rd] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
819 static void __kprobes
820 emulate_alu_imm_rwflags(struct kprobe *p, struct pt_regs *regs)
822 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
823 kprobe_opcode_t insn = p->opcode;
824 int rd = (insn >> 12) & 0xf;
825 int rn = (insn >> 16) & 0xf;
826 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
828 regs->uregs[rd] = insnslot_1arg_rwflags(rnv, ®s->ARM_cpsr, i_fn);
831 static void __kprobes
832 emulate_alu_rflags(struct kprobe *p, struct pt_regs *regs)
834 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
835 kprobe_opcode_t insn = p->opcode;
836 long ppc = (long)p->addr + 8;
837 int rd = (insn >> 12) & 0xf;
838 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
839 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
841 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
842 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
843 long rsv = regs->uregs[rs];
846 insnslot_3arg_rflags(rnv, rmv, rsv, regs->ARM_cpsr, i_fn);
849 static void __kprobes
850 emulate_alu_rwflags(struct kprobe *p, struct pt_regs *regs)
852 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
853 kprobe_opcode_t insn = p->opcode;
854 long ppc = (long)p->addr + 8;
855 int rd = (insn >> 12) & 0xf;
856 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
857 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
859 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
860 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
861 long rsv = regs->uregs[rs];
864 insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn);
867 static enum kprobe_insn __kprobes
868 prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi)
870 int ibit = (insn & (1 << 26)) ? 25 : 22;
873 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
874 if (insn & (1 << ibit)) {
876 insn |= 2; /* Rm = r2 */
879 asi->insn_handler = (insn & (1 << 20)) ? emulate_ldr : emulate_str;
883 static enum kprobe_insn __kprobes
884 prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi)
886 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
888 asi->insn_handler = emulate_rd12rm0;
892 static enum kprobe_insn __kprobes
893 prep_emulate_rd12(kprobe_opcode_t insn, struct arch_specific_insn *asi)
895 insn &= 0xffff0fff; /* Rd = r0 */
897 asi->insn_handler = emulate_rd12;
901 static enum kprobe_insn __kprobes
902 prep_emulate_rd12rn16rm0_wflags(kprobe_opcode_t insn,
903 struct arch_specific_insn *asi)
905 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
906 insn |= 0x00000001; /* Rm = r1 */
908 asi->insn_handler = emulate_rd12rn16rm0_rwflags;
912 static enum kprobe_insn __kprobes
913 prep_emulate_rd16rs8rm0_wflags(kprobe_opcode_t insn,
914 struct arch_specific_insn *asi)
916 insn &= 0xfff0f0f0; /* Rd = r0, Rs = r0 */
917 insn |= 0x00000001; /* Rm = r1 */
919 asi->insn_handler = emulate_rd16rs8rm0_rwflags;
923 static enum kprobe_insn __kprobes
924 prep_emulate_rd16rn12rs8rm0_wflags(kprobe_opcode_t insn,
925 struct arch_specific_insn *asi)
927 insn &= 0xfff000f0; /* Rd = r0, Rn = r0 */
928 insn |= 0x00000102; /* Rs = r1, Rm = r2 */
930 asi->insn_handler = emulate_rd16rn12rs8rm0_rwflags;
934 static enum kprobe_insn __kprobes
935 prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn,
936 struct arch_specific_insn *asi)
938 insn &= 0xfff000f0; /* RdHi = r0, RdLo = r1 */
939 insn |= 0x00001203; /* Rs = r2, Rm = r3 */
941 asi->insn_handler = emulate_rdhi16rdlo12rs8rm0_rwflags;
946 * For the instruction masking and comparisons in all the "space_*"
947 * functions below, Do _not_ rearrange the order of tests unless
948 * you're very, very sure of what you are doing. For the sake of
949 * efficiency, the masks for some tests sometimes assume other test
950 * have been done prior to them so the number of patterns to test
951 * for an instruction set can be as broad as possible to reduce the
952 * number of tests needed.
955 static enum kprobe_insn __kprobes
956 space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi)
958 /* CPS mmod == 1 : 1111 0001 0000 xx10 xxxx xxxx xx0x xxxx */
959 /* RFE : 1111 100x x0x1 xxxx xxxx 1010 xxxx xxxx */
960 /* SRS : 1111 100x x1x0 1101 xxxx 0101 xxxx xxxx */
961 if ((insn & 0xfff30020) == 0xf1020000 ||
962 (insn & 0xfe500f00) == 0xf8100a00 ||
963 (insn & 0xfe5f0f00) == 0xf84d0500)
964 return INSN_REJECTED;
966 /* PLD : 1111 01x1 x101 xxxx xxxx xxxx xxxx xxxx : */
967 if ((insn & 0xfd700000) == 0xf4500000) {
968 insn &= 0xfff0ffff; /* Rn = r0 */
970 asi->insn_handler = emulate_rn16;
974 /* BLX(1) : 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx : */
975 if ((insn & 0xfe000000) == 0xfa000000) {
976 asi->insn_handler = simulate_blx1;
977 return INSN_GOOD_NO_SLOT;
980 /* SETEND : 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
981 /* CDP2 : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
982 if ((insn & 0xffff00f0) == 0xf1010000 ||
983 (insn & 0xff000010) == 0xfe000000) {
985 asi->insn_handler = emulate_none;
989 /* MCRR2 : 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
990 /* MRRC2 : 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
991 if ((insn & 0xffe00000) == 0xfc400000) {
992 insn &= 0xfff00fff; /* Rn = r0 */
993 insn |= 0x00001000; /* Rd = r1 */
996 (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
1000 /* LDC2 : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
1001 /* STC2 : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
1002 if ((insn & 0xfe000000) == 0xfc000000) {
1003 insn &= 0xfff0ffff; /* Rn = r0 */
1004 asi->insn[0] = insn;
1005 asi->insn_handler = emulate_ldcstc;
1009 /* MCR2 : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1010 /* MRC2 : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
1011 insn &= 0xffff0fff; /* Rd = r0 */
1012 asi->insn[0] = insn;
1013 asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
1017 static enum kprobe_insn __kprobes
1018 space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1020 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx xxx0 xxxx */
1021 if ((insn & 0x0f900010) == 0x01000000) {
1023 /* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
1024 /* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
1025 if ((insn & 0x0ff000f0) == 0x01200020 ||
1026 (insn & 0x0fb000f0) == 0x01200000)
1027 return INSN_REJECTED;
1029 /* MRS : cccc 0001 0x00 xxxx xxxx xxxx 0000 xxxx */
1030 if ((insn & 0x0fb00010) == 0x01000000)
1031 return prep_emulate_rd12(insn, asi);
1033 /* SMLALxy : cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
1034 if ((insn & 0x0ff00090) == 0x01400080)
1035 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1037 /* SMULWy : cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
1038 /* SMULxy : cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
1039 if ((insn & 0x0ff000b0) == 0x012000a0 ||
1040 (insn & 0x0ff00090) == 0x01600080)
1041 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1043 /* SMLAxy : cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx : Q */
1044 /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 0x00 xxxx : Q */
1045 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1049 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx 0xx1 xxxx */
1050 else if ((insn & 0x0f900090) == 0x01000010) {
1052 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1053 if ((insn & 0xfff000f0) == 0xe1200070)
1054 return INSN_REJECTED;
1056 /* BLX(2) : cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
1057 /* BX : cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
1058 if ((insn & 0x0ff000d0) == 0x01200010) {
1059 asi->insn[0] = truecc_insn(insn);
1060 asi->insn_handler = simulate_blx2bx;
1064 /* CLZ : cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
1065 if ((insn & 0x0ff000f0) == 0x01600010)
1066 return prep_emulate_rd12rm0(insn, asi);
1068 /* QADD : cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx :Q */
1069 /* QSUB : cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx :Q */
1070 /* QDADD : cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx :Q */
1071 /* QDSUB : cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx :Q */
1072 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1075 /* cccc 0000 xxxx xxxx xxxx xxxx xxxx 1001 xxxx */
1076 else if ((insn & 0x0f000090) == 0x00000090) {
1078 /* MUL : cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx : */
1079 /* MULS : cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx :cc */
1080 /* MLA : cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx : */
1081 /* MLAS : cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx :cc */
1082 /* UMAAL : cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx : */
1083 /* UMULL : cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx : */
1084 /* UMULLS : cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx :cc */
1085 /* UMLAL : cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx : */
1086 /* UMLALS : cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx :cc */
1087 /* SMULL : cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx : */
1088 /* SMULLS : cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx :cc */
1089 /* SMLAL : cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx : */
1090 /* SMLALS : cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx :cc */
1091 if ((insn & 0x0fe000f0) == 0x00000090) {
1092 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1093 } else if ((insn & 0x0fe000f0) == 0x00200090) {
1094 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1096 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1100 /* cccc 000x xxxx xxxx xxxx xxxx xxxx 1xx1 xxxx */
1101 else if ((insn & 0x0e000090) == 0x00000090) {
1103 /* SWP : cccc 0001 0000 xxxx xxxx xxxx 1001 xxxx */
1104 /* SWPB : cccc 0001 0100 xxxx xxxx xxxx 1001 xxxx */
1105 /* LDRD : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */
1106 /* STRD : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */
1107 /* STREX : cccc 0001 1000 xxxx xxxx xxxx 1001 xxxx */
1108 /* LDREX : cccc 0001 1001 xxxx xxxx xxxx 1001 xxxx */
1109 /* LDRH : cccc 000x xxx1 xxxx xxxx xxxx 1011 xxxx */
1110 /* STRH : cccc 000x xxx0 xxxx xxxx xxxx 1011 xxxx */
1111 /* LDRSB : cccc 000x xxx1 xxxx xxxx xxxx 1101 xxxx */
1112 /* LDRSH : cccc 000x xxx1 xxxx xxxx xxxx 1111 xxxx */
1113 if ((insn & 0x0fb000f0) == 0x01000090) {
1115 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1116 } else if ((insn & 0x0e1000d0) == 0x00000d0) {
1119 insn |= 0x00002000; /* Rn = r0, Rd = r2 */
1120 if (insn & (1 << 22)) {
1123 insn |= 1; /* Rm = r1 */
1125 asi->insn[0] = insn;
1127 (insn & (1 << 5)) ? emulate_strd : emulate_ldrd;
1131 return prep_emulate_ldr_str(insn, asi);
1134 /* cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx */
1137 * ALU op with S bit and Rd == 15 :
1138 * cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx
1140 if ((insn & 0x0e10f000) == 0x0010f000)
1141 return INSN_REJECTED;
1144 * "mov ip, sp" is the most common kprobe'd instruction by far.
1145 * Check and optimize for it explicitly.
1147 if (insn == 0xe1a0c00d) {
1148 asi->insn_handler = simulate_mov_ipsp;
1149 return INSN_GOOD_NO_SLOT;
1153 * Data processing: Immediate-shift / Register-shift
1154 * ALU op : cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx
1155 * CPY : cccc 0001 1010 xxxx xxxx 0000 0000 xxxx
1156 * MOV : cccc 0001 101x xxxx xxxx xxxx xxxx xxxx
1157 * *S (bit 20) updates condition codes
1158 * ADC/SBC/RSC reads the C flag
1160 insn &= 0xfff00ff0; /* Rn = r0, Rd = r0 */
1161 insn |= 0x00000001; /* Rm = r1 */
1163 insn &= 0xfffff0ff; /* register shift */
1164 insn |= 0x00000200; /* Rs = r2 */
1166 asi->insn[0] = insn;
1167 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1168 emulate_alu_rwflags : emulate_alu_rflags;
1172 static enum kprobe_insn __kprobes
1173 space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1176 * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
1177 * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
1178 * ALU op with S bit and Rd == 15 :
1179 * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
1181 if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */
1182 (insn & 0x0ff00000) == 0x03400000 || /* Undef */
1183 (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */
1184 return INSN_REJECTED;
1187 * Data processing: 32-bit Immediate
1188 * ALU op : cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
1189 * MOV : cccc 0011 101x xxxx xxxx xxxx xxxx xxxx
1190 * *S (bit 20) updates condition codes
1191 * ADC/SBC/RSC reads the C flag
1193 insn &= 0xffff0fff; /* Rd = r0 */
1194 asi->insn[0] = insn;
1195 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1196 emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
1200 static enum kprobe_insn __kprobes
1201 space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1203 /* SEL : cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx GE: !!! */
1204 if ((insn & 0x0ff000f0) == 0x068000b0) {
1205 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
1206 insn |= 0x00000001; /* Rm = r1 */
1207 asi->insn[0] = insn;
1208 asi->insn_handler = emulate_sel;
1212 /* SSAT : cccc 0110 101x xxxx xxxx xxxx xx01 xxxx :Q */
1213 /* USAT : cccc 0110 111x xxxx xxxx xxxx xx01 xxxx :Q */
1214 /* SSAT16 : cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx :Q */
1215 /* USAT16 : cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx :Q */
1216 if ((insn & 0x0fa00030) == 0x06a00010 ||
1217 (insn & 0x0fb000f0) == 0x06a00030) {
1218 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
1219 asi->insn[0] = insn;
1220 asi->insn_handler = emulate_sat;
1224 /* REV : cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
1225 /* REV16 : cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
1226 /* REVSH : cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
1227 if ((insn & 0x0ff00070) == 0x06b00030 ||
1228 (insn & 0x0ff000f0) == 0x06f000b0)
1229 return prep_emulate_rd12rm0(insn, asi);
1231 /* SADD16 : cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx :GE */
1232 /* SADDSUBX : cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx :GE */
1233 /* SSUBADDX : cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx :GE */
1234 /* SSUB16 : cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx :GE */
1235 /* SADD8 : cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx :GE */
1236 /* SSUB8 : cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx :GE */
1237 /* QADD16 : cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx : */
1238 /* QADDSUBX : cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx : */
1239 /* QSUBADDX : cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx : */
1240 /* QSUB16 : cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx : */
1241 /* QADD8 : cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx : */
1242 /* QSUB8 : cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx : */
1243 /* SHADD16 : cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx : */
1244 /* SHADDSUBX : cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx : */
1245 /* SHSUBADDX : cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx : */
1246 /* SHSUB16 : cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx : */
1247 /* SHADD8 : cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx : */
1248 /* SHSUB8 : cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx : */
1249 /* UADD16 : cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx :GE */
1250 /* UADDSUBX : cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx :GE */
1251 /* USUBADDX : cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx :GE */
1252 /* USUB16 : cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx :GE */
1253 /* UADD8 : cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx :GE */
1254 /* USUB8 : cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx :GE */
1255 /* UQADD16 : cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx : */
1256 /* UQADDSUBX : cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx : */
1257 /* UQSUBADDX : cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx : */
1258 /* UQSUB16 : cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx : */
1259 /* UQADD8 : cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx : */
1260 /* UQSUB8 : cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx : */
1261 /* UHADD16 : cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx : */
1262 /* UHADDSUBX : cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx : */
1263 /* UHSUBADDX : cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx : */
1264 /* UHSUB16 : cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx : */
1265 /* UHADD8 : cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx : */
1266 /* UHSUB8 : cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx : */
1267 /* PKHBT : cccc 0110 1000 xxxx xxxx xxxx x001 xxxx : */
1268 /* PKHTB : cccc 0110 1000 xxxx xxxx xxxx x101 xxxx : */
1269 /* SXTAB16 : cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx : */
1270 /* SXTB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */
1271 /* SXTAB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */
1272 /* SXTAH : cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx : */
1273 /* UXTAB16 : cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx : */
1274 /* UXTAB : cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx : */
1275 /* UXTAH : cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx : */
1276 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1279 static enum kprobe_insn __kprobes
1280 space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1282 /* Undef : cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
1283 if ((insn & 0x0ff000f0) == 0x03f000f0)
1284 return INSN_REJECTED;
1286 /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
1287 /* USAD8 : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
1288 if ((insn & 0x0ff000f0) == 0x07800010)
1289 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1291 /* SMLALD : cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
1292 /* SMLSLD : cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
1293 if ((insn & 0x0ff00090) == 0x07400010)
1294 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1296 /* SMLAD : cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx :Q */
1297 /* SMLSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx :Q */
1298 /* SMMLA : cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx : */
1299 /* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */
1300 if ((insn & 0x0ff00090) == 0x07000010 ||
1301 (insn & 0x0ff000d0) == 0x07500010 ||
1302 (insn & 0x0ff000d0) == 0x075000d0)
1303 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1305 /* SMUSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx : */
1306 /* SMUAD : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */
1307 /* SMMUL : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx : */
1308 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1311 static enum kprobe_insn __kprobes
1312 space_cccc_01xx(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1314 /* LDR : cccc 01xx x0x1 xxxx xxxx xxxx xxxx xxxx */
1315 /* LDRB : cccc 01xx x1x1 xxxx xxxx xxxx xxxx xxxx */
1316 /* LDRBT : cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
1317 /* LDRT : cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
1318 /* STR : cccc 01xx x0x0 xxxx xxxx xxxx xxxx xxxx */
1319 /* STRB : cccc 01xx x1x0 xxxx xxxx xxxx xxxx xxxx */
1320 /* STRBT : cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
1321 /* STRT : cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
1322 return prep_emulate_ldr_str(insn, asi);
1325 static enum kprobe_insn __kprobes
1326 space_cccc_100x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1328 /* LDM(2) : cccc 100x x101 xxxx 0xxx xxxx xxxx xxxx */
1329 /* LDM(3) : cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
1330 if ((insn & 0x0e708000) == 0x85000000 ||
1331 (insn & 0x0e508000) == 0x85010000)
1332 return INSN_REJECTED;
1334 /* LDM(1) : cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
1335 /* STM(1) : cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
1336 asi->insn[0] = truecc_insn(insn);
1337 asi->insn_handler = ((insn & 0x108000) == 0x008000) ? /* STM & R15 */
1338 simulate_stm1_pc : simulate_ldm1stm1;
1342 static enum kprobe_insn __kprobes
1343 space_cccc_101x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1345 /* B : cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
1346 /* BL : cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
1347 asi->insn[0] = truecc_insn(insn);
1348 asi->insn_handler = simulate_bbl;
1352 static enum kprobe_insn __kprobes
1353 space_cccc_1100_010x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1355 /* MCRR : cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1356 /* MRRC : cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1358 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
1359 asi->insn[0] = insn;
1360 asi->insn_handler = (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
1364 static enum kprobe_insn __kprobes
1365 space_cccc_110x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1367 /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
1368 /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
1369 insn &= 0xfff0ffff; /* Rn = r0 */
1370 asi->insn[0] = insn;
1371 asi->insn_handler = emulate_ldcstc;
1375 static enum kprobe_insn __kprobes
1376 space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1378 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1379 /* SWI : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
1380 if ((insn & 0xfff000f0) == 0xe1200070 ||
1381 (insn & 0x0f000000) == 0x0f000000)
1382 return INSN_REJECTED;
1384 /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
1385 if ((insn & 0x0f000010) == 0x0e000000) {
1386 asi->insn[0] = insn;
1387 asi->insn_handler = emulate_none;
1391 /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1392 /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
1393 insn &= 0xffff0fff; /* Rd = r0 */
1394 asi->insn[0] = insn;
1395 asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
1400 * INSN_REJECTED If instruction is one not allowed to kprobe,
1401 * INSN_GOOD If instruction is supported and uses instruction slot,
1402 * INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
1404 * For instructions we don't want to kprobe (INSN_REJECTED return result):
1405 * These are generally ones that modify the processor state making
1406 * them "hard" to simulate such as switches processor modes or
1407 * make accesses in alternate modes. Any of these could be simulated
1408 * if the work was put into it, but low return considering they
1409 * should also be very rare.
1411 enum kprobe_insn __kprobes
1412 arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1414 asi->insn[1] = KPROBE_RETURN_INSTRUCTION;
1416 if ((insn & 0xf0000000) == 0xf0000000) {
1418 return space_1111(insn, asi);
1420 } else if ((insn & 0x0e000000) == 0x00000000) {
1422 return space_cccc_000x(insn, asi);
1424 } else if ((insn & 0x0e000000) == 0x02000000) {
1426 return space_cccc_001x(insn, asi);
1428 } else if ((insn & 0x0f000010) == 0x06000010) {
1430 return space_cccc_0110__1(insn, asi);
1432 } else if ((insn & 0x0f000010) == 0x07000010) {
1434 return space_cccc_0111__1(insn, asi);
1436 } else if ((insn & 0x0c000000) == 0x04000000) {
1438 return space_cccc_01xx(insn, asi);
1440 } else if ((insn & 0x0e000000) == 0x08000000) {
1442 return space_cccc_100x(insn, asi);
1444 } else if ((insn & 0x0e000000) == 0x0a000000) {
1446 return space_cccc_101x(insn, asi);
1448 } else if ((insn & 0x0fe00000) == 0x0c400000) {
1450 return space_cccc_1100_010x(insn, asi);
1452 } else if ((insn & 0x0e000000) == 0x0c000000) {
1454 return space_cccc_110x(insn, asi);
1458 return space_cccc_111x(insn, asi);
1461 void __init arm_kprobe_decode_init(void)
1463 find_str_pc_offset();
1468 * All ARM instructions listed below.
1470 * Instructions and their general purpose registers are given.
1471 * If a particular register may not use R15, it is prefixed with a "!".
1472 * If marked with a "*" means the value returned by reading R15
1473 * is implementation defined.
1475 * ADC/ADD/AND/BIC/CMN/CMP/EOR/MOV/MVN/ORR/RSB/RSC/SBC/SUB/TEQ
1476 * TST: Rd, Rn, Rm, !Rs
1479 * BX: Rm (R15 legal, but discouraged)
1483 * LDC/2,STC/2 immediate offset & unindex: Rn
1484 * LDC/2,STC/2 immediate pre/post-indexed: !Rn
1485 * LDM(1/3): !Rn, register_list
1486 * LDM(2): !Rn, !register_list
1487 * LDR,STR,PLD immediate offset: Rd, Rn
1488 * LDR,STR,PLD register offset: Rd, Rn, !Rm
1489 * LDR,STR,PLD scaled register offset: Rd, !Rn, !Rm
1490 * LDR,STR immediate pre/post-indexed: Rd, !Rn
1491 * LDR,STR register pre/post-indexed: Rd, !Rn, !Rm
1492 * LDR,STR scaled register pre/post-indexed: Rd, !Rn, !Rm
1493 * LDRB,STRB immediate offset: !Rd, Rn
1494 * LDRB,STRB register offset: !Rd, Rn, !Rm
1495 * LDRB,STRB scaled register offset: !Rd, !Rn, !Rm
1496 * LDRB,STRB immediate pre/post-indexed: !Rd, !Rn
1497 * LDRB,STRB register pre/post-indexed: !Rd, !Rn, !Rm
1498 * LDRB,STRB scaled register pre/post-indexed: !Rd, !Rn, !Rm
1499 * LDRT,LDRBT,STRBT immediate pre/post-indexed: !Rd, !Rn
1500 * LDRT,LDRBT,STRBT register pre/post-indexed: !Rd, !Rn, !Rm
1501 * LDRT,LDRBT,STRBT scaled register pre/post-indexed: !Rd, !Rn, !Rm
1502 * LDRH/SH/SB/D,STRH/SH/SB/D immediate offset: !Rd, Rn
1503 * LDRH/SH/SB/D,STRH/SH/SB/D register offset: !Rd, Rn, !Rm
1504 * LDRH/SH/SB/D,STRH/SH/SB/D immediate pre/post-indexed: !Rd, !Rn
1505 * LDRH/SH/SB/D,STRH/SH/SB/D register pre/post-indexed: !Rd, !Rn, !Rm
1508 * MCRR/2,MRRC/2: !Rd, !Rn
1509 * MLA: !Rd, !Rn, !Rm, !Rs
1511 * MRC/2: !Rd (if Rd==15, only changes cond codes, not the register)
1513 * MUL: !Rd, !Rm, !Rs
1514 * PKH{BT,TB}: !Rd, !Rn, !Rm
1515 * QDADD,[U]QADD/16/8/SUBX: !Rd, !Rm, !Rn
1516 * QDSUB,[U]QSUB/16/8/ADDX: !Rd, !Rm, !Rn
1517 * REV/16/SH: !Rd, !Rm
1519 * {S,U}[H]ADD{16,8,SUBX},{S,U}[H]SUB{16,8,ADDX}: !Rd, !Rn, !Rm
1520 * SEL: !Rd, !Rn, !Rm
1521 * SMLA<x><y>,SMLA{D,W<y>},SMLSD,SMML{A,S}: !Rd, !Rn, !Rm, !Rs
1522 * SMLAL<x><y>,SMLA{D,LD},SMLSLD,SMMULL,SMULW<y>: !RdHi, !RdLo, !Rm, !Rs
1523 * SMMUL,SMUAD,SMUL<x><y>,SMUSD: !Rd, !Rm, !Rs
1525 * STM(1/2): !Rn, register_list* (R15 in reg list not recommended)
1526 * STRT immediate pre/post-indexed: Rd*, !Rn
1527 * STRT register pre/post-indexed: Rd*, !Rn, !Rm
1528 * STRT scaled register pre/post-indexed: Rd*, !Rn, !Rm
1529 * STREX: !Rd, !Rn, !Rm
1530 * SWP/B: !Rd, !Rn, !Rm
1531 * {S,U}XTA{B,B16,H}: !Rd, !Rn, !Rm
1532 * {S,U}XT{B,B16,H}: !Rd, !Rm
1533 * UM{AA,LA,UL}L: !RdHi, !RdLo, !Rm, !Rs
1534 * USA{D8,A8,T,T16}: !Rd, !Rm, !Rs
1536 * May transfer control by writing R15 (possible mode changes or alternate
1537 * mode accesses marked by "*"):
1538 * ALU op (* with s-bit), B, BL, BKPT, BLX(1/2), BX, BXJ, CPS*, CPY,
1539 * LDM(1), LDM(2/3)*, LDR, MOV, RFE*, SWI*
1541 * Instructions that do not take general registers, nor transfer control:
1542 * CDP/2, SETEND, SRS*