2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/assembler.h>
19 #include <asm/memory.h>
20 #include <asm/glue-df.h>
21 #include <asm/glue-pf.h>
22 #include <asm/vfpmacros.h>
23 #ifndef CONFIG_MULTI_IRQ_HANDLER
24 #include <mach/entry-macro.S>
26 #include <asm/thread_notify.h>
27 #include <asm/unwind.h>
28 #include <asm/unistd.h>
30 #include <asm/system_info.h>
32 #include "entry-header.S"
33 #include <asm/entry-macro-multi.S>
39 #ifdef CONFIG_MULTI_IRQ_HANDLER
40 ldr r1, =handle_arch_irq
45 arch_irq_handler_default
51 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
55 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
64 @ Call the processor-specific abort handler:
67 @ r4 - aborted context pc
68 @ r5 - aborted context psr
70 @ The abort handler must return the aborted address in r0, and
71 @ the fault status register in r1. r9 must be preserved.
76 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
83 .section .kprobes.text,"ax",%progbits
89 * Invalid mode handlers
91 .macro inv_entry, reason
92 sub sp, sp, #S_FRAME_SIZE
93 ARM( stmib sp, {r1 - lr} )
94 THUMB( stmia sp, {r0 - r12} )
95 THUMB( str sp, [sp, #S_SP] )
96 THUMB( str lr, [sp, #S_LR] )
101 inv_entry BAD_PREFETCH
103 ENDPROC(__pabt_invalid)
108 ENDPROC(__dabt_invalid)
113 ENDPROC(__irq_invalid)
116 inv_entry BAD_UNDEFINSTR
119 @ XXX fall through to common_invalid
123 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
129 add r0, sp, #S_PC @ here for interlock avoidance
130 mov r7, #-1 @ "" "" "" ""
131 str r4, [sp] @ save preserved r0
132 stmia r0, {r5 - r7} @ lr_<exception>,
133 @ cpsr_<exception>, "old_r0"
137 ENDPROC(__und_invalid)
143 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
144 #define SPFIX(code...) code
146 #define SPFIX(code...)
149 .macro svc_entry, stack_hole=0
151 UNWIND(.save {r0 - pc} )
152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
153 #ifdef CONFIG_THUMB2_KERNEL
154 SPFIX( str r0, [sp] ) @ temporarily saved
156 SPFIX( tst r0, #4 ) @ test original stack alignment
157 SPFIX( ldr r0, [sp] ) @ restored
161 SPFIX( subeq sp, sp, #4 )
165 add r7, sp, #S_SP - 4 @ here for interlock avoidance
166 mov r6, #-1 @ "" "" "" ""
167 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
168 SPFIX( addeq r2, r2, #4 )
169 str r3, [sp, #-4]! @ save the "real" r0 copied
170 @ from the exception stack
175 @ We are now ready to fill in the remaining blanks on the stack:
179 @ r4 - lr_<exception>, already fixed up for correct return/restart
180 @ r5 - spsr_<exception>
181 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
185 #ifdef CONFIG_TRACE_IRQFLAGS
186 bl trace_hardirqs_off
197 @ IRQs off again before pulling preserved data off the stack
201 #ifdef CONFIG_TRACE_IRQFLAGS
203 bleq trace_hardirqs_on
205 blne trace_hardirqs_off
207 svc_exit r5 @ return from exception
216 #ifdef CONFIG_PREEMPT
218 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
219 ldr r0, [tsk, #TI_FLAGS] @ get flags
220 teq r8, #0 @ if preempt count != 0
221 movne r0, #0 @ force flags to 0
222 tst r0, #_TIF_NEED_RESCHED
226 #ifdef CONFIG_TRACE_IRQFLAGS
227 @ The parent context IRQs must have been enabled to get here in
228 @ the first place, so there's no point checking the PSR I bit.
231 svc_exit r5 @ return from exception
237 #ifdef CONFIG_PREEMPT
240 1: bl preempt_schedule_irq @ irq en/disable is done inside
241 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
242 tst r0, #_TIF_NEED_RESCHED
243 moveq pc, r8 @ go again
249 #ifdef CONFIG_KPROBES
250 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
251 @ it obviously needs free stack space which then will belong to
258 @ call emulation code, which returns using r9 if it has emulated
259 @ the instruction, or the more conventional lr if we are to treat
260 @ this as a real undefined instruction
264 #ifndef CONFIG_THUMB2_KERNEL
267 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
268 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
269 ldrhhs r9, [r4] @ bottom 16 bits
270 orrhs r0, r9, r0, lsl #16
276 mov r0, sp @ struct pt_regs *regs
280 @ IRQs off again before pulling preserved data off the stack
282 1: disable_irq_notrace
285 @ restore SPSR and restart the instruction
287 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
288 #ifdef CONFIG_TRACE_IRQFLAGS
290 bleq trace_hardirqs_on
292 blne trace_hardirqs_off
294 svc_exit r5 @ return from exception
305 @ IRQs off again before pulling preserved data off the stack
309 #ifdef CONFIG_TRACE_IRQFLAGS
311 bleq trace_hardirqs_on
313 blne trace_hardirqs_off
315 svc_exit r5 @ return from exception
332 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
335 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
336 #error "sizeof(struct pt_regs) must be a multiple of 8"
341 UNWIND(.cantunwind ) @ don't unwind the user space
342 sub sp, sp, #S_FRAME_SIZE
343 ARM( stmib sp, {r1 - r12} )
344 THUMB( stmia sp, {r0 - r12} )
347 add r0, sp, #S_PC @ here for interlock avoidance
348 mov r6, #-1 @ "" "" "" ""
350 str r3, [sp] @ save the "real" r0 copied
351 @ from the exception stack
354 @ We are now ready to fill in the remaining blanks on the stack:
356 @ r4 - lr_<exception>, already fixed up for correct return/restart
357 @ r5 - spsr_<exception>
358 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
360 @ Also, separately save sp_usr and lr_usr
363 ARM( stmdb r0, {sp, lr}^ )
364 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
367 @ Enable the alignment trap while in kernel mode
372 @ Clear FP to mark the first stack frame
376 #ifdef CONFIG_IRQSOFF_TRACER
377 bl trace_hardirqs_off
381 .macro kuser_cmpxchg_check
382 #if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
384 #warning "NPTL on non MMU needs fixing"
386 @ Make sure our user space atomic helper is restarted
387 @ if it was interrupted in a critical region. Here we
388 @ perform a quick test inline since it should be false
389 @ 99.9999% of the time. The rest is done out of line.
391 blhs kuser_cmpxchg64_fixup
413 b ret_to_user_from_irq
427 @ fall through to the emulation code, which returns using r9 if
428 @ it has emulated the instruction, or the more conventional lr
429 @ if we are to treat this as a real undefined instruction
433 adr r9, BSYM(ret_from_exception)
434 adr lr, BSYM(__und_usr_unknown)
435 tst r3, #PSR_T_BIT @ Thumb mode?
436 itet eq @ explicit IT needed for the 1f label
437 subeq r4, r2, #4 @ ARM instr at LR - 4
438 subne r4, r2, #2 @ Thumb instr at LR - 2
440 #ifdef CONFIG_CPU_ENDIAN_BE8
441 reveq r0, r0 @ little endian instruction
445 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
447 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
448 * can never be supported in a single kernel, this code is not applicable at
449 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
450 * made about .arch directives.
452 #if __LINUX_ARM_ARCH__ < 7
453 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
454 #define NEED_CPU_ARCHITECTURE
455 ldr r5, .LCcpu_architecture
457 cmp r5, #CPU_ARCH_ARMv7
458 blo __und_usr_unknown
460 * The following code won't get run unless the running CPU really is v7, so
461 * coding round the lack of ldrht on older arches is pointless. Temporarily
462 * override the assembler target arch with the minimum required instead:
467 ARM( ldrht r5, [r4], #2 )
468 THUMB( ldrht r5, [r4] )
469 THUMB( add r4, r4, #2 )
470 cmp r5, #0xe800 @ 32bit instruction if xx != 0
471 blo __und_usr_unknown
473 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
474 orr r0, r0, r5, lsl #16
476 #if __LINUX_ARM_ARCH__ < 7
477 /* If the target arch was overridden, change it back: */
478 #ifdef CONFIG_CPU_32v6K
483 #endif /* __LINUX_ARM_ARCH__ < 7 */
484 #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
491 @ fallthrough to call_fpe
495 * The out of line fixup for the ldrt above.
497 .pushsection .fixup, "ax"
500 .pushsection __ex_table,"a"
502 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
509 * Check whether the instruction is a co-processor instruction.
510 * If yes, we need to call the relevant co-processor handler.
512 * Note that we don't do a full check here for the co-processor
513 * instructions; all instructions with bit 27 set are well
514 * defined. The only instructions that should fault are the
515 * co-processor instructions. However, we have to watch out
516 * for the ARM6/ARM7 SWI bug.
518 * NEON is a special case that has to be handled here. Not all
519 * NEON instructions are co-processor instructions, so we have
520 * to make a special case of checking for them. Plus, there's
521 * five groups of them, so we have a table of mask/opcode pairs
522 * to check against, and if any match then we branch off into the
525 * Emulators may wish to make use of the following registers:
526 * r0 = instruction opcode.
528 * r9 = normal "successful" return address
529 * r10 = this threads thread_info structure.
530 * lr = unrecognised instruction return address
533 @ Fall-through from Thumb-2 __und_usr
536 adr r6, .LCneon_thumb_opcodes
541 adr r6, .LCneon_arm_opcodes
543 ldr r7, [r6], #4 @ mask value
544 cmp r7, #0 @ end mask?
547 ldr r7, [r6], #4 @ opcode bits matching in mask
548 cmp r8, r7 @ NEON instruction?
552 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
553 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
554 b do_vfp @ let VFP handler handle this
557 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
558 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
559 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
560 and r8, r0, #0x0f000000 @ mask out op-code bits
561 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
564 get_thread_info r10 @ get current thread
565 and r8, r0, #0x00000f00 @ mask out CP number
566 THUMB( lsr r8, r8, #8 )
568 add r6, r10, #TI_USED_CP
569 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
570 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
572 @ Test if we need to give access to iWMMXt coprocessors
573 ldr r5, [r10, #TI_FLAGS]
574 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
575 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
576 bcs iwmmxt_task_enable
578 ARM( add pc, pc, r8, lsr #6 )
579 THUMB( lsl r8, r8, #2 )
584 W(b) do_fpe @ CP#1 (FPE)
585 W(b) do_fpe @ CP#2 (FPE)
588 b crunch_task_enable @ CP#4 (MaverickCrunch)
589 b crunch_task_enable @ CP#5 (MaverickCrunch)
590 b crunch_task_enable @ CP#6 (MaverickCrunch)
600 W(b) do_vfp @ CP#10 (VFP)
601 W(b) do_vfp @ CP#11 (VFP)
603 movw_pc lr @ CP#10 (VFP)
604 movw_pc lr @ CP#11 (VFP)
608 movw_pc lr @ CP#14 (Debug)
609 movw_pc lr @ CP#15 (Control)
611 #ifdef NEED_CPU_ARCHITECTURE
614 .word __cpu_architecture
621 .word 0xfe000000 @ mask
622 .word 0xf2000000 @ opcode
624 .word 0xff100000 @ mask
625 .word 0xf4000000 @ opcode
627 .word 0x00000000 @ mask
628 .word 0x00000000 @ opcode
630 .LCneon_thumb_opcodes:
631 .word 0xef000000 @ mask
632 .word 0xef000000 @ opcode
634 .word 0xff100000 @ mask
635 .word 0xf9000000 @ opcode
637 .word 0x00000000 @ mask
638 .word 0x00000000 @ opcode
644 add r10, r10, #TI_FPSTATE @ r10 = workspace
645 ldr pc, [r4] @ Call FP module USR entry point
648 * The FP module is called with these registers set:
651 * r9 = normal "successful" return address
653 * lr = unrecognised FP instruction return address
668 adr lr, BSYM(ret_from_exception)
670 ENDPROC(__und_usr_unknown)
680 * This is the return code to user mode for abort handlers
682 ENTRY(ret_from_exception)
690 ENDPROC(ret_from_exception)
693 * Register switch for ARMv3 and ARMv4 processors
694 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
695 * previous and next are guaranteed not to be the same.
700 add ip, r1, #TI_CPU_SAVE
701 ldr r3, [r2, #TI_TP_VALUE]
702 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
703 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
704 THUMB( str sp, [ip], #4 )
705 THUMB( str lr, [ip], #4 )
706 #ifdef CONFIG_CPU_USE_DOMAINS
707 ldr r6, [r2, #TI_CPU_DOMAIN]
710 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
711 ldr r7, [r2, #TI_TASK]
712 ldr r8, =__stack_chk_guard
713 ldr r7, [r7, #TSK_STACK_CANARY]
715 #ifdef CONFIG_CPU_USE_DOMAINS
716 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
719 add r4, r2, #TI_CPU_SAVE
720 ldr r0, =thread_notify_head
721 mov r1, #THREAD_NOTIFY_SWITCH
722 bl atomic_notifier_call_chain
723 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
728 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
729 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
730 THUMB( ldr sp, [ip], #4 )
731 THUMB( ldr pc, [ip] )
740 * Each segment is 32-byte aligned and will be moved to the top of the high
741 * vector page. New segments (if ever needed) must be added in front of
742 * existing ones. This mechanism should be used only for things that are
743 * really small and justified, and not be abused freely.
745 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
750 #ifdef CONFIG_ARM_THUMB
758 .globl __kuser_helper_start
759 __kuser_helper_start:
762 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
763 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
766 __kuser_cmpxchg64: @ 0xffff0f60
768 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
771 * Poor you. No fast solution possible...
772 * The kernel itself must perform the operation.
773 * A special ghost syscall is used for that (see traps.c).
776 ldr r7, 1f @ it's 20 bits
777 swi __ARM_NR_cmpxchg64
779 1: .word __ARM_NR_cmpxchg64
781 #elif defined(CONFIG_CPU_32v6K)
783 stmfd sp!, {r4, r5, r6, r7}
784 ldrd r4, r5, [r0] @ load old val
785 ldrd r6, r7, [r1] @ load new val
787 1: ldrexd r0, r1, [r2] @ load current val
788 eors r3, r0, r4 @ compare with oldval (1)
789 eoreqs r3, r1, r5 @ compare with oldval (2)
790 strexdeq r3, r6, r7, [r2] @ store newval if eq
791 teqeq r3, #1 @ success?
792 beq 1b @ if no then retry
794 rsbs r0, r3, #0 @ set returned val and C flag
795 ldmfd sp!, {r4, r5, r6, r7}
798 #elif !defined(CONFIG_SMP)
803 * The only thing that can break atomicity in this cmpxchg64
804 * implementation is either an IRQ or a data abort exception
805 * causing another process/thread to be scheduled in the middle of
806 * the critical sequence. The same strategy as for cmpxchg is used.
808 stmfd sp!, {r4, r5, r6, lr}
809 ldmia r0, {r4, r5} @ load old val
810 ldmia r1, {r6, lr} @ load new val
811 1: ldmia r2, {r0, r1} @ load current val
812 eors r3, r0, r4 @ compare with oldval (1)
813 eoreqs r3, r1, r5 @ compare with oldval (2)
814 2: stmeqia r2, {r6, lr} @ store newval if eq
815 rsbs r0, r3, #0 @ set return val and C flag
816 ldmfd sp!, {r4, r5, r6, pc}
819 kuser_cmpxchg64_fixup:
820 @ Called from kuser_cmpxchg_fixup.
821 @ r4 = address of interrupted insn (must be preserved).
822 @ sp = saved regs. r7 and r8 are clobbered.
823 @ 1b = first critical insn, 2b = last critical insn.
824 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
826 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
828 rsbcss r8, r8, #(2b - 1b)
829 strcs r7, [sp, #S_PC]
830 #if __LINUX_ARM_ARCH__ < 6
831 bcc kuser_cmpxchg32_fixup
837 #warning "NPTL on non MMU needs fixing"
844 #error "incoherent kernel configuration"
847 /* pad to next slot */
848 .rept (16 - (. - __kuser_cmpxchg64)/4)
854 __kuser_memory_barrier: @ 0xffff0fa0
860 __kuser_cmpxchg: @ 0xffff0fc0
862 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
865 * Poor you. No fast solution possible...
866 * The kernel itself must perform the operation.
867 * A special ghost syscall is used for that (see traps.c).
870 ldr r7, 1f @ it's 20 bits
873 1: .word __ARM_NR_cmpxchg
875 #elif __LINUX_ARM_ARCH__ < 6
880 * The only thing that can break atomicity in this cmpxchg
881 * implementation is either an IRQ or a data abort exception
882 * causing another process/thread to be scheduled in the middle
883 * of the critical sequence. To prevent this, code is added to
884 * the IRQ and data abort exception handlers to set the pc back
885 * to the beginning of the critical section if it is found to be
886 * within that critical section (see kuser_cmpxchg_fixup).
888 1: ldr r3, [r2] @ load current val
889 subs r3, r3, r0 @ compare with oldval
890 2: streq r1, [r2] @ store newval if eq
891 rsbs r0, r3, #0 @ set return val and C flag
895 kuser_cmpxchg32_fixup:
896 @ Called from kuser_cmpxchg_check macro.
897 @ r4 = address of interrupted insn (must be preserved).
898 @ sp = saved regs. r7 and r8 are clobbered.
899 @ 1b = first critical insn, 2b = last critical insn.
900 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
902 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
904 rsbcss r8, r8, #(2b - 1b)
905 strcs r7, [sp, #S_PC]
910 #warning "NPTL on non MMU needs fixing"
925 /* beware -- each __kuser slot must be 8 instructions max */
926 ALT_SMP(b __kuser_memory_barrier)
933 __kuser_get_tls: @ 0xffff0fe0
934 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
936 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
938 .word 0 @ 0xffff0ff0 software TLS value, then
939 .endr @ pad up to __kuser_helper_version
941 __kuser_helper_version: @ 0xffff0ffc
942 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
944 .globl __kuser_helper_end
952 * This code is copied to 0xffff0200 so we can use branches in the
953 * vectors, rather than ldr's. Note that this code must not
954 * exceed 0x300 bytes.
956 * Common stub entry macro:
957 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
959 * SP points to a minimal amount of processor-private memory, the address
960 * of which is copied into r0 for the mode specific abort handler.
962 .macro vector_stub, name, mode, correction=0
967 sub lr, lr, #\correction
971 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
974 stmia sp, {r0, lr} @ save r0, lr
976 str lr, [sp, #8] @ save spsr
979 @ Prepare for SVC32 mode. IRQs remain disabled.
982 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
986 @ the branch table must immediately follow this code
990 THUMB( ldr lr, [r0, lr, lsl #2] )
992 ARM( ldr lr, [pc, lr, lsl #2] )
993 movs pc, lr @ branch to handler in SVC mode
994 ENDPROC(vector_\name)
997 @ handler addresses follow this label
1001 .globl __stubs_start
1004 * Interrupt dispatcher
1006 vector_stub irq, IRQ_MODE, 4
1008 .long __irq_usr @ 0 (USR_26 / USR_32)
1009 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1010 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1011 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1012 .long __irq_invalid @ 4
1013 .long __irq_invalid @ 5
1014 .long __irq_invalid @ 6
1015 .long __irq_invalid @ 7
1016 .long __irq_invalid @ 8
1017 .long __irq_invalid @ 9
1018 .long __irq_invalid @ a
1019 .long __irq_invalid @ b
1020 .long __irq_invalid @ c
1021 .long __irq_invalid @ d
1022 .long __irq_invalid @ e
1023 .long __irq_invalid @ f
1026 * Data abort dispatcher
1027 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1029 vector_stub dabt, ABT_MODE, 8
1031 .long __dabt_usr @ 0 (USR_26 / USR_32)
1032 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1033 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1034 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1035 .long __dabt_invalid @ 4
1036 .long __dabt_invalid @ 5
1037 .long __dabt_invalid @ 6
1038 .long __dabt_invalid @ 7
1039 .long __dabt_invalid @ 8
1040 .long __dabt_invalid @ 9
1041 .long __dabt_invalid @ a
1042 .long __dabt_invalid @ b
1043 .long __dabt_invalid @ c
1044 .long __dabt_invalid @ d
1045 .long __dabt_invalid @ e
1046 .long __dabt_invalid @ f
1049 * Prefetch abort dispatcher
1050 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1052 vector_stub pabt, ABT_MODE, 4
1054 .long __pabt_usr @ 0 (USR_26 / USR_32)
1055 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1056 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1057 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1058 .long __pabt_invalid @ 4
1059 .long __pabt_invalid @ 5
1060 .long __pabt_invalid @ 6
1061 .long __pabt_invalid @ 7
1062 .long __pabt_invalid @ 8
1063 .long __pabt_invalid @ 9
1064 .long __pabt_invalid @ a
1065 .long __pabt_invalid @ b
1066 .long __pabt_invalid @ c
1067 .long __pabt_invalid @ d
1068 .long __pabt_invalid @ e
1069 .long __pabt_invalid @ f
1072 * Undef instr entry dispatcher
1073 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1075 vector_stub und, UND_MODE
1077 .long __und_usr @ 0 (USR_26 / USR_32)
1078 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1079 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1080 .long __und_svc @ 3 (SVC_26 / SVC_32)
1081 .long __und_invalid @ 4
1082 .long __und_invalid @ 5
1083 .long __und_invalid @ 6
1084 .long __und_invalid @ 7
1085 .long __und_invalid @ 8
1086 .long __und_invalid @ 9
1087 .long __und_invalid @ a
1088 .long __und_invalid @ b
1089 .long __und_invalid @ c
1090 .long __und_invalid @ d
1091 .long __und_invalid @ e
1092 .long __und_invalid @ f
1096 /*=============================================================================
1098 *-----------------------------------------------------------------------------
1099 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1100 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1101 * Basically to switch modes, we *HAVE* to clobber one register... brain
1102 * damage alert! I don't think that we can execute any code in here in any
1103 * other mode than FIQ... Ok you can switch to another mode, but you can't
1104 * get out of that mode without clobbering one register.
1109 /*=============================================================================
1110 * Address exception handler
1111 *-----------------------------------------------------------------------------
1112 * These aren't too critical.
1113 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1120 * We group all the following data together to optimise
1121 * for CPUs with separate I & D caches.
1131 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1133 .globl __vectors_start
1135 ARM( swi SYS_ERROR0 )
1138 W(b) vector_und + stubs_offset
1139 W(ldr) pc, .LCvswi + stubs_offset
1140 W(b) vector_pabt + stubs_offset
1141 W(b) vector_dabt + stubs_offset
1142 W(b) vector_addrexcptn + stubs_offset
1143 W(b) vector_irq + stubs_offset
1144 W(b) vector_fiq + stubs_offset
1146 .globl __vectors_end
1152 .globl cr_no_alignment
1158 #ifdef CONFIG_MULTI_IRQ_HANDLER
1159 .globl handle_arch_irq