2 * arch/arm/include/asm/io.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
12 * constant addresses and variable addresses.
13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
14 * specific IO header files.
15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
16 * 04-Apr-1999 PJB Added check_signature.
17 * 12-Dec-1999 RMK More cleanups
18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
21 #ifndef __ASM_ARM_IO_H
22 #define __ASM_ARM_IO_H
26 #include <linux/types.h>
27 #include <linux/blk_types.h>
28 #include <asm/byteorder.h>
29 #include <asm/memory.h>
30 #include <asm-generic/pci_iomap.h>
34 * ISA I/O bus memory addresses are 1:1 with the physical address.
36 #define isa_virt_to_bus virt_to_phys
37 #define isa_page_to_bus page_to_phys
38 #define isa_bus_to_virt phys_to_virt
41 * Atomic MMIO-wide IO modify
43 extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
44 extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
47 * Generic IO read/write. These perform native-endian accesses. Note
48 * that some architectures will want to re-define __raw_{read,write}w.
50 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
51 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
52 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
54 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
55 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
56 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
58 #if __LINUX_ARM_ARCH__ < 6
60 * Half-word accesses are problematic with RiscPC due to limitations of
61 * the bus. Rather than special-case the machine, just let the compiler
62 * generate the access for CPUs prior to ARMv6.
64 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
65 #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
68 * When running under a hypervisor, we want to avoid I/O accesses with
69 * writeback addressing modes as these incur a significant performance
70 * overhead (the address generation must be emulated in software).
72 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
74 asm volatile("strh %1, %0"
75 : "+Q" (*(volatile u16 __force *)addr)
79 static inline u16 __raw_readw(const volatile void __iomem *addr)
82 asm volatile("ldrh %1, %0"
83 : "+Q" (*(volatile u16 __force *)addr),
89 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
91 asm volatile("strb %1, %0"
92 : "+Qo" (*(volatile u8 __force *)addr)
96 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
98 asm volatile("str %1, %0"
99 : "+Qo" (*(volatile u32 __force *)addr)
103 static inline u8 __raw_readb(const volatile void __iomem *addr)
106 asm volatile("ldrb %1, %0"
107 : "+Qo" (*(volatile u8 __force *)addr),
112 static inline u32 __raw_readl(const volatile void __iomem *addr)
115 asm volatile("ldr %1, %0"
116 : "+Qo" (*(volatile u32 __force *)addr),
122 * Architecture ioremap implementation.
125 #define MT_DEVICE_NONSHARED 1
126 #define MT_DEVICE_CACHED 2
127 #define MT_DEVICE_WC 3
129 * types 4 onwards can be found in asm/mach/map.h and are undefined
134 * __arm_ioremap takes CPU physical address.
135 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
136 * The _caller variety takes a __builtin_return_address(0) value for
137 * /proc/vmalloc to use - and should only be used in non-inline functions.
139 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
140 size_t, unsigned int, void *);
141 extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
144 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
145 extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int);
146 extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
147 extern void __iounmap(volatile void __iomem *addr);
148 extern void __arm_iounmap(volatile void __iomem *addr);
150 extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
151 unsigned int, void *);
152 extern void (*arch_iounmap)(volatile void __iomem *);
155 * Bad read/write accesses...
157 extern void __readwrite_bug(const char *fn);
160 * A typesafe __io() helper
162 static inline void __iomem *__typesafe_io(unsigned long addr)
164 return (void __iomem *)addr;
167 #define IOMEM(x) ((void __force __iomem *)(x))
170 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
171 #include <asm/barrier.h>
172 #define __iormb() rmb()
173 #define __iowmb() wmb()
175 #define __iormb() do { } while (0)
176 #define __iowmb() do { } while (0)
179 /* PCI fixed i/o mapping */
180 #define PCI_IO_VIRT_BASE 0xfee00000
182 extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
185 * Now, pick up the machine-defined IO definitions
187 #ifdef CONFIG_NEED_MACH_IO_H
189 #elif defined(CONFIG_PCI)
190 #define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
191 #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
193 #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
197 * This is the limit of PC card/PCI/ISA IO space, which is by default
198 * 64K if we have PC card, PCI or ISA support. Otherwise, default to
199 * zero to prevent ISA/PCI drivers claiming IO space (and potentially
202 * Only set this larger if you really need inb() et.al. to operate over
203 * a larger address space. Note that SOC_COMMON ioremaps each sockets
204 * IO space area, and so inb() et.al. must be defined to operate as per
205 * readb() et.al. on such platforms.
207 #ifndef IO_SPACE_LIMIT
208 #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
209 #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
210 #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
211 #define IO_SPACE_LIMIT ((resource_size_t)0xffff)
213 #define IO_SPACE_LIMIT ((resource_size_t)0)
218 * IO port access primitives
219 * -------------------------
221 * The ARM doesn't have special IO access instructions; all IO is memory
222 * mapped. Note that these are defined to perform little endian accesses
223 * only. Their primary purpose is to access PCI and ISA peripherals.
225 * Note that for a big endian machine, this implies that the following
226 * big endian mode connectivity is in place, as described by numerous
229 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
230 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
232 * The machine specific io.h include defines __io to translate an "IO"
233 * address to a memory address.
235 * Note that we prevent GCC re-ordering or caching values in expressions
236 * by introducing sequence points into the in*() definitions. Note that
237 * __raw_* do not guarantee this behaviour.
239 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
242 #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
243 #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
244 cpu_to_le16(v),__io(p)); })
245 #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
246 cpu_to_le32(v),__io(p)); })
248 #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
249 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
250 __raw_readw(__io(p))); __iormb(); __v; })
251 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
252 __raw_readl(__io(p))); __iormb(); __v; })
254 #define outsb(p,d,l) __raw_writesb(__io(p),d,l)
255 #define outsw(p,d,l) __raw_writesw(__io(p),d,l)
256 #define outsl(p,d,l) __raw_writesl(__io(p),d,l)
258 #define insb(p,d,l) __raw_readsb(__io(p),d,l)
259 #define insw(p,d,l) __raw_readsw(__io(p),d,l)
260 #define insl(p,d,l) __raw_readsl(__io(p),d,l)
263 #define outb_p(val,port) outb((val),(port))
264 #define outw_p(val,port) outw((val),(port))
265 #define outl_p(val,port) outl((val),(port))
266 #define inb_p(port) inb((port))
267 #define inw_p(port) inw((port))
268 #define inl_p(port) inl((port))
270 #define outsb_p(port,from,len) outsb(port,from,len)
271 #define outsw_p(port,from,len) outsw(port,from,len)
272 #define outsl_p(port,from,len) outsl(port,from,len)
273 #define insb_p(port,to,len) insb(port,to,len)
274 #define insw_p(port,to,len) insw(port,to,len)
275 #define insl_p(port,to,len) insl(port,to,len)
278 * String version of IO memory access ops:
280 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
281 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
282 extern void _memset_io(volatile void __iomem *, int, size_t);
287 * Memory access primitives
288 * ------------------------
290 * These perform PCI memory accesses via an ioremap region. They don't
291 * take an address as such, but a cookie.
293 * Again, this are defined to perform little endian accesses. See the
294 * IO port primitives for more information.
297 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
298 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
299 __raw_readw(c)); __r; })
300 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
301 __raw_readl(c)); __r; })
303 #define writeb_relaxed(v,c) __raw_writeb(v,c)
304 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
305 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
307 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
308 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
309 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
311 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
312 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
313 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
315 #define readsb(p,d,l) __raw_readsb(p,d,l)
316 #define readsw(p,d,l) __raw_readsw(p,d,l)
317 #define readsl(p,d,l) __raw_readsl(p,d,l)
319 #define writesb(p,d,l) __raw_writesb(p,d,l)
320 #define writesw(p,d,l) __raw_writesw(p,d,l)
321 #define writesl(p,d,l) __raw_writesl(p,d,l)
323 #define memset_io(c,v,l) _memset_io(c,(v),(l))
324 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
325 #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
330 * ioremap and friends.
332 * ioremap takes a PCI memory address, as specified in
333 * Documentation/io-mapping.txt.
336 #define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
337 #define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
338 #define ioremap_cache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
339 #define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC)
340 #define iounmap __arm_iounmap
343 * io{read,write}{8,16,32} macros
346 #define ioread8(p) ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
347 #define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
348 #define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
350 #define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
351 #define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
353 #define iowrite8(v,p) ({ __iowmb(); __raw_writeb(v, p); })
354 #define iowrite16(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_le16(v), p); })
355 #define iowrite32(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_le32(v), p); })
357 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
358 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
360 #define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
361 #define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
362 #define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
364 #define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
365 #define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
366 #define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
368 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
369 extern void ioport_unmap(void __iomem *addr);
374 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
377 * can the hardware map this into one segment or not, given no other
380 #define BIOVEC_MERGEABLE(vec1, vec2) \
381 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
384 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
385 const struct bio_vec *vec2);
386 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
387 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
388 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
391 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
392 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
393 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
394 extern int devmem_is_allowed(unsigned long pfn);
398 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
401 #define xlate_dev_mem_ptr(p) __va(p)
404 * Convert a virtual cached pointer to an uncached pointer
406 #define xlate_dev_kmem_ptr(p) p
409 * Register ISA memory and port locations for glibc iopl/inb/outb
412 extern void register_isa_ports(unsigned int mmio, unsigned int io,
413 unsigned int io_shift);
415 #endif /* __KERNEL__ */
416 #endif /* __ASM_ARM_IO_H */