Pileus Git - ~andy/linux/blob - arch/arm/include/asm/cputype.h

   1 #ifndef __ASM_ARM_CPUTYPE_H
   2 #define __ASM_ARM_CPUTYPE_H
   3
   4 #include <linux/stringify.h>
   5 #include <linux/kernel.h>
   6
   7 #define CPUID_ID        0
   8 #define CPUID_CACHETYPE 1
   9 #define CPUID_TCM       2
  10 #define CPUID_TLBTYPE   3
  11 #define CPUID_MPIDR     5
  12
  13 #ifdef CONFIG_CPU_V7M
  14 #define CPUID_EXT_PFR0  0x40
  15 #define CPUID_EXT_PFR1  0x44
  16 #define CPUID_EXT_DFR0  0x48
  17 #define CPUID_EXT_AFR0  0x4c
  18 #define CPUID_EXT_MMFR0 0x50
  19 #define CPUID_EXT_MMFR1 0x54
  20 #define CPUID_EXT_MMFR2 0x58
  21 #define CPUID_EXT_MMFR3 0x5c
  22 #define CPUID_EXT_ISAR0 0x60
  23 #define CPUID_EXT_ISAR1 0x64
  24 #define CPUID_EXT_ISAR2 0x68
  25 #define CPUID_EXT_ISAR3 0x6c
  26 #define CPUID_EXT_ISAR4 0x70
  27 #define CPUID_EXT_ISAR5 0x74
  28 #else
  29 #define CPUID_EXT_PFR0  "c1, 0"
  30 #define CPUID_EXT_PFR1  "c1, 1"
  31 #define CPUID_EXT_DFR0  "c1, 2"
  32 #define CPUID_EXT_AFR0  "c1, 3"
  33 #define CPUID_EXT_MMFR0 "c1, 4"
  34 #define CPUID_EXT_MMFR1 "c1, 5"
  35 #define CPUID_EXT_MMFR2 "c1, 6"
  36 #define CPUID_EXT_MMFR3 "c1, 7"
  37 #define CPUID_EXT_ISAR0 "c2, 0"
  38 #define CPUID_EXT_ISAR1 "c2, 1"
  39 #define CPUID_EXT_ISAR2 "c2, 2"
  40 #define CPUID_EXT_ISAR3 "c2, 3"
  41 #define CPUID_EXT_ISAR4 "c2, 4"
  42 #define CPUID_EXT_ISAR5 "c2, 5"
  43 #endif
  44
  45 #define MPIDR_SMP_BITMASK (0x3 << 30)
  46 #define MPIDR_SMP_VALUE (0x2 << 30)
  47
  48 #define MPIDR_MT_BITMASK (0x1 << 24)
  49
  50 #define MPIDR_HWID_BITMASK 0xFFFFFF
  51
  52 #define MPIDR_LEVEL_BITS 8
  53 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  54
  55 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  56         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  57
  58 #define ARM_CPU_IMP_ARM                 0x41
  59 #define ARM_CPU_IMP_INTEL               0x69
  60
  61 #define ARM_CPU_PART_ARM1136            0xB360
  62 #define ARM_CPU_PART_ARM1156            0xB560
  63 #define ARM_CPU_PART_ARM1176            0xB760
  64 #define ARM_CPU_PART_ARM11MPCORE        0xB020
  65 #define ARM_CPU_PART_CORTEX_A8          0xC080
  66 #define ARM_CPU_PART_CORTEX_A9          0xC090
  67 #define ARM_CPU_PART_CORTEX_A5          0xC050
  68 #define ARM_CPU_PART_CORTEX_A15         0xC0F0
  69 #define ARM_CPU_PART_CORTEX_A7          0xC070
  70
  71 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
  72 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
  73 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
  74 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
  75
  76 extern unsigned int processor_id;
  77
  78 #ifdef CONFIG_CPU_CP15
  79 #define read_cpuid(reg)                                                 \
  80         ({                                                              \
  81                 unsigned int __val;                                     \
  82                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
  83                     : "=r" (__val)                                      \
  84                     :                                                   \
  85                     : "cc");                                            \
  86                 __val;                                                  \
  87         })
  88
  89 #define read_cpuid_ext(ext_reg)                                         \
  90         ({                                                              \
  91                 unsigned int __val;                                     \
  92                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
  93                     : "=r" (__val)                                      \
  94                     :                                                   \
  95                     : "cc");                                            \
  96                 __val;                                                  \
  97         })
  98
  99 #elif defined(CONFIG_CPU_V7M)
 100
 101 #include <asm/io.h>
 102 #include <asm/v7m.h>
 103
 104 #define read_cpuid(reg)                                                 \
 105         ({                                                              \
 106                 WARN_ON_ONCE(1);                                        \
 107                 0;                                                      \
 108         })
 109
 110 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 111 {
 112         return readl(BASEADDR_V7M_SCB + offset);
 113 }
 114
 115 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 116
 117 /*
 118  * read_cpuid and read_cpuid_ext should only ever be called on machines that
 119  * have cp15 so warn on other usages.
 120  */
 121 #define read_cpuid(reg)                                                 \
 122         ({                                                              \
 123                 WARN_ON_ONCE(1);                                        \
 124                 0;                                                      \
 125         })
 126
 127 #define read_cpuid_ext(reg) read_cpuid(reg)
 128
 129 #endif /* ifdef CONFIG_CPU_CP15 / else */
 130
 131 #ifdef CONFIG_CPU_CP15
 132 /*
 133  * The CPU ID never changes at run time, so we might as well tell the
 134  * compiler that it's constant.  Use this function to read the CPU ID
 135  * rather than directly reading processor_id or read_cpuid() directly.
 136  */
 137 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 138 {
 139         return read_cpuid(CPUID_ID);
 140 }
 141
 142 #elif defined(CONFIG_CPU_V7M)
 143
 144 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 145 {
 146         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 147 }
 148
 149 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 150
 151 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 152 {
 153         return processor_id;
 154 }
 155
 156 #endif /* ifdef CONFIG_CPU_CP15 / else */
 157
 158 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 159 {
 160         return (read_cpuid_id() & 0xFF000000) >> 24;
 161 }
 162
 163 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
 164 {
 165         return read_cpuid_id() & 0xFFF0;
 166 }
 167
 168 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 169 {
 170         return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
 171 }
 172
 173 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 174 {
 175         return read_cpuid(CPUID_CACHETYPE);
 176 }
 177
 178 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 179 {
 180         return read_cpuid(CPUID_TCM);
 181 }
 182
 183 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 184 {
 185         return read_cpuid(CPUID_MPIDR);
 186 }
 187
 188 /*
 189  * Intel's XScale3 core supports some v6 features (supersections, L2)
 190  * but advertises itself as v5 as it does not support the v6 ISA.  For
 191  * this reason, we need a way to explicitly test for this type of CPU.
 192  */
 193 #ifndef CONFIG_CPU_XSC3
 194 #define cpu_is_xsc3()   0
 195 #else
 196 static inline int cpu_is_xsc3(void)
 197 {
 198         unsigned int id;
 199         id = read_cpuid_id() & 0xffffe000;
 200         /* It covers both Intel ID and Marvell ID */
 201         if ((id == 0x69056000) || (id == 0x56056000))
 202                 return 1;
 203
 204         return 0;
 205 }
 206 #endif
 207
 208 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
 209 #define cpu_is_xscale() 0
 210 #else
 211 #define cpu_is_xscale() 1
 212 #endif
 213
 214 #endif