Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/tegra30.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra30";
   5         interrupt-parent = <&intc>;
   6
   7         aliases {
   8                 serial0 = &uarta;
   9                 serial1 = &uartb;
  10                 serial2 = &uartc;
  11                 serial3 = &uartd;
  12                 serial4 = &uarte;
  13         };
  14
  15         host1x {
  16                 compatible = "nvidia,tegra30-host1x", "simple-bus";
  17                 reg = <0x50000000 0x00024000>;
  18                 interrupts = <0 65 0x04   /* mpcore syncpt */
  19                               0 67 0x04>; /* mpcore general */
  20                 clocks = <&tegra_car 28>;
  21
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24
  25                 ranges = <0x54000000 0x54000000 0x04000000>;
  26
  27                 mpe {
  28                         compatible = "nvidia,tegra30-mpe";
  29                         reg = <0x54040000 0x00040000>;
  30                         interrupts = <0 68 0x04>;
  31                         clocks = <&tegra_car 60>;
  32                 };
  33
  34                 vi {
  35                         compatible = "nvidia,tegra30-vi";
  36                         reg = <0x54080000 0x00040000>;
  37                         interrupts = <0 69 0x04>;
  38                         clocks = <&tegra_car 164>;
  39                 };
  40
  41                 epp {
  42                         compatible = "nvidia,tegra30-epp";
  43                         reg = <0x540c0000 0x00040000>;
  44                         interrupts = <0 70 0x04>;
  45                         clocks = <&tegra_car 19>;
  46                 };
  47
  48                 isp {
  49                         compatible = "nvidia,tegra30-isp";
  50                         reg = <0x54100000 0x00040000>;
  51                         interrupts = <0 71 0x04>;
  52                         clocks = <&tegra_car 23>;
  53                 };
  54
  55                 gr2d {
  56                         compatible = "nvidia,tegra30-gr2d";
  57                         reg = <0x54140000 0x00040000>;
  58                         interrupts = <0 72 0x04>;
  59                         clocks = <&tegra_car 21>;
  60                 };
  61
  62                 gr3d {
  63                         compatible = "nvidia,tegra30-gr3d";
  64                         reg = <0x54180000 0x00040000>;
  65                         clocks = <&tegra_car 24 &tegra_car 98>;
  66                         clock-names = "3d", "3d2";
  67                 };
  68
  69                 dc@54200000 {
  70                         compatible = "nvidia,tegra30-dc";
  71                         reg = <0x54200000 0x00040000>;
  72                         interrupts = <0 73 0x04>;
  73                         clocks = <&tegra_car 27>, <&tegra_car 179>;
  74                         clock-names = "disp1", "parent";
  75
  76                         rgb {
  77                                 status = "disabled";
  78                         };
  79                 };
  80
  81                 dc@54240000 {
  82                         compatible = "nvidia,tegra30-dc";
  83                         reg = <0x54240000 0x00040000>;
  84                         interrupts = <0 74 0x04>;
  85                         clocks = <&tegra_car 26>, <&tegra_car 179>;
  86                         clock-names = "disp2", "parent";
  87
  88                         rgb {
  89                                 status = "disabled";
  90                         };
  91                 };
  92
  93                 hdmi {
  94                         compatible = "nvidia,tegra30-hdmi";
  95                         reg = <0x54280000 0x00040000>;
  96                         interrupts = <0 75 0x04>;
  97                         clocks = <&tegra_car 51>, <&tegra_car 189>;
  98                         clock-names = "hdmi", "parent";
  99                         status = "disabled";
 100                 };
 101
 102                 tvo {
 103                         compatible = "nvidia,tegra30-tvo";
 104                         reg = <0x542c0000 0x00040000>;
 105                         interrupts = <0 76 0x04>;
 106                         clocks = <&tegra_car 169>;
 107                         status = "disabled";
 108                 };
 109
 110                 dsi {
 111                         compatible = "nvidia,tegra30-dsi";
 112                         reg = <0x54300000 0x00040000>;
 113                         clocks = <&tegra_car 48>;
 114                         status = "disabled";
 115                 };
 116         };
 117
 118         timer@50004600 {
 119                 compatible = "arm,cortex-a9-twd-timer";
 120                 reg = <0x50040600 0x20>;
 121                 interrupts = <1 13 0xf04>;
 122                 clocks = <&tegra_car 214>;
 123         };
 124
 125         intc: interrupt-controller {
 126                 compatible = "arm,cortex-a9-gic";
 127                 reg = <0x50041000 0x1000
 128                        0x50040100 0x0100>;
 129                 interrupt-controller;
 130                 #interrupt-cells = <3>;
 131         };
 132
 133         cache-controller {
 134                 compatible = "arm,pl310-cache";
 135                 reg = <0x50043000 0x1000>;
 136                 arm,data-latency = <6 6 2>;
 137                 arm,tag-latency = <5 5 2>;
 138                 cache-unified;
 139                 cache-level = <2>;
 140         };
 141
 142         timer@60005000 {
 143                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 144                 reg = <0x60005000 0x400>;
 145                 interrupts = <0 0 0x04
 146                               0 1 0x04
 147                               0 41 0x04
 148                               0 42 0x04
 149                               0 121 0x04
 150                               0 122 0x04>;
 151                 clocks = <&tegra_car 5>;
 152         };
 153
 154         tegra_car: clock {
 155                 compatible = "nvidia,tegra30-car";
 156                 reg = <0x60006000 0x1000>;
 157                 #clock-cells = <1>;
 158         };
 159
 160         apbdma: dma {
 161                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 162                 reg = <0x6000a000 0x1400>;
 163                 interrupts = <0 104 0x04
 164                               0 105 0x04
 165                               0 106 0x04
 166                               0 107 0x04
 167                               0 108 0x04
 168                               0 109 0x04
 169                               0 110 0x04
 170                               0 111 0x04
 171                               0 112 0x04
 172                               0 113 0x04
 173                               0 114 0x04
 174                               0 115 0x04
 175                               0 116 0x04
 176                               0 117 0x04
 177                               0 118 0x04
 178                               0 119 0x04
 179                               0 128 0x04
 180                               0 129 0x04
 181                               0 130 0x04
 182                               0 131 0x04
 183                               0 132 0x04
 184                               0 133 0x04
 185                               0 134 0x04
 186                               0 135 0x04
 187                               0 136 0x04
 188                               0 137 0x04
 189                               0 138 0x04
 190                               0 139 0x04
 191                               0 140 0x04
 192                               0 141 0x04
 193                               0 142 0x04
 194                               0 143 0x04>;
 195                 clocks = <&tegra_car 34>;
 196         };
 197
 198         ahb: ahb {
 199                 compatible = "nvidia,tegra30-ahb";
 200                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
 201         };
 202
 203         gpio: gpio {
 204                 compatible = "nvidia,tegra30-gpio";
 205                 reg = <0x6000d000 0x1000>;
 206                 interrupts = <0 32 0x04
 207                               0 33 0x04
 208                               0 34 0x04
 209                               0 35 0x04
 210                               0 55 0x04
 211                               0 87 0x04
 212                               0 89 0x04
 213                               0 125 0x04>;
 214                 #gpio-cells = <2>;
 215                 gpio-controller;
 216                 #interrupt-cells = <2>;
 217                 interrupt-controller;
 218         };
 219
 220         pinmux: pinmux {
 221                 compatible = "nvidia,tegra30-pinmux";
 222                 reg = <0x70000868 0xd4    /* Pad control registers */
 223                        0x70003000 0x3e4>; /* Mux registers */
 224         };
 225
 226         /*
 227          * There are two serial driver i.e. 8250 based simple serial
 228          * driver and APB DMA based serial driver for higher baudrate
 229          * and performace. To enable the 8250 based driver, the compatible
 230          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 231          * the APB DMA based serial driver, the comptible is
 232          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 233          */
 234         uarta: serial@70006000 {
 235                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 236                 reg = <0x70006000 0x40>;
 237                 reg-shift = <2>;
 238                 interrupts = <0 36 0x04>;
 239                 nvidia,dma-request-selector = <&apbdma 8>;
 240                 clocks = <&tegra_car 6>;
 241                 status = "disabled";
 242         };
 243
 244         uartb: serial@70006040 {
 245                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 246                 reg = <0x70006040 0x40>;
 247                 reg-shift = <2>;
 248                 interrupts = <0 37 0x04>;
 249                 nvidia,dma-request-selector = <&apbdma 9>;
 250                 clocks = <&tegra_car 160>;
 251                 status = "disabled";
 252         };
 253
 254         uartc: serial@70006200 {
 255                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 256                 reg = <0x70006200 0x100>;
 257                 reg-shift = <2>;
 258                 interrupts = <0 46 0x04>;
 259                 nvidia,dma-request-selector = <&apbdma 10>;
 260                 clocks = <&tegra_car 55>;
 261                 status = "disabled";
 262         };
 263
 264         uartd: serial@70006300 {
 265                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 266                 reg = <0x70006300 0x100>;
 267                 reg-shift = <2>;
 268                 interrupts = <0 90 0x04>;
 269                 nvidia,dma-request-selector = <&apbdma 19>;
 270                 clocks = <&tegra_car 65>;
 271                 status = "disabled";
 272         };
 273
 274         uarte: serial@70006400 {
 275                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 276                 reg = <0x70006400 0x100>;
 277                 reg-shift = <2>;
 278                 interrupts = <0 91 0x04>;
 279                 nvidia,dma-request-selector = <&apbdma 20>;
 280                 clocks = <&tegra_car 66>;
 281                 status = "disabled";
 282         };
 283
 284         pwm: pwm {
 285                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 286                 reg = <0x7000a000 0x100>;
 287                 #pwm-cells = <2>;
 288                 clocks = <&tegra_car 17>;
 289         };
 290
 291         rtc {
 292                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 293                 reg = <0x7000e000 0x100>;
 294                 interrupts = <0 2 0x04>;
 295                 clocks = <&tegra_car 4>;
 296         };
 297
 298         i2c@7000c000 {
 299                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 300                 reg = <0x7000c000 0x100>;
 301                 interrupts = <0 38 0x04>;
 302                 #address-cells = <1>;
 303                 #size-cells = <0>;
 304                 clocks = <&tegra_car 12>, <&tegra_car 182>;
 305                 clock-names = "div-clk", "fast-clk";
 306                 status = "disabled";
 307         };
 308
 309         i2c@7000c400 {
 310                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 311                 reg = <0x7000c400 0x100>;
 312                 interrupts = <0 84 0x04>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 clocks = <&tegra_car 54>, <&tegra_car 182>;
 316                 clock-names = "div-clk", "fast-clk";
 317                 status = "disabled";
 318         };
 319
 320         i2c@7000c500 {
 321                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 322                 reg = <0x7000c500 0x100>;
 323                 interrupts = <0 92 0x04>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 clocks = <&tegra_car 67>, <&tegra_car 182>;
 327                 clock-names = "div-clk", "fast-clk";
 328                 status = "disabled";
 329         };
 330
 331         i2c@7000c700 {
 332                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 333                 reg = <0x7000c700 0x100>;
 334                 interrupts = <0 120 0x04>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337                 clocks = <&tegra_car 103>, <&tegra_car 182>;
 338                 clock-names = "div-clk", "fast-clk";
 339                 status = "disabled";
 340         };
 341
 342         i2c@7000d000 {
 343                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 344                 reg = <0x7000d000 0x100>;
 345                 interrupts = <0 53 0x04>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clocks = <&tegra_car 47>, <&tegra_car 182>;
 349                 clock-names = "div-clk", "fast-clk";
 350                 status = "disabled";
 351         };
 352
 353         spi@7000d400 {
 354                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 355                 reg = <0x7000d400 0x200>;
 356                 interrupts = <0 59 0x04>;
 357                 nvidia,dma-request-selector = <&apbdma 15>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 clocks = <&tegra_car 41>;
 361                 status = "disabled";
 362         };
 363
 364         spi@7000d600 {
 365                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 366                 reg = <0x7000d600 0x200>;
 367                 interrupts = <0 82 0x04>;
 368                 nvidia,dma-request-selector = <&apbdma 16>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 clocks = <&tegra_car 44>;
 372                 status = "disabled";
 373         };
 374
 375         spi@7000d800 {
 376                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 377                 reg = <0x7000d800 0x200>;
 378                 interrupts = <0 83 0x04>;
 379                 nvidia,dma-request-selector = <&apbdma 17>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382                 clocks = <&tegra_car 46>;
 383                 status = "disabled";
 384         };
 385
 386         spi@7000da00 {
 387                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 388                 reg = <0x7000da00 0x200>;
 389                 interrupts = <0 93 0x04>;
 390                 nvidia,dma-request-selector = <&apbdma 18>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 clocks = <&tegra_car 68>;
 394                 status = "disabled";
 395         };
 396
 397         spi@7000dc00 {
 398                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 399                 reg = <0x7000dc00 0x200>;
 400                 interrupts = <0 94 0x04>;
 401                 nvidia,dma-request-selector = <&apbdma 27>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 clocks = <&tegra_car 104>;
 405                 status = "disabled";
 406         };
 407
 408         spi@7000de00 {
 409                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 410                 reg = <0x7000de00 0x200>;
 411                 interrupts = <0 79 0x04>;
 412                 nvidia,dma-request-selector = <&apbdma 28>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 clocks = <&tegra_car 105>;
 416                 status = "disabled";
 417         };
 418
 419         kbc {
 420                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 421                 reg = <0x7000e200 0x100>;
 422                 interrupts = <0 85 0x04>;
 423                 clocks = <&tegra_car 36>;
 424                 status = "disabled";
 425         };
 426
 427         pmc {
 428                 compatible = "nvidia,tegra30-pmc";
 429                 reg = <0x7000e400 0x400>;
 430                 clocks = <&tegra_car 218>, <&clk32k_in>;
 431                 clock-names = "pclk", "clk32k_in";
 432         };
 433
 434         memory-controller {
 435                 compatible = "nvidia,tegra30-mc";
 436                 reg = <0x7000f000 0x010
 437                        0x7000f03c 0x1b4
 438                        0x7000f200 0x028
 439                        0x7000f284 0x17c>;
 440                 interrupts = <0 77 0x04>;
 441         };
 442
 443         iommu {
 444                 compatible = "nvidia,tegra30-smmu";
 445                 reg = <0x7000f010 0x02c
 446                        0x7000f1f0 0x010
 447                        0x7000f228 0x05c>;
 448                 nvidia,#asids = <4>;            /* # of ASIDs */
 449                 dma-window = <0 0x40000000>;    /* IOVA start & length */
 450                 nvidia,ahb = <&ahb>;
 451         };
 452
 453         ahub {
 454                 compatible = "nvidia,tegra30-ahub";
 455                 reg = <0x70080000 0x200
 456                        0x70080200 0x100>;
 457                 interrupts = <0 103 0x04>;
 458                 nvidia,dma-request-selector = <&apbdma 1>;
 459                 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
 460                          <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
 461                          <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
 462                          <&tegra_car 110>, <&tegra_car 162>;
 463                 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 464                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 465                               "spdif_in";
 466                 ranges;
 467                 #address-cells = <1>;
 468                 #size-cells = <1>;
 469
 470                 tegra_i2s0: i2s@70080300 {
 471                         compatible = "nvidia,tegra30-i2s";
 472                         reg = <0x70080300 0x100>;
 473                         nvidia,ahub-cif-ids = <4 4>;
 474                         clocks = <&tegra_car 30>;
 475                         status = "disabled";
 476                 };
 477
 478                 tegra_i2s1: i2s@70080400 {
 479                         compatible = "nvidia,tegra30-i2s";
 480                         reg = <0x70080400 0x100>;
 481                         nvidia,ahub-cif-ids = <5 5>;
 482                         clocks = <&tegra_car 11>;
 483                         status = "disabled";
 484                 };
 485
 486                 tegra_i2s2: i2s@70080500 {
 487                         compatible = "nvidia,tegra30-i2s";
 488                         reg = <0x70080500 0x100>;
 489                         nvidia,ahub-cif-ids = <6 6>;
 490                         clocks = <&tegra_car 18>;
 491                         status = "disabled";
 492                 };
 493
 494                 tegra_i2s3: i2s@70080600 {
 495                         compatible = "nvidia,tegra30-i2s";
 496                         reg = <0x70080600 0x100>;
 497                         nvidia,ahub-cif-ids = <7 7>;
 498                         clocks = <&tegra_car 101>;
 499                         status = "disabled";
 500                 };
 501
 502                 tegra_i2s4: i2s@70080700 {
 503                         compatible = "nvidia,tegra30-i2s";
 504                         reg = <0x70080700 0x100>;
 505                         nvidia,ahub-cif-ids = <8 8>;
 506                         clocks = <&tegra_car 102>;
 507                         status = "disabled";
 508                 };
 509         };
 510
 511         sdhci@78000000 {
 512                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 513                 reg = <0x78000000 0x200>;
 514                 interrupts = <0 14 0x04>;
 515                 clocks = <&tegra_car 14>;
 516                 status = "disabled";
 517         };
 518
 519         sdhci@78000200 {
 520                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 521                 reg = <0x78000200 0x200>;
 522                 interrupts = <0 15 0x04>;
 523                 clocks = <&tegra_car 9>;
 524                 status = "disabled";
 525         };
 526
 527         sdhci@78000400 {
 528                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 529                 reg = <0x78000400 0x200>;
 530                 interrupts = <0 19 0x04>;
 531                 clocks = <&tegra_car 69>;
 532                 status = "disabled";
 533         };
 534
 535         sdhci@78000600 {
 536                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 537                 reg = <0x78000600 0x200>;
 538                 interrupts = <0 31 0x04>;
 539                 clocks = <&tegra_car 15>;
 540                 status = "disabled";
 541         };
 542
 543         cpus {
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546
 547                 cpu@0 {
 548                         device_type = "cpu";
 549                         compatible = "arm,cortex-a9";
 550                         reg = <0>;
 551                 };
 552
 553                 cpu@1 {
 554                         device_type = "cpu";
 555                         compatible = "arm,cortex-a9";
 556                         reg = <1>;
 557                 };
 558
 559                 cpu@2 {
 560                         device_type = "cpu";
 561                         compatible = "arm,cortex-a9";
 562                         reg = <2>;
 563                 };
 564
 565                 cpu@3 {
 566                         device_type = "cpu";
 567                         compatible = "arm,cortex-a9";
 568                         reg = <3>;
 569                 };
 570         };
 571
 572         pmu {
 573                 compatible = "arm,cortex-a9-pmu";
 574                 interrupts = <0 144 0x04
 575                               0 145 0x04
 576                               0 146 0x04
 577                               0 147 0x04>;
 578         };
 579 };