Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/sun5i-a10s.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         cpus {
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a8";
  22                 };
  23         };
  24
  25         memory {
  26                 reg = <0x40000000 0x20000000>;
  27         };
  28
  29         clocks {
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 ranges;
  33
  34                 /*
  35                  * This is a dummy clock, to be used as placeholder on
  36                  * other mux clocks when a specific parent clock is not
  37                  * yet implemented. It should be dropped when the driver
  38                  * is complete.
  39                  */
  40                 dummy: dummy {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <0>;
  44                 };
  45
  46                 osc24M: osc24M@01c20050 {
  47                         #clock-cells = <0>;
  48                         compatible = "allwinner,sun4i-osc-clk";
  49                         reg = <0x01c20050 0x4>;
  50                         clock-frequency = <24000000>;
  51                 };
  52
  53                 osc32k: osc32k {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <32768>;
  57                 };
  58
  59                 pll1: pll1@01c20000 {
  60                         #clock-cells = <0>;
  61                         compatible = "allwinner,sun4i-pll1-clk";
  62                         reg = <0x01c20000 0x4>;
  63                         clocks = <&osc24M>;
  64                 };
  65
  66                 pll4: pll4@01c20018 {
  67                         #clock-cells = <0>;
  68                         compatible = "allwinner,sun4i-pll1-clk";
  69                         reg = <0x01c20018 0x4>;
  70                         clocks = <&osc24M>;
  71                 };
  72
  73                 pll5: pll5@01c20020 {
  74                         #clock-cells = <1>;
  75                         compatible = "allwinner,sun4i-pll5-clk";
  76                         reg = <0x01c20020 0x4>;
  77                         clocks = <&osc24M>;
  78                         clock-output-names = "pll5_ddr", "pll5_other";
  79                 };
  80
  81                 pll6: pll6@01c20028 {
  82                         #clock-cells = <1>;
  83                         compatible = "allwinner,sun4i-pll6-clk";
  84                         reg = <0x01c20028 0x4>;
  85                         clocks = <&osc24M>;
  86                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
  87                 };
  88
  89                 /* dummy is 200M */
  90                 cpu: cpu@01c20054 {
  91                         #clock-cells = <0>;
  92                         compatible = "allwinner,sun4i-cpu-clk";
  93                         reg = <0x01c20054 0x4>;
  94                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  95                 };
  96
  97                 axi: axi@01c20054 {
  98                         #clock-cells = <0>;
  99                         compatible = "allwinner,sun4i-axi-clk";
 100                         reg = <0x01c20054 0x4>;
 101                         clocks = <&cpu>;
 102                 };
 103
 104                 axi_gates: axi_gates@01c2005c {
 105                         #clock-cells = <1>;
 106                         compatible = "allwinner,sun4i-axi-gates-clk";
 107                         reg = <0x01c2005c 0x4>;
 108                         clocks = <&axi>;
 109                         clock-output-names = "axi_dram";
 110                 };
 111
 112                 ahb: ahb@01c20054 {
 113                         #clock-cells = <0>;
 114                         compatible = "allwinner,sun4i-ahb-clk";
 115                         reg = <0x01c20054 0x4>;
 116                         clocks = <&axi>;
 117                 };
 118
 119                 ahb_gates: ahb_gates@01c20060 {
 120                         #clock-cells = <1>;
 121                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 122                         reg = <0x01c20060 0x8>;
 123                         clocks = <&ahb>;
 124                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 125                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 126                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 127                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 128                                 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
 129                                 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
 130                                 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
 131                 };
 132
 133                 apb0: apb0@01c20054 {
 134                         #clock-cells = <0>;
 135                         compatible = "allwinner,sun4i-apb0-clk";
 136                         reg = <0x01c20054 0x4>;
 137                         clocks = <&ahb>;
 138                 };
 139
 140                 apb0_gates: apb0_gates@01c20068 {
 141                         #clock-cells = <1>;
 142                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 143                         reg = <0x01c20068 0x4>;
 144                         clocks = <&apb0>;
 145                         clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
 146                                 "apb0_ir", "apb0_keypad";
 147                 };
 148
 149                 apb1_mux: apb1_mux@01c20058 {
 150                         #clock-cells = <0>;
 151                         compatible = "allwinner,sun4i-apb1-mux-clk";
 152                         reg = <0x01c20058 0x4>;
 153                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 154                 };
 155
 156                 apb1: apb1@01c20058 {
 157                         #clock-cells = <0>;
 158                         compatible = "allwinner,sun4i-apb1-clk";
 159                         reg = <0x01c20058 0x4>;
 160                         clocks = <&apb1_mux>;
 161                 };
 162
 163                 apb1_gates: apb1_gates@01c2006c {
 164                         #clock-cells = <1>;
 165                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 166                         reg = <0x01c2006c 0x4>;
 167                         clocks = <&apb1>;
 168                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 169                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
 170                                 "apb1_uart2", "apb1_uart3";
 171                 };
 172
 173                 nand_clk: clk@01c20080 {
 174                         #clock-cells = <0>;
 175                         compatible = "allwinner,sun4i-mod0-clk";
 176                         reg = <0x01c20080 0x4>;
 177                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 178                         clock-output-names = "nand";
 179                 };
 180
 181                 ms_clk: clk@01c20084 {
 182                         #clock-cells = <0>;
 183                         compatible = "allwinner,sun4i-mod0-clk";
 184                         reg = <0x01c20084 0x4>;
 185                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 186                         clock-output-names = "ms";
 187                 };
 188
 189                 mmc0_clk: clk@01c20088 {
 190                         #clock-cells = <0>;
 191                         compatible = "allwinner,sun4i-mod0-clk";
 192                         reg = <0x01c20088 0x4>;
 193                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 194                         clock-output-names = "mmc0";
 195                 };
 196
 197                 mmc1_clk: clk@01c2008c {
 198                         #clock-cells = <0>;
 199                         compatible = "allwinner,sun4i-mod0-clk";
 200                         reg = <0x01c2008c 0x4>;
 201                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 202                         clock-output-names = "mmc1";
 203                 };
 204
 205                 mmc2_clk: clk@01c20090 {
 206                         #clock-cells = <0>;
 207                         compatible = "allwinner,sun4i-mod0-clk";
 208                         reg = <0x01c20090 0x4>;
 209                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 210                         clock-output-names = "mmc2";
 211                 };
 212
 213                 ts_clk: clk@01c20098 {
 214                         #clock-cells = <0>;
 215                         compatible = "allwinner,sun4i-mod0-clk";
 216                         reg = <0x01c20098 0x4>;
 217                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 218                         clock-output-names = "ts";
 219                 };
 220
 221                 ss_clk: clk@01c2009c {
 222                         #clock-cells = <0>;
 223                         compatible = "allwinner,sun4i-mod0-clk";
 224                         reg = <0x01c2009c 0x4>;
 225                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 226                         clock-output-names = "ss";
 227                 };
 228
 229                 spi0_clk: clk@01c200a0 {
 230                         #clock-cells = <0>;
 231                         compatible = "allwinner,sun4i-mod0-clk";
 232                         reg = <0x01c200a0 0x4>;
 233                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 234                         clock-output-names = "spi0";
 235                 };
 236
 237                 spi1_clk: clk@01c200a4 {
 238                         #clock-cells = <0>;
 239                         compatible = "allwinner,sun4i-mod0-clk";
 240                         reg = <0x01c200a4 0x4>;
 241                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 242                         clock-output-names = "spi1";
 243                 };
 244
 245                 spi2_clk: clk@01c200a8 {
 246                         #clock-cells = <0>;
 247                         compatible = "allwinner,sun4i-mod0-clk";
 248                         reg = <0x01c200a8 0x4>;
 249                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 250                         clock-output-names = "spi2";
 251                 };
 252
 253                 ir0_clk: clk@01c200b0 {
 254                         #clock-cells = <0>;
 255                         compatible = "allwinner,sun4i-mod0-clk";
 256                         reg = <0x01c200b0 0x4>;
 257                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 258                         clock-output-names = "ir0";
 259                 };
 260
 261                 mbus_clk: clk@01c2015c {
 262                         #clock-cells = <0>;
 263                         compatible = "allwinner,sun4i-mod0-clk";
 264                         reg = <0x01c2015c 0x4>;
 265                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 266                         clock-output-names = "mbus";
 267                 };
 268         };
 269
 270         soc@01c00000 {
 271                 compatible = "simple-bus";
 272                 #address-cells = <1>;
 273                 #size-cells = <1>;
 274                 ranges;
 275
 276                 emac: ethernet@01c0b000 {
 277                         compatible = "allwinner,sun4i-emac";
 278                         reg = <0x01c0b000 0x1000>;
 279                         interrupts = <55>;
 280                         clocks = <&ahb_gates 17>;
 281                         status = "disabled";
 282                 };
 283
 284                 mdio@01c0b080 {
 285                         compatible = "allwinner,sun4i-mdio";
 286                         reg = <0x01c0b080 0x14>;
 287                         status = "disabled";
 288                         #address-cells = <1>;
 289                         #size-cells = <0>;
 290                 };
 291
 292                 intc: interrupt-controller@01c20400 {
 293                         compatible = "allwinner,sun4i-ic";
 294                         reg = <0x01c20400 0x400>;
 295                         interrupt-controller;
 296                         #interrupt-cells = <1>;
 297                 };
 298
 299                 pio: pinctrl@01c20800 {
 300                         compatible = "allwinner,sun5i-a10s-pinctrl";
 301                         reg = <0x01c20800 0x400>;
 302                         interrupts = <28>;
 303                         clocks = <&apb0_gates 5>;
 304                         gpio-controller;
 305                         interrupt-controller;
 306                         #address-cells = <1>;
 307                         #size-cells = <0>;
 308                         #gpio-cells = <3>;
 309
 310                         uart0_pins_a: uart0@0 {
 311                                 allwinner,pins = "PB19", "PB20";
 312                                 allwinner,function = "uart0";
 313                                 allwinner,drive = <0>;
 314                                 allwinner,pull = <0>;
 315                         };
 316
 317                         uart2_pins_a: uart2@0 {
 318                                 allwinner,pins = "PC18", "PC19";
 319                                 allwinner,function = "uart2";
 320                                 allwinner,drive = <0>;
 321                                 allwinner,pull = <0>;
 322                         };
 323
 324                         uart3_pins_a: uart3@0 {
 325                                 allwinner,pins = "PG9", "PG10";
 326                                 allwinner,function = "uart3";
 327                                 allwinner,drive = <0>;
 328                                 allwinner,pull = <0>;
 329                         };
 330
 331                         emac_pins_a: emac0@0 {
 332                                 allwinner,pins = "PA0", "PA1", "PA2",
 333                                                 "PA3", "PA4", "PA5", "PA6",
 334                                                 "PA7", "PA8", "PA9", "PA10",
 335                                                 "PA11", "PA12", "PA13", "PA14",
 336                                                 "PA15", "PA16";
 337                                 allwinner,function = "emac";
 338                                 allwinner,drive = <0>;
 339                                 allwinner,pull = <0>;
 340                         };
 341
 342                         i2c0_pins_a: i2c0@0 {
 343                                 allwinner,pins = "PB0", "PB1";
 344                                 allwinner,function = "i2c0";
 345                                 allwinner,drive = <0>;
 346                                 allwinner,pull = <0>;
 347                         };
 348
 349                         i2c1_pins_a: i2c1@0 {
 350                                 allwinner,pins = "PB15", "PB16";
 351                                 allwinner,function = "i2c1";
 352                                 allwinner,drive = <0>;
 353                                 allwinner,pull = <0>;
 354                         };
 355
 356                         i2c2_pins_a: i2c2@0 {
 357                                 allwinner,pins = "PB17", "PB18";
 358                                 allwinner,function = "i2c2";
 359                                 allwinner,drive = <0>;
 360                                 allwinner,pull = <0>;
 361                         };
 362                 };
 363
 364                 timer@01c20c00 {
 365                         compatible = "allwinner,sun4i-timer";
 366                         reg = <0x01c20c00 0x90>;
 367                         interrupts = <22>;
 368                         clocks = <&osc24M>;
 369                 };
 370
 371                 wdt: watchdog@01c20c90 {
 372                         compatible = "allwinner,sun4i-wdt";
 373                         reg = <0x01c20c90 0x10>;
 374                 };
 375
 376                 sid: eeprom@01c23800 {
 377                         compatible = "allwinner,sun4i-sid";
 378                         reg = <0x01c23800 0x10>;
 379                 };
 380
 381                 uart0: serial@01c28000 {
 382                         compatible = "snps,dw-apb-uart";
 383                         reg = <0x01c28000 0x400>;
 384                         interrupts = <1>;
 385                         reg-shift = <2>;
 386                         reg-io-width = <4>;
 387                         clocks = <&apb1_gates 16>;
 388                         status = "disabled";
 389                 };
 390
 391                 uart1: serial@01c28400 {
 392                         compatible = "snps,dw-apb-uart";
 393                         reg = <0x01c28400 0x400>;
 394                         interrupts = <2>;
 395                         reg-shift = <2>;
 396                         reg-io-width = <4>;
 397                         clocks = <&apb1_gates 17>;
 398                         status = "disabled";
 399                 };
 400
 401                 uart2: serial@01c28800 {
 402                         compatible = "snps,dw-apb-uart";
 403                         reg = <0x01c28800 0x400>;
 404                         interrupts = <3>;
 405                         reg-shift = <2>;
 406                         reg-io-width = <4>;
 407                         clocks = <&apb1_gates 18>;
 408                         status = "disabled";
 409                 };
 410
 411                 uart3: serial@01c28c00 {
 412                         compatible = "snps,dw-apb-uart";
 413                         reg = <0x01c28c00 0x400>;
 414                         interrupts = <4>;
 415                         reg-shift = <2>;
 416                         reg-io-width = <4>;
 417                         clocks = <&apb1_gates 19>;
 418                         status = "disabled";
 419                 };
 420
 421                 i2c0: i2c@01c2ac00 {
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         compatible = "allwinner,sun4i-i2c";
 425                         reg = <0x01c2ac00 0x400>;
 426                         interrupts = <7>;
 427                         clocks = <&apb1_gates 0>;
 428                         clock-frequency = <100000>;
 429                         status = "disabled";
 430                 };
 431
 432                 i2c1: i2c@01c2b000 {
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         compatible = "allwinner,sun4i-i2c";
 436                         reg = <0x01c2b000 0x400>;
 437                         interrupts = <8>;
 438                         clocks = <&apb1_gates 1>;
 439                         clock-frequency = <100000>;
 440                         status = "disabled";
 441                 };
 442
 443                 i2c2: i2c@01c2b400 {
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         compatible = "allwinner,sun4i-i2c";
 447                         reg = <0x01c2b400 0x400>;
 448                         interrupts = <9>;
 449                         clocks = <&apb1_gates 2>;
 450                         clock-frequency = <100000>;
 451                         status = "disabled";
 452                 };
 453         };
 454 };