Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         aliases {
  19                 ethernet0 = &emac;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25                 cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a8";
  28                         reg = <0x0>;
  29                 };
  30         };
  31
  32         memory {
  33                 reg = <0x40000000 0x80000000>;
  34         };
  35
  36         clocks {
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges;
  40
  41                 /*
  42                  * This is a dummy clock, to be used as placeholder on
  43                  * other mux clocks when a specific parent clock is not
  44                  * yet implemented. It should be dropped when the driver
  45                  * is complete.
  46                  */
  47                 dummy: dummy {
  48                         #clock-cells = <0>;
  49                         compatible = "fixed-clock";
  50                         clock-frequency = <0>;
  51                 };
  52
  53                 osc24M: osc24M@01c20050 {
  54                         #clock-cells = <0>;
  55                         compatible = "allwinner,sun4i-osc-clk";
  56                         reg = <0x01c20050 0x4>;
  57                         clock-frequency = <24000000>;
  58                 };
  59
  60                 osc32k: osc32k {
  61                         #clock-cells = <0>;
  62                         compatible = "fixed-clock";
  63                         clock-frequency = <32768>;
  64                 };
  65
  66                 pll1: pll1@01c20000 {
  67                         #clock-cells = <0>;
  68                         compatible = "allwinner,sun4i-pll1-clk";
  69                         reg = <0x01c20000 0x4>;
  70                         clocks = <&osc24M>;
  71                 };
  72
  73                 pll4: pll4@01c20018 {
  74                         #clock-cells = <0>;
  75                         compatible = "allwinner,sun4i-pll1-clk";
  76                         reg = <0x01c20018 0x4>;
  77                         clocks = <&osc24M>;
  78                 };
  79
  80                 pll5: pll5@01c20020 {
  81                         #clock-cells = <1>;
  82                         compatible = "allwinner,sun4i-pll5-clk";
  83                         reg = <0x01c20020 0x4>;
  84                         clocks = <&osc24M>;
  85                         clock-output-names = "pll5_ddr", "pll5_other";
  86                 };
  87
  88                 pll6: pll6@01c20028 {
  89                         #clock-cells = <1>;
  90                         compatible = "allwinner,sun4i-pll6-clk";
  91                         reg = <0x01c20028 0x4>;
  92                         clocks = <&osc24M>;
  93                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
  94                 };
  95
  96                 /* dummy is 200M */
  97                 cpu: cpu@01c20054 {
  98                         #clock-cells = <0>;
  99                         compatible = "allwinner,sun4i-cpu-clk";
 100                         reg = <0x01c20054 0x4>;
 101                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 102                 };
 103
 104                 axi: axi@01c20054 {
 105                         #clock-cells = <0>;
 106                         compatible = "allwinner,sun4i-axi-clk";
 107                         reg = <0x01c20054 0x4>;
 108                         clocks = <&cpu>;
 109                 };
 110
 111                 axi_gates: axi_gates@01c2005c {
 112                         #clock-cells = <1>;
 113                         compatible = "allwinner,sun4i-axi-gates-clk";
 114                         reg = <0x01c2005c 0x4>;
 115                         clocks = <&axi>;
 116                         clock-output-names = "axi_dram";
 117                 };
 118
 119                 ahb: ahb@01c20054 {
 120                         #clock-cells = <0>;
 121                         compatible = "allwinner,sun4i-ahb-clk";
 122                         reg = <0x01c20054 0x4>;
 123                         clocks = <&axi>;
 124                 };
 125
 126                 ahb_gates: ahb_gates@01c20060 {
 127                         #clock-cells = <1>;
 128                         compatible = "allwinner,sun4i-ahb-gates-clk";
 129                         reg = <0x01c20060 0x8>;
 130                         clocks = <&ahb>;
 131                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 132                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 133                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 134                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 135                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 136                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 137                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 138                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 139                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 140                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 141                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 142                 };
 143
 144                 apb0: apb0@01c20054 {
 145                         #clock-cells = <0>;
 146                         compatible = "allwinner,sun4i-apb0-clk";
 147                         reg = <0x01c20054 0x4>;
 148                         clocks = <&ahb>;
 149                 };
 150
 151                 apb0_gates: apb0_gates@01c20068 {
 152                         #clock-cells = <1>;
 153                         compatible = "allwinner,sun4i-apb0-gates-clk";
 154                         reg = <0x01c20068 0x4>;
 155                         clocks = <&apb0>;
 156                         clock-output-names = "apb0_codec", "apb0_spdif",
 157                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 158                                 "apb0_ir1", "apb0_keypad";
 159                 };
 160
 161                 apb1_mux: apb1_mux@01c20058 {
 162                         #clock-cells = <0>;
 163                         compatible = "allwinner,sun4i-apb1-mux-clk";
 164                         reg = <0x01c20058 0x4>;
 165                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 166                 };
 167
 168                 apb1: apb1@01c20058 {
 169                         #clock-cells = <0>;
 170                         compatible = "allwinner,sun4i-apb1-clk";
 171                         reg = <0x01c20058 0x4>;
 172                         clocks = <&apb1_mux>;
 173                 };
 174
 175                 apb1_gates: apb1_gates@01c2006c {
 176                         #clock-cells = <1>;
 177                         compatible = "allwinner,sun4i-apb1-gates-clk";
 178                         reg = <0x01c2006c 0x4>;
 179                         clocks = <&apb1>;
 180                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 181                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 182                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 183                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 184                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 185                                 "apb1_uart7";
 186                 };
 187
 188                 nand_clk: clk@01c20080 {
 189                         #clock-cells = <0>;
 190                         compatible = "allwinner,sun4i-mod0-clk";
 191                         reg = <0x01c20080 0x4>;
 192                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 193                         clock-output-names = "nand";
 194                 };
 195
 196                 ms_clk: clk@01c20084 {
 197                         #clock-cells = <0>;
 198                         compatible = "allwinner,sun4i-mod0-clk";
 199                         reg = <0x01c20084 0x4>;
 200                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 201                         clock-output-names = "ms";
 202                 };
 203
 204                 mmc0_clk: clk@01c20088 {
 205                         #clock-cells = <0>;
 206                         compatible = "allwinner,sun4i-mod0-clk";
 207                         reg = <0x01c20088 0x4>;
 208                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 209                         clock-output-names = "mmc0";
 210                 };
 211
 212                 mmc1_clk: clk@01c2008c {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun4i-mod0-clk";
 215                         reg = <0x01c2008c 0x4>;
 216                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 217                         clock-output-names = "mmc1";
 218                 };
 219
 220                 mmc2_clk: clk@01c20090 {
 221                         #clock-cells = <0>;
 222                         compatible = "allwinner,sun4i-mod0-clk";
 223                         reg = <0x01c20090 0x4>;
 224                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 225                         clock-output-names = "mmc2";
 226                 };
 227
 228                 mmc3_clk: clk@01c20094 {
 229                         #clock-cells = <0>;
 230                         compatible = "allwinner,sun4i-mod0-clk";
 231                         reg = <0x01c20094 0x4>;
 232                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 233                         clock-output-names = "mmc3";
 234                 };
 235
 236                 ts_clk: clk@01c20098 {
 237                         #clock-cells = <0>;
 238                         compatible = "allwinner,sun4i-mod0-clk";
 239                         reg = <0x01c20098 0x4>;
 240                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 241                         clock-output-names = "ts";
 242                 };
 243
 244                 ss_clk: clk@01c2009c {
 245                         #clock-cells = <0>;
 246                         compatible = "allwinner,sun4i-mod0-clk";
 247                         reg = <0x01c2009c 0x4>;
 248                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 249                         clock-output-names = "ss";
 250                 };
 251
 252                 spi0_clk: clk@01c200a0 {
 253                         #clock-cells = <0>;
 254                         compatible = "allwinner,sun4i-mod0-clk";
 255                         reg = <0x01c200a0 0x4>;
 256                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 257                         clock-output-names = "spi0";
 258                 };
 259
 260                 spi1_clk: clk@01c200a4 {
 261                         #clock-cells = <0>;
 262                         compatible = "allwinner,sun4i-mod0-clk";
 263                         reg = <0x01c200a4 0x4>;
 264                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 265                         clock-output-names = "spi1";
 266                 };
 267
 268                 spi2_clk: clk@01c200a8 {
 269                         #clock-cells = <0>;
 270                         compatible = "allwinner,sun4i-mod0-clk";
 271                         reg = <0x01c200a8 0x4>;
 272                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 273                         clock-output-names = "spi2";
 274                 };
 275
 276                 pata_clk: clk@01c200ac {
 277                         #clock-cells = <0>;
 278                         compatible = "allwinner,sun4i-mod0-clk";
 279                         reg = <0x01c200ac 0x4>;
 280                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 281                         clock-output-names = "pata";
 282                 };
 283
 284                 ir0_clk: clk@01c200b0 {
 285                         #clock-cells = <0>;
 286                         compatible = "allwinner,sun4i-mod0-clk";
 287                         reg = <0x01c200b0 0x4>;
 288                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 289                         clock-output-names = "ir0";
 290                 };
 291
 292                 ir1_clk: clk@01c200b4 {
 293                         #clock-cells = <0>;
 294                         compatible = "allwinner,sun4i-mod0-clk";
 295                         reg = <0x01c200b4 0x4>;
 296                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 297                         clock-output-names = "ir1";
 298                 };
 299
 300                 spi3_clk: clk@01c200d4 {
 301                         #clock-cells = <0>;
 302                         compatible = "allwinner,sun4i-mod0-clk";
 303                         reg = <0x01c200d4 0x4>;
 304                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 305                         clock-output-names = "spi3";
 306                 };
 307         };
 308
 309         soc@01c00000 {
 310                 compatible = "simple-bus";
 311                 #address-cells = <1>;
 312                 #size-cells = <1>;
 313                 ranges;
 314
 315                 emac: ethernet@01c0b000 {
 316                         compatible = "allwinner,sun4i-emac";
 317                         reg = <0x01c0b000 0x1000>;
 318                         interrupts = <55>;
 319                         clocks = <&ahb_gates 17>;
 320                         status = "disabled";
 321                 };
 322
 323                 mdio@01c0b080 {
 324                         compatible = "allwinner,sun4i-mdio";
 325                         reg = <0x01c0b080 0x14>;
 326                         status = "disabled";
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                 };
 330
 331                 intc: interrupt-controller@01c20400 {
 332                         compatible = "allwinner,sun4i-ic";
 333                         reg = <0x01c20400 0x400>;
 334                         interrupt-controller;
 335                         #interrupt-cells = <1>;
 336                 };
 337
 338                 pio: pinctrl@01c20800 {
 339                         compatible = "allwinner,sun4i-a10-pinctrl";
 340                         reg = <0x01c20800 0x400>;
 341                         interrupts = <28>;
 342                         clocks = <&apb0_gates 5>;
 343                         gpio-controller;
 344                         interrupt-controller;
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         #gpio-cells = <3>;
 348
 349                         uart0_pins_a: uart0@0 {
 350                                 allwinner,pins = "PB22", "PB23";
 351                                 allwinner,function = "uart0";
 352                                 allwinner,drive = <0>;
 353                                 allwinner,pull = <0>;
 354                         };
 355
 356                         uart0_pins_b: uart0@1 {
 357                                 allwinner,pins = "PF2", "PF4";
 358                                 allwinner,function = "uart0";
 359                                 allwinner,drive = <0>;
 360                                 allwinner,pull = <0>;
 361                         };
 362
 363                         uart1_pins_a: uart1@0 {
 364                                 allwinner,pins = "PA10", "PA11";
 365                                 allwinner,function = "uart1";
 366                                 allwinner,drive = <0>;
 367                                 allwinner,pull = <0>;
 368                         };
 369
 370                         i2c0_pins_a: i2c0@0 {
 371                                 allwinner,pins = "PB0", "PB1";
 372                                 allwinner,function = "i2c0";
 373                                 allwinner,drive = <0>;
 374                                 allwinner,pull = <0>;
 375                         };
 376
 377                         i2c1_pins_a: i2c1@0 {
 378                                 allwinner,pins = "PB18", "PB19";
 379                                 allwinner,function = "i2c1";
 380                                 allwinner,drive = <0>;
 381                                 allwinner,pull = <0>;
 382                         };
 383
 384                         i2c2_pins_a: i2c2@0 {
 385                                 allwinner,pins = "PB20", "PB21";
 386                                 allwinner,function = "i2c2";
 387                                 allwinner,drive = <0>;
 388                                 allwinner,pull = <0>;
 389                         };
 390
 391                         emac_pins_a: emac0@0 {
 392                                 allwinner,pins = "PA0", "PA1", "PA2",
 393                                                 "PA3", "PA4", "PA5", "PA6",
 394                                                 "PA7", "PA8", "PA9", "PA10",
 395                                                 "PA11", "PA12", "PA13", "PA14",
 396                                                 "PA15", "PA16";
 397                                 allwinner,function = "emac";
 398                                 allwinner,drive = <0>;
 399                                 allwinner,pull = <0>;
 400                         };
 401                 };
 402
 403                 timer@01c20c00 {
 404                         compatible = "allwinner,sun4i-timer";
 405                         reg = <0x01c20c00 0x90>;
 406                         interrupts = <22>;
 407                         clocks = <&osc24M>;
 408                 };
 409
 410                 wdt: watchdog@01c20c90 {
 411                         compatible = "allwinner,sun4i-wdt";
 412                         reg = <0x01c20c90 0x10>;
 413                 };
 414
 415                 rtc: rtc@01c20d00 {
 416                         compatible = "allwinner,sun4i-rtc";
 417                         reg = <0x01c20d00 0x20>;
 418                         interrupts = <24>;
 419                 };
 420
 421                 sid: eeprom@01c23800 {
 422                         compatible = "allwinner,sun4i-sid";
 423                         reg = <0x01c23800 0x10>;
 424                 };
 425
 426                 uart0: serial@01c28000 {
 427                         compatible = "snps,dw-apb-uart";
 428                         reg = <0x01c28000 0x400>;
 429                         interrupts = <1>;
 430                         reg-shift = <2>;
 431                         reg-io-width = <4>;
 432                         clocks = <&apb1_gates 16>;
 433                         status = "disabled";
 434                 };
 435
 436                 uart1: serial@01c28400 {
 437                         compatible = "snps,dw-apb-uart";
 438                         reg = <0x01c28400 0x400>;
 439                         interrupts = <2>;
 440                         reg-shift = <2>;
 441                         reg-io-width = <4>;
 442                         clocks = <&apb1_gates 17>;
 443                         status = "disabled";
 444                 };
 445
 446                 uart2: serial@01c28800 {
 447                         compatible = "snps,dw-apb-uart";
 448                         reg = <0x01c28800 0x400>;
 449                         interrupts = <3>;
 450                         reg-shift = <2>;
 451                         reg-io-width = <4>;
 452                         clocks = <&apb1_gates 18>;
 453                         status = "disabled";
 454                 };
 455
 456                 uart3: serial@01c28c00 {
 457                         compatible = "snps,dw-apb-uart";
 458                         reg = <0x01c28c00 0x400>;
 459                         interrupts = <4>;
 460                         reg-shift = <2>;
 461                         reg-io-width = <4>;
 462                         clocks = <&apb1_gates 19>;
 463                         status = "disabled";
 464                 };
 465
 466                 uart4: serial@01c29000 {
 467                         compatible = "snps,dw-apb-uart";
 468                         reg = <0x01c29000 0x400>;
 469                         interrupts = <17>;
 470                         reg-shift = <2>;
 471                         reg-io-width = <4>;
 472                         clocks = <&apb1_gates 20>;
 473                         status = "disabled";
 474                 };
 475
 476                 uart5: serial@01c29400 {
 477                         compatible = "snps,dw-apb-uart";
 478                         reg = <0x01c29400 0x400>;
 479                         interrupts = <18>;
 480                         reg-shift = <2>;
 481                         reg-io-width = <4>;
 482                         clocks = <&apb1_gates 21>;
 483                         status = "disabled";
 484                 };
 485
 486                 uart6: serial@01c29800 {
 487                         compatible = "snps,dw-apb-uart";
 488                         reg = <0x01c29800 0x400>;
 489                         interrupts = <19>;
 490                         reg-shift = <2>;
 491                         reg-io-width = <4>;
 492                         clocks = <&apb1_gates 22>;
 493                         status = "disabled";
 494                 };
 495
 496                 uart7: serial@01c29c00 {
 497                         compatible = "snps,dw-apb-uart";
 498                         reg = <0x01c29c00 0x400>;
 499                         interrupts = <20>;
 500                         reg-shift = <2>;
 501                         reg-io-width = <4>;
 502                         clocks = <&apb1_gates 23>;
 503                         status = "disabled";
 504                 };
 505
 506                 i2c0: i2c@01c2ac00 {
 507                         compatible = "allwinner,sun4i-i2c";
 508                         reg = <0x01c2ac00 0x400>;
 509                         interrupts = <7>;
 510                         clocks = <&apb1_gates 0>;
 511                         clock-frequency = <100000>;
 512                         status = "disabled";
 513                 };
 514
 515                 i2c1: i2c@01c2b000 {
 516                         compatible = "allwinner,sun4i-i2c";
 517                         reg = <0x01c2b000 0x400>;
 518                         interrupts = <8>;
 519                         clocks = <&apb1_gates 1>;
 520                         clock-frequency = <100000>;
 521                         status = "disabled";
 522                 };
 523
 524                 i2c2: i2c@01c2b400 {
 525                         compatible = "allwinner,sun4i-i2c";
 526                         reg = <0x01c2b400 0x400>;
 527                         interrupts = <9>;
 528                         clocks = <&apb1_gates 2>;
 529                         clock-frequency = <100000>;
 530                         status = "disabled";
 531                 };
 532         };
 533 };