Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13
  14 / {
  15         compatible = "renesas,r8a7790";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a15";
  27                         reg = <0>;
  28                         clock-frequency = <1300000000>;
  29                 };
  30
  31                 cpu1: cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a15";
  34                         reg = <1>;
  35                         clock-frequency = <1300000000>;
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a15";
  41                         reg = <2>;
  42                         clock-frequency = <1300000000>;
  43                 };
  44
  45                 cpu3: cpu@3 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <3>;
  49                         clock-frequency = <1300000000>;
  50                 };
  51
  52                 cpu4: cpu@4 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a7";
  55                         reg = <0x100>;
  56                         clock-frequency = <780000000>;
  57                 };
  58
  59                 cpu5: cpu@5 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a7";
  62                         reg = <0x101>;
  63                         clock-frequency = <780000000>;
  64                 };
  65
  66                 cpu6: cpu@6 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a7";
  69                         reg = <0x102>;
  70                         clock-frequency = <780000000>;
  71                 };
  72
  73                 cpu7: cpu@7 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a7";
  76                         reg = <0x103>;
  77                         clock-frequency = <780000000>;
  78                 };
  79         };
  80
  81         gic: interrupt-controller@f1001000 {
  82                 compatible = "arm,cortex-a15-gic";
  83                 #interrupt-cells = <3>;
  84                 #address-cells = <0>;
  85                 interrupt-controller;
  86                 reg = <0 0xf1001000 0 0x1000>,
  87                         <0 0xf1002000 0 0x1000>,
  88                         <0 0xf1004000 0 0x2000>,
  89                         <0 0xf1006000 0 0x2000>;
  90                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  91         };
  92
  93         gpio0: gpio@ffc40000 {
  94                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  95                 reg = <0 0xffc40000 0 0x2c>;
  96                 interrupt-parent = <&gic>;
  97                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  98                 #gpio-cells = <2>;
  99                 gpio-controller;
 100                 gpio-ranges = <&pfc 0 0 32>;
 101                 #interrupt-cells = <2>;
 102                 interrupt-controller;
 103         };
 104
 105         gpio1: gpio@ffc41000 {
 106                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 107                 reg = <0 0xffc41000 0 0x2c>;
 108                 interrupt-parent = <&gic>;
 109                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 110                 #gpio-cells = <2>;
 111                 gpio-controller;
 112                 gpio-ranges = <&pfc 0 32 32>;
 113                 #interrupt-cells = <2>;
 114                 interrupt-controller;
 115         };
 116
 117         gpio2: gpio@ffc42000 {
 118                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 119                 reg = <0 0xffc42000 0 0x2c>;
 120                 interrupt-parent = <&gic>;
 121                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 122                 #gpio-cells = <2>;
 123                 gpio-controller;
 124                 gpio-ranges = <&pfc 0 64 32>;
 125                 #interrupt-cells = <2>;
 126                 interrupt-controller;
 127         };
 128
 129         gpio3: gpio@ffc43000 {
 130                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 131                 reg = <0 0xffc43000 0 0x2c>;
 132                 interrupt-parent = <&gic>;
 133                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 134                 #gpio-cells = <2>;
 135                 gpio-controller;
 136                 gpio-ranges = <&pfc 0 96 32>;
 137                 #interrupt-cells = <2>;
 138                 interrupt-controller;
 139         };
 140
 141         gpio4: gpio@ffc44000 {
 142                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 143                 reg = <0 0xffc44000 0 0x2c>;
 144                 interrupt-parent = <&gic>;
 145                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 146                 #gpio-cells = <2>;
 147                 gpio-controller;
 148                 gpio-ranges = <&pfc 0 128 32>;
 149                 #interrupt-cells = <2>;
 150                 interrupt-controller;
 151         };
 152
 153         gpio5: gpio@ffc45000 {
 154                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 155                 reg = <0 0xffc45000 0 0x2c>;
 156                 interrupt-parent = <&gic>;
 157                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 158                 #gpio-cells = <2>;
 159                 gpio-controller;
 160                 gpio-ranges = <&pfc 0 160 32>;
 161                 #interrupt-cells = <2>;
 162                 interrupt-controller;
 163         };
 164
 165         thermal@e61f0000 {
 166                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 167                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 168                 interrupt-parent = <&gic>;
 169                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 170         };
 171
 172         timer {
 173                 compatible = "arm,armv7-timer";
 174                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 175                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 176                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 177                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 178         };
 179
 180         irqc0: interrupt-controller@e61c0000 {
 181                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 182                 #interrupt-cells = <2>;
 183                 interrupt-controller;
 184                 reg = <0 0xe61c0000 0 0x200>;
 185                 interrupt-parent = <&gic>;
 186                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 187                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 188                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 189                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 190         };
 191
 192         i2c0: i2c@e6508000 {
 193                 #address-cells = <1>;
 194                 #size-cells = <0>;
 195                 compatible = "renesas,i2c-r8a7790";
 196                 reg = <0 0xe6508000 0 0x40>;
 197                 interrupt-parent = <&gic>;
 198                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 199                 status = "disabled";
 200         };
 201
 202         i2c1: i2c@e6518000 {
 203                 #address-cells = <1>;
 204                 #size-cells = <0>;
 205                 compatible = "renesas,i2c-r8a7790";
 206                 reg = <0 0xe6518000 0 0x40>;
 207                 interrupt-parent = <&gic>;
 208                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 209                 status = "disabled";
 210         };
 211
 212         i2c2: i2c@e6530000 {
 213                 #address-cells = <1>;
 214                 #size-cells = <0>;
 215                 compatible = "renesas,i2c-r8a7790";
 216                 reg = <0 0xe6530000 0 0x40>;
 217                 interrupt-parent = <&gic>;
 218                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 219                 status = "disabled";
 220         };
 221
 222         i2c3: i2c@e6540000 {
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 compatible = "renesas,i2c-r8a7790";
 226                 reg = <0 0xe6540000 0 0x40>;
 227                 interrupt-parent = <&gic>;
 228                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 229                 status = "disabled";
 230         };
 231
 232         mmcif0: mmcif@ee200000 {
 233                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 234                 reg = <0 0xee200000 0 0x80>;
 235                 interrupt-parent = <&gic>;
 236                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 237                 reg-io-width = <4>;
 238                 status = "disabled";
 239         };
 240
 241         mmcif1: mmc@ee220000 {
 242                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 243                 reg = <0 0xee220000 0 0x80>;
 244                 interrupt-parent = <&gic>;
 245                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 246                 reg-io-width = <4>;
 247                 status = "disabled";
 248         };
 249
 250         pfc: pfc@e6060000 {
 251                 compatible = "renesas,pfc-r8a7790";
 252                 reg = <0 0xe6060000 0 0x250>;
 253         };
 254
 255         sdhi0: sd@ee100000 {
 256                 compatible = "renesas,sdhi-r8a7790";
 257                 reg = <0 0xee100000 0 0x100>;
 258                 interrupt-parent = <&gic>;
 259                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 260                 cap-sd-highspeed;
 261                 status = "disabled";
 262         };
 263
 264         sdhi1: sd@ee120000 {
 265                 compatible = "renesas,sdhi-r8a7790";
 266                 reg = <0 0xee120000 0 0x100>;
 267                 interrupt-parent = <&gic>;
 268                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 269                 cap-sd-highspeed;
 270                 status = "disabled";
 271         };
 272
 273         sdhi2: sd@ee140000 {
 274                 compatible = "renesas,sdhi-r8a7790";
 275                 reg = <0 0xee140000 0 0x100>;
 276                 interrupt-parent = <&gic>;
 277                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 278                 cap-sd-highspeed;
 279                 status = "disabled";
 280         };
 281
 282         sdhi3: sd@ee160000 {
 283                 compatible = "renesas,sdhi-r8a7790";
 284                 reg = <0 0xee160000 0 0x100>;
 285                 interrupt-parent = <&gic>;
 286                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 287                 cap-sd-highspeed;
 288                 status = "disabled";
 289         };
 290 };