Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/prima2.dtsi

   1 /*
   2  * DTS file for CSR SiRFprimaII SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,prima2";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         reg = <0x0>;
  24                         d-cache-line-size = <32>;
  25                         i-cache-line-size = <32>;
  26                         d-cache-size = <32768>;
  27                         i-cache-size = <32768>;
  28                         /* from bootloader */
  29                         timebase-frequency = <0>;
  30                         bus-frequency = <0>;
  31                         clock-frequency = <0>;
  32                 };
  33         };
  34
  35         axi {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges = <0x40000000 0x40000000 0x80000000>;
  40
  41                 l2-cache-controller@80040000 {
  42                         compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
  43                         reg = <0x80040000 0x1000>;
  44                         interrupts = <59>;
  45                         arm,tag-latency = <1 1 1>;
  46                         arm,data-latency = <1 1 1>;
  47                         arm,filter-ranges = <0 0x40000000>;
  48                 };
  49
  50                 intc: interrupt-controller@80020000 {
  51                         #interrupt-cells = <1>;
  52                         interrupt-controller;
  53                         compatible = "sirf,prima2-intc";
  54                         reg = <0x80020000 0x1000>;
  55                 };
  56
  57                 sys-iobg {
  58                         compatible = "simple-bus";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         ranges = <0x88000000 0x88000000 0x40000>;
  62
  63                         clks: clock-controller@88000000 {
  64                                 compatible = "sirf,prima2-clkc";
  65                                 reg = <0x88000000 0x1000>;
  66                                 interrupts = <3>;
  67                                 #clock-cells = <1>;
  68                         };
  69
  70                         reset-controller@88010000 {
  71                                 compatible = "sirf,prima2-rstc";
  72                                 reg = <0x88010000 0x1000>;
  73                         };
  74
  75                         rsc-controller@88020000 {
  76                                 compatible = "sirf,prima2-rsc";
  77                                 reg = <0x88020000 0x1000>;
  78                         };
  79                 };
  80
  81                 mem-iobg {
  82                         compatible = "simple-bus";
  83                         #address-cells = <1>;
  84                         #size-cells = <1>;
  85                         ranges = <0x90000000 0x90000000 0x10000>;
  86
  87                         memory-controller@90000000 {
  88                                 compatible = "sirf,prima2-memc";
  89                                 reg = <0x90000000 0x10000>;
  90                                 interrupts = <27>;
  91                                 clocks = <&clks 5>;
  92                         };
  93                 };
  94
  95                 disp-iobg {
  96                         compatible = "simple-bus";
  97                         #address-cells = <1>;
  98                         #size-cells = <1>;
  99                         ranges = <0x90010000 0x90010000 0x30000>;
 100
 101                         display@90010000 {
 102                                 compatible = "sirf,prima2-lcd";
 103                                 reg = <0x90010000 0x20000>;
 104                                 interrupts = <30>;
 105                         };
 106
 107                         vpp@90020000 {
 108                                 compatible = "sirf,prima2-vpp";
 109                                 reg = <0x90020000 0x10000>;
 110                                 interrupts = <31>;
 111                                 clocks = <&clks 35>;
 112                         };
 113                 };
 114
 115                 graphics-iobg {
 116                         compatible = "simple-bus";
 117                         #address-cells = <1>;
 118                         #size-cells = <1>;
 119                         ranges = <0x98000000 0x98000000 0x8000000>;
 120
 121                         graphics@98000000 {
 122                                 compatible = "powervr,sgx531";
 123                                 reg = <0x98000000 0x8000000>;
 124                                 interrupts = <6>;
 125                                 clocks = <&clks 32>;
 126                         };
 127                 };
 128
 129                 multimedia-iobg {
 130                         compatible = "simple-bus";
 131                         #address-cells = <1>;
 132                         #size-cells = <1>;
 133                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 134
 135                         multimedia@a0000000 {
 136                                 compatible = "sirf,prima2-video-codec";
 137                                 reg = <0xa0000000 0x8000000>;
 138                                 interrupts = <5>;
 139                                 clocks = <&clks 33>;
 140                         };
 141                 };
 142
 143                 dsp-iobg {
 144                         compatible = "simple-bus";
 145                         #address-cells = <1>;
 146                         #size-cells = <1>;
 147                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 148
 149                         dspif@a8000000 {
 150                                 compatible = "sirf,prima2-dspif";
 151                                 reg = <0xa8000000 0x10000>;
 152                                 interrupts = <9>;
 153                         };
 154
 155                         gps@a8010000 {
 156                                 compatible = "sirf,prima2-gps";
 157                                 reg = <0xa8010000 0x10000>;
 158                                 interrupts = <7>;
 159                                 clocks = <&clks 9>;
 160                         };
 161
 162                         dsp@a9000000 {
 163                                 compatible = "sirf,prima2-dsp";
 164                                 reg = <0xa9000000 0x1000000>;
 165                                 interrupts = <8>;
 166                                 clocks = <&clks 8>;
 167                         };
 168                 };
 169
 170                 peri-iobg {
 171                         compatible = "simple-bus";
 172                         #address-cells = <1>;
 173                         #size-cells = <1>;
 174                         ranges = <0xb0000000 0xb0000000 0x180000>,
 175                                <0x56000000 0x56000000 0x1b00000>;
 176
 177                         timer@b0020000 {
 178                                 compatible = "sirf,prima2-tick";
 179                                 reg = <0xb0020000 0x1000>;
 180                                 interrupts = <0>;
 181                         };
 182
 183                         nand@b0030000 {
 184                                 compatible = "sirf,prima2-nand";
 185                                 reg = <0xb0030000 0x10000>;
 186                                 interrupts = <41>;
 187                                 clocks = <&clks 26>;
 188                         };
 189
 190                         audio@b0040000 {
 191                                 compatible = "sirf,prima2-audio";
 192                                 reg = <0xb0040000 0x10000>;
 193                                 interrupts = <35>;
 194                                 clocks = <&clks 27>;
 195                         };
 196
 197                         uart0: uart@b0050000 {
 198                                 cell-index = <0>;
 199                                 compatible = "sirf,prima2-uart";
 200                                 reg = <0xb0050000 0x1000>;
 201                                 interrupts = <17>;
 202                                 fifosize = <128>;
 203                                 clocks = <&clks 13>;
 204                                 sirf,uart-dma-rx-channel = <21>;
 205                                 sirf,uart-dma-tx-channel = <2>;
 206                         };
 207
 208                         uart1: uart@b0060000 {
 209                                 cell-index = <1>;
 210                                 compatible = "sirf,prima2-uart";
 211                                 reg = <0xb0060000 0x1000>;
 212                                 interrupts = <18>;
 213                                 fifosize = <32>;
 214                                 clocks = <&clks 14>;
 215                         };
 216
 217                         uart2: uart@b0070000 {
 218                                 cell-index = <2>;
 219                                 compatible = "sirf,prima2-uart";
 220                                 reg = <0xb0070000 0x1000>;
 221                                 interrupts = <19>;
 222                                 fifosize = <128>;
 223                                 clocks = <&clks 15>;
 224                                 sirf,uart-dma-rx-channel = <6>;
 225                                 sirf,uart-dma-tx-channel = <7>;
 226                         };
 227
 228                         usp0: usp@b0080000 {
 229                                 cell-index = <0>;
 230                                 compatible = "sirf,prima2-usp";
 231                                 reg = <0xb0080000 0x10000>;
 232                                 interrupts = <20>;
 233                                 fifosize = <128>;
 234                                 clocks = <&clks 28>;
 235                                 sirf,usp-dma-rx-channel = <17>;
 236                                 sirf,usp-dma-tx-channel = <18>;
 237                         };
 238
 239                         usp1: usp@b0090000 {
 240                                 cell-index = <1>;
 241                                 compatible = "sirf,prima2-usp";
 242                                 reg = <0xb0090000 0x10000>;
 243                                 interrupts = <21>;
 244                                 fifosize = <128>;
 245                                 clocks = <&clks 29>;
 246                                 sirf,usp-dma-rx-channel = <14>;
 247                                 sirf,usp-dma-tx-channel = <15>;
 248                         };
 249
 250                         usp2: usp@b00a0000 {
 251                                 cell-index = <2>;
 252                                 compatible = "sirf,prima2-usp";
 253                                 reg = <0xb00a0000 0x10000>;
 254                                 interrupts = <22>;
 255                                 fifosize = <128>;
 256                                 clocks = <&clks 30>;
 257                                 sirf,usp-dma-rx-channel = <10>;
 258                                 sirf,usp-dma-tx-channel = <11>;
 259                         };
 260
 261                         dmac0: dma-controller@b00b0000 {
 262                                 cell-index = <0>;
 263                                 compatible = "sirf,prima2-dmac";
 264                                 reg = <0xb00b0000 0x10000>;
 265                                 interrupts = <12>;
 266                                 clocks = <&clks 24>;
 267                         };
 268
 269                         dmac1: dma-controller@b0160000 {
 270                                 cell-index = <1>;
 271                                 compatible = "sirf,prima2-dmac";
 272                                 reg = <0xb0160000 0x10000>;
 273                                 interrupts = <13>;
 274                                 clocks = <&clks 25>;
 275                         };
 276
 277                         vip@b00C0000 {
 278                                 compatible = "sirf,prima2-vip";
 279                                 reg = <0xb00C0000 0x10000>;
 280                                 clocks = <&clks 31>;
 281                         };
 282
 283                         spi0: spi@b00d0000 {
 284                                 cell-index = <0>;
 285                                 compatible = "sirf,prima2-spi";
 286                                 reg = <0xb00d0000 0x10000>;
 287                                 interrupts = <15>;
 288                                 clocks = <&clks 19>;
 289                         };
 290
 291                         spi1: spi@b0170000 {
 292                                 cell-index = <1>;
 293                                 compatible = "sirf,prima2-spi";
 294                                 reg = <0xb0170000 0x10000>;
 295                                 interrupts = <16>;
 296                                 clocks = <&clks 20>;
 297                         };
 298
 299                         i2c0: i2c@b00e0000 {
 300                                 cell-index = <0>;
 301                                 compatible = "sirf,prima2-i2c";
 302                                 reg = <0xb00e0000 0x10000>;
 303                                 interrupts = <24>;
 304                                 clocks = <&clks 17>;
 305                         };
 306
 307                         i2c1: i2c@b00f0000 {
 308                                 cell-index = <1>;
 309                                 compatible = "sirf,prima2-i2c";
 310                                 reg = <0xb00f0000 0x10000>;
 311                                 interrupts = <25>;
 312                                 clocks = <&clks 18>;
 313                         };
 314
 315                         tsc@b0110000 {
 316                                 compatible = "sirf,prima2-tsc";
 317                                 reg = <0xb0110000 0x10000>;
 318                                 interrupts = <33>;
 319                                 clocks = <&clks 16>;
 320                         };
 321
 322                         gpio: pinctrl@b0120000 {
 323                                 #gpio-cells = <2>;
 324                                 #interrupt-cells = <2>;
 325                                 compatible = "sirf,prima2-pinctrl";
 326                                 reg = <0xb0120000 0x10000>;
 327                                 interrupts = <43 44 45 46 47>;
 328                                 gpio-controller;
 329                                 interrupt-controller;
 330
 331                                 lcd_16pins_a: lcd0@0 {
 332                                         lcd {
 333                                                 sirf,pins = "lcd_16bitsgrp";
 334                                                 sirf,function = "lcd_16bits";
 335                                         };
 336                                 };
 337                                 lcd_18pins_a: lcd0@1 {
 338                                         lcd {
 339                                                 sirf,pins = "lcd_18bitsgrp";
 340                                                 sirf,function = "lcd_18bits";
 341                                         };
 342                                 };
 343                                 lcd_24pins_a: lcd0@2 {
 344                                         lcd {
 345                                                 sirf,pins = "lcd_24bitsgrp";
 346                                                 sirf,function = "lcd_24bits";
 347                                         };
 348                                 };
 349                                 lcdrom_pins_a: lcdrom0@0 {
 350                                         lcd {
 351                                                 sirf,pins = "lcdromgrp";
 352                                                 sirf,function = "lcdrom";
 353                                         };
 354                                 };
 355                                 uart0_pins_a: uart0@0 {
 356                                         uart {
 357                                                 sirf,pins = "uart0grp";
 358                                                 sirf,function = "uart0";
 359                                         };
 360                                 };
 361                                 uart1_pins_a: uart1@0 {
 362                                         uart {
 363                                                 sirf,pins = "uart1grp";
 364                                                 sirf,function = "uart1";
 365                                         };
 366                                 };
 367                                 uart2_pins_a: uart2@0 {
 368                                         uart {
 369                                                 sirf,pins = "uart2grp";
 370                                                 sirf,function = "uart2";
 371                                         };
 372                                 };
 373                                 uart2_noflow_pins_a: uart2@1 {
 374                                         uart {
 375                                                 sirf,pins = "uart2_nostreamctrlgrp";
 376                                                 sirf,function = "uart2_nostreamctrl";
 377                                         };
 378                                 };
 379                                 spi0_pins_a: spi0@0 {
 380                                         spi {
 381                                                 sirf,pins = "spi0grp";
 382                                                 sirf,function = "spi0";
 383                                         };
 384                                 };
 385                                 spi1_pins_a: spi1@0 {
 386                                         spi {
 387                                                 sirf,pins = "spi1grp";
 388                                                 sirf,function = "spi1";
 389                                         };
 390                                 };
 391                                 i2c0_pins_a: i2c0@0 {
 392                                         i2c {
 393                                                 sirf,pins = "i2c0grp";
 394                                                 sirf,function = "i2c0";
 395                                         };
 396                                 };
 397                                 i2c1_pins_a: i2c1@0 {
 398                                         i2c {
 399                                                 sirf,pins = "i2c1grp";
 400                                                 sirf,function = "i2c1";
 401                                         };
 402                                 };
 403                                 pwm0_pins_a: pwm0@0 {
 404                                         pwm {
 405                                                 sirf,pins = "pwm0grp";
 406                                                 sirf,function = "pwm0";
 407                                         };
 408                                 };
 409                                 pwm1_pins_a: pwm1@0 {
 410                                         pwm {
 411                                                 sirf,pins = "pwm1grp";
 412                                                 sirf,function = "pwm1";
 413                                         };
 414                                 };
 415                                 pwm2_pins_a: pwm2@0 {
 416                                         pwm {
 417                                                 sirf,pins = "pwm2grp";
 418                                                 sirf,function = "pwm2";
 419                                         };
 420                                 };
 421                                 pwm3_pins_a: pwm3@0 {
 422                                         pwm {
 423                                                 sirf,pins = "pwm3grp";
 424                                                 sirf,function = "pwm3";
 425                                         };
 426                                 };
 427                                 gps_pins_a: gps@0 {
 428                                         gps {
 429                                                 sirf,pins = "gpsgrp";
 430                                                 sirf,function = "gps";
 431                                         };
 432                                 };
 433                                 vip_pins_a: vip@0 {
 434                                         vip {
 435                                                 sirf,pins = "vipgrp";
 436                                                 sirf,function = "vip";
 437                                         };
 438                                 };
 439                                 sdmmc0_pins_a: sdmmc0@0 {
 440                                         sdmmc0 {
 441                                                 sirf,pins = "sdmmc0grp";
 442                                                 sirf,function = "sdmmc0";
 443                                         };
 444                                 };
 445                                 sdmmc1_pins_a: sdmmc1@0 {
 446                                         sdmmc1 {
 447                                                 sirf,pins = "sdmmc1grp";
 448                                                 sirf,function = "sdmmc1";
 449                                         };
 450                                 };
 451                                 sdmmc2_pins_a: sdmmc2@0 {
 452                                         sdmmc2 {
 453                                                 sirf,pins = "sdmmc2grp";
 454                                                 sirf,function = "sdmmc2";
 455                                         };
 456                                 };
 457                                 sdmmc3_pins_a: sdmmc3@0 {
 458                                         sdmmc3 {
 459                                                 sirf,pins = "sdmmc3grp";
 460                                                 sirf,function = "sdmmc3";
 461                                         };
 462                                 };
 463                                 sdmmc4_pins_a: sdmmc4@0 {
 464                                         sdmmc4 {
 465                                                 sirf,pins = "sdmmc4grp";
 466                                                 sirf,function = "sdmmc4";
 467                                         };
 468                                 };
 469                                 sdmmc5_pins_a: sdmmc5@0 {
 470                                         sdmmc5 {
 471                                                 sirf,pins = "sdmmc5grp";
 472                                                 sirf,function = "sdmmc5";
 473                                         };
 474                                 };
 475                                 i2s_pins_a: i2s@0 {
 476                                         i2s {
 477                                                 sirf,pins = "i2sgrp";
 478                                                 sirf,function = "i2s";
 479                                         };
 480                                 };
 481                                 ac97_pins_a: ac97@0 {
 482                                         ac97 {
 483                                                 sirf,pins = "ac97grp";
 484                                                 sirf,function = "ac97";
 485                                         };
 486                                 };
 487                                 nand_pins_a: nand@0 {
 488                                         nand {
 489                                                 sirf,pins = "nandgrp";
 490                                                 sirf,function = "nand";
 491                                         };
 492                                 };
 493                                 usp0_pins_a: usp0@0 {
 494                                         usp0 {
 495                                                 sirf,pins = "usp0grp";
 496                                                 sirf,function = "usp0";
 497                                         };
 498                                 };
 499                                 usp1_pins_a: usp1@0 {
 500                                         usp1 {
 501                                                 sirf,pins = "usp1grp";
 502                                                 sirf,function = "usp1";
 503                                         };
 504                                 };
 505                                 usp2_pins_a: usp2@0 {
 506                                         usp2 {
 507                                                 sirf,pins = "usp2grp";
 508                                                 sirf,function = "usp2";
 509                                         };
 510                                 };
 511                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
 512                                         usb0_utmi_drvbus {
 513                                                 sirf,pins = "usb0_utmi_drvbusgrp";
 514                                                 sirf,function = "usb0_utmi_drvbus";
 515                                         };
 516                                 };
 517                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 518                                         usb1_utmi_drvbus {
 519                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 520                                                 sirf,function = "usb1_utmi_drvbus";
 521                                         };
 522                                 };
 523                                 warm_rst_pins_a: warm_rst@0 {
 524                                         warm_rst {
 525                                                 sirf,pins = "warm_rstgrp";
 526                                                 sirf,function = "warm_rst";
 527                                         };
 528                                 };
 529                                 pulse_count_pins_a: pulse_count@0 {
 530                                         pulse_count {
 531                                                 sirf,pins = "pulse_countgrp";
 532                                                 sirf,function = "pulse_count";
 533                                         };
 534                                 };
 535                                 cko0_pins_a: cko0@0 {
 536                                         cko0 {
 537                                                 sirf,pins = "cko0grp";
 538                                                 sirf,function = "cko0";
 539                                         };
 540                                 };
 541                                 cko1_pins_a: cko1@0 {
 542                                         cko1 {
 543                                                 sirf,pins = "cko1grp";
 544                                                 sirf,function = "cko1";
 545                                         };
 546                                 };
 547                         };
 548
 549                         pwm@b0130000 {
 550                                 compatible = "sirf,prima2-pwm";
 551                                 reg = <0xb0130000 0x10000>;
 552                                 clocks = <&clks 21>;
 553                         };
 554
 555                         efusesys@b0140000 {
 556                                 compatible = "sirf,prima2-efuse";
 557                                 reg = <0xb0140000 0x10000>;
 558                                 clocks = <&clks 22>;
 559                         };
 560
 561                         pulsec@b0150000 {
 562                                 compatible = "sirf,prima2-pulsec";
 563                                 reg = <0xb0150000 0x10000>;
 564                                 interrupts = <48>;
 565                                 clocks = <&clks 23>;
 566                         };
 567
 568                         pci-iobg {
 569                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 570                                 #address-cells = <1>;
 571                                 #size-cells = <1>;
 572                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 573
 574                                 sd0: sdhci@56000000 {
 575                                         cell-index = <0>;
 576                                         compatible = "sirf,prima2-sdhc";
 577                                         reg = <0x56000000 0x100000>;
 578                                         interrupts = <38>;
 579                                 };
 580
 581                                 sd1: sdhci@56100000 {
 582                                         cell-index = <1>;
 583                                         compatible = "sirf,prima2-sdhc";
 584                                         reg = <0x56100000 0x100000>;
 585                                         interrupts = <38>;
 586                                 };
 587
 588                                 sd2: sdhci@56200000 {
 589                                         cell-index = <2>;
 590                                         compatible = "sirf,prima2-sdhc";
 591                                         reg = <0x56200000 0x100000>;
 592                                         interrupts = <23>;
 593                                 };
 594
 595                                 sd3: sdhci@56300000 {
 596                                         cell-index = <3>;
 597                                         compatible = "sirf,prima2-sdhc";
 598                                         reg = <0x56300000 0x100000>;
 599                                         interrupts = <23>;
 600                                 };
 601
 602                                 sd4: sdhci@56400000 {
 603                                         cell-index = <4>;
 604                                         compatible = "sirf,prima2-sdhc";
 605                                         reg = <0x56400000 0x100000>;
 606                                         interrupts = <39>;
 607                                 };
 608
 609                                 sd5: sdhci@56500000 {
 610                                         cell-index = <5>;
 611                                         compatible = "sirf,prima2-sdhc";
 612                                         reg = <0x56500000 0x100000>;
 613                                         interrupts = <39>;
 614                                 };
 615
 616                                 pci-copy@57900000 {
 617                                         compatible = "sirf,prima2-pcicp";
 618                                         reg = <0x57900000 0x100000>;
 619                                         interrupts = <40>;
 620                                 };
 621
 622                                 rom-interface@57a00000 {
 623                                         compatible = "sirf,prima2-romif";
 624                                         reg = <0x57a00000 0x100000>;
 625                                 };
 626                         };
 627                 };
 628
 629                 rtc-iobg {
 630                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 631                         #address-cells = <1>;
 632                         #size-cells = <1>;
 633                         reg = <0x80030000 0x10000>;
 634
 635                         gpsrtc@1000 {
 636                                 compatible = "sirf,prima2-gpsrtc";
 637                                 reg = <0x1000 0x1000>;
 638                                 interrupts = <55 56 57>;
 639                         };
 640
 641                         sysrtc@2000 {
 642                                 compatible = "sirf,prima2-sysrtc";
 643                                 reg = <0x2000 0x1000>;
 644                                 interrupts = <52 53 54>;
 645                         };
 646
 647                         pwrc@3000 {
 648                                 compatible = "sirf,prima2-pwrc";
 649                                 reg = <0x3000 0x1000>;
 650                                 interrupts = <32>;
 651                         };
 652                 };
 653
 654                 uus-iobg {
 655                         compatible = "simple-bus";
 656                         #address-cells = <1>;
 657                         #size-cells = <1>;
 658                         ranges = <0xb8000000 0xb8000000 0x40000>;
 659
 660                         usb0: usb@b00e0000 {
 661                                 compatible = "chipidea,ci13611a-prima2";
 662                                 reg = <0xb8000000 0x10000>;
 663                                 interrupts = <10>;
 664                                 clocks = <&clks 40>;
 665                         };
 666
 667                         usb1: usb@b00f0000 {
 668                                 compatible = "chipidea,ci13611a-prima2";
 669                                 reg = <0xb8010000 0x10000>;
 670                                 interrupts = <11>;
 671                                 clocks = <&clks 41>;
 672                         };
 673
 674                         sata@b00f0000 {
 675                                 compatible = "synopsys,dwc-ahsata";
 676                                 reg = <0xb8020000 0x10000>;
 677                                 interrupts = <37>;
 678                         };
 679
 680                         security@b00f0000 {
 681                                 compatible = "sirf,prima2-security";
 682                                 reg = <0xb8030000 0x10000>;
 683                                 interrupts = <42>;
 684                                 clocks = <&clks 7>;
 685                         };
 686                 };
 687         };
 688 };