Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/prima2.dtsi

   1 /*
   2  * DTS file for CSR SiRFprimaII SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,prima2";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         reg = <0x0>;
  24                         d-cache-line-size = <32>;
  25                         i-cache-line-size = <32>;
  26                         d-cache-size = <32768>;
  27                         i-cache-size = <32768>;
  28                         /* from bootloader */
  29                         timebase-frequency = <0>;
  30                         bus-frequency = <0>;
  31                         clock-frequency = <0>;
  32                         clocks = <&clks 12>;
  33                         operating-points = <
  34                                 /* kHz    uV */
  35                                 200000  1025000
  36                                 400000  1025000
  37                                 664000  1050000
  38                                 800000  1100000
  39                         >;
  40                         clock-latency = <150000>;
  41                 };
  42         };
  43
  44         axi {
  45                 compatible = "simple-bus";
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 ranges = <0x40000000 0x40000000 0x80000000>;
  49
  50                 l2-cache-controller@80040000 {
  51                         compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
  52                         reg = <0x80040000 0x1000>;
  53                         interrupts = <59>;
  54                         arm,tag-latency = <1 1 1>;
  55                         arm,data-latency = <1 1 1>;
  56                         arm,filter-ranges = <0 0x40000000>;
  57                 };
  58
  59                 intc: interrupt-controller@80020000 {
  60                         #interrupt-cells = <1>;
  61                         interrupt-controller;
  62                         compatible = "sirf,prima2-intc";
  63                         reg = <0x80020000 0x1000>;
  64                 };
  65
  66                 sys-iobg {
  67                         compatible = "simple-bus";
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         ranges = <0x88000000 0x88000000 0x40000>;
  71
  72                         clks: clock-controller@88000000 {
  73                                 compatible = "sirf,prima2-clkc";
  74                                 reg = <0x88000000 0x1000>;
  75                                 interrupts = <3>;
  76                                 #clock-cells = <1>;
  77                         };
  78
  79                         reset-controller@88010000 {
  80                                 compatible = "sirf,prima2-rstc";
  81                                 reg = <0x88010000 0x1000>;
  82                         };
  83
  84                         rsc-controller@88020000 {
  85                                 compatible = "sirf,prima2-rsc";
  86                                 reg = <0x88020000 0x1000>;
  87                         };
  88
  89                         cphifbg@88030000 {
  90                                 compatible = "sirf,prima2-cphifbg";
  91                                 reg = <0x88030000 0x1000>;
  92                                 clocks = <&clks 42>;
  93                         };
  94                 };
  95
  96                 mem-iobg {
  97                         compatible = "simple-bus";
  98                         #address-cells = <1>;
  99                         #size-cells = <1>;
 100                         ranges = <0x90000000 0x90000000 0x10000>;
 101
 102                         memory-controller@90000000 {
 103                                 compatible = "sirf,prima2-memc";
 104                                 reg = <0x90000000 0x2000>;
 105                                 interrupts = <27>;
 106                                 clocks = <&clks 5>;
 107                         };
 108
 109                         memc-monitor {
 110                                 compatible = "sirf,prima2-memcmon";
 111                                 reg = <0x90002000 0x200>;
 112                                 interrupts = <4>;
 113                                 clocks = <&clks 32>;
 114                         };
 115                 };
 116
 117                 disp-iobg {
 118                         compatible = "simple-bus";
 119                         #address-cells = <1>;
 120                         #size-cells = <1>;
 121                         ranges = <0x90010000 0x90010000 0x30000>;
 122
 123                         display@90010000 {
 124                                 compatible = "sirf,prima2-lcd";
 125                                 reg = <0x90010000 0x20000>;
 126                                 interrupts = <30>;
 127                         };
 128
 129                         vpp@90020000 {
 130                                 compatible = "sirf,prima2-vpp";
 131                                 reg = <0x90020000 0x10000>;
 132                                 interrupts = <31>;
 133                                 clocks = <&clks 35>;
 134                         };
 135                 };
 136
 137                 graphics-iobg {
 138                         compatible = "simple-bus";
 139                         #address-cells = <1>;
 140                         #size-cells = <1>;
 141                         ranges = <0x98000000 0x98000000 0x8000000>;
 142
 143                         graphics@98000000 {
 144                                 compatible = "powervr,sgx531";
 145                                 reg = <0x98000000 0x8000000>;
 146                                 interrupts = <6>;
 147                                 clocks = <&clks 32>;
 148                         };
 149                 };
 150
 151                 multimedia-iobg {
 152                         compatible = "simple-bus";
 153                         #address-cells = <1>;
 154                         #size-cells = <1>;
 155                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 156
 157                         multimedia@a0000000 {
 158                                 compatible = "sirf,prima2-video-codec";
 159                                 reg = <0xa0000000 0x8000000>;
 160                                 interrupts = <5>;
 161                                 clocks = <&clks 33>;
 162                         };
 163                 };
 164
 165                 dsp-iobg {
 166                         compatible = "simple-bus";
 167                         #address-cells = <1>;
 168                         #size-cells = <1>;
 169                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 170
 171                         dspif@a8000000 {
 172                                 compatible = "sirf,prima2-dspif";
 173                                 reg = <0xa8000000 0x10000>;
 174                                 interrupts = <9>;
 175                         };
 176
 177                         gps@a8010000 {
 178                                 compatible = "sirf,prima2-gps";
 179                                 reg = <0xa8010000 0x10000>;
 180                                 interrupts = <7>;
 181                                 clocks = <&clks 9>;
 182                         };
 183
 184                         dsp@a9000000 {
 185                                 compatible = "sirf,prima2-dsp";
 186                                 reg = <0xa9000000 0x1000000>;
 187                                 interrupts = <8>;
 188                                 clocks = <&clks 8>;
 189                         };
 190                 };
 191
 192                 peri-iobg {
 193                         compatible = "simple-bus";
 194                         #address-cells = <1>;
 195                         #size-cells = <1>;
 196                         ranges = <0xb0000000 0xb0000000 0x180000>,
 197                                <0x56000000 0x56000000 0x1b00000>;
 198
 199                         timer@b0020000 {
 200                                 compatible = "sirf,prima2-tick";
 201                                 reg = <0xb0020000 0x1000>;
 202                                 interrupts = <0>;
 203                         };
 204
 205                         nand@b0030000 {
 206                                 compatible = "sirf,prima2-nand";
 207                                 reg = <0xb0030000 0x10000>;
 208                                 interrupts = <41>;
 209                                 clocks = <&clks 26>;
 210                         };
 211
 212                         audio@b0040000 {
 213                                 compatible = "sirf,prima2-audio";
 214                                 reg = <0xb0040000 0x10000>;
 215                                 interrupts = <35>;
 216                                 clocks = <&clks 27>;
 217                         };
 218
 219                         uart0: uart@b0050000 {
 220                                 cell-index = <0>;
 221                                 compatible = "sirf,prima2-uart";
 222                                 reg = <0xb0050000 0x1000>;
 223                                 interrupts = <17>;
 224                                 fifosize = <128>;
 225                                 clocks = <&clks 13>;
 226                                 sirf,uart-dma-rx-channel = <21>;
 227                                 sirf,uart-dma-tx-channel = <2>;
 228                         };
 229
 230                         uart1: uart@b0060000 {
 231                                 cell-index = <1>;
 232                                 compatible = "sirf,prima2-uart";
 233                                 reg = <0xb0060000 0x1000>;
 234                                 interrupts = <18>;
 235                                 fifosize = <32>;
 236                                 clocks = <&clks 14>;
 237                         };
 238
 239                         uart2: uart@b0070000 {
 240                                 cell-index = <2>;
 241                                 compatible = "sirf,prima2-uart";
 242                                 reg = <0xb0070000 0x1000>;
 243                                 interrupts = <19>;
 244                                 fifosize = <128>;
 245                                 clocks = <&clks 15>;
 246                                 sirf,uart-dma-rx-channel = <6>;
 247                                 sirf,uart-dma-tx-channel = <7>;
 248                         };
 249
 250                         usp0: usp@b0080000 {
 251                                 cell-index = <0>;
 252                                 compatible = "sirf,prima2-usp";
 253                                 reg = <0xb0080000 0x10000>;
 254                                 interrupts = <20>;
 255                                 fifosize = <128>;
 256                                 clocks = <&clks 28>;
 257                                 sirf,usp-dma-rx-channel = <17>;
 258                                 sirf,usp-dma-tx-channel = <18>;
 259                         };
 260
 261                         usp1: usp@b0090000 {
 262                                 cell-index = <1>;
 263                                 compatible = "sirf,prima2-usp";
 264                                 reg = <0xb0090000 0x10000>;
 265                                 interrupts = <21>;
 266                                 fifosize = <128>;
 267                                 clocks = <&clks 29>;
 268                                 sirf,usp-dma-rx-channel = <14>;
 269                                 sirf,usp-dma-tx-channel = <15>;
 270                         };
 271
 272                         usp2: usp@b00a0000 {
 273                                 cell-index = <2>;
 274                                 compatible = "sirf,prima2-usp";
 275                                 reg = <0xb00a0000 0x10000>;
 276                                 interrupts = <22>;
 277                                 fifosize = <128>;
 278                                 clocks = <&clks 30>;
 279                                 sirf,usp-dma-rx-channel = <10>;
 280                                 sirf,usp-dma-tx-channel = <11>;
 281                         };
 282
 283                         dmac0: dma-controller@b00b0000 {
 284                                 cell-index = <0>;
 285                                 compatible = "sirf,prima2-dmac";
 286                                 reg = <0xb00b0000 0x10000>;
 287                                 interrupts = <12>;
 288                                 clocks = <&clks 24>;
 289                         };
 290
 291                         dmac1: dma-controller@b0160000 {
 292                                 cell-index = <1>;
 293                                 compatible = "sirf,prima2-dmac";
 294                                 reg = <0xb0160000 0x10000>;
 295                                 interrupts = <13>;
 296                                 clocks = <&clks 25>;
 297                         };
 298
 299                         vip@b00C0000 {
 300                                 compatible = "sirf,prima2-vip";
 301                                 reg = <0xb00C0000 0x10000>;
 302                                 clocks = <&clks 31>;
 303                                 interrupts = <14>;
 304                                 sirf,vip-dma-rx-channel = <16>;
 305                         };
 306
 307                         spi0: spi@b00d0000 {
 308                                 cell-index = <0>;
 309                                 compatible = "sirf,prima2-spi";
 310                                 reg = <0xb00d0000 0x10000>;
 311                                 interrupts = <15>;
 312                                 sirf,spi-num-chipselects = <1>;
 313                                 sirf,spi-dma-rx-channel = <25>;
 314                                 sirf,spi-dma-tx-channel = <20>;
 315                                 #address-cells = <1>;
 316                                 #size-cells = <0>;
 317                                 clocks = <&clks 19>;
 318                                 status = "disabled";
 319                         };
 320
 321                         spi1: spi@b0170000 {
 322                                 cell-index = <1>;
 323                                 compatible = "sirf,prima2-spi";
 324                                 reg = <0xb0170000 0x10000>;
 325                                 interrupts = <16>;
 326                                 sirf,spi-num-chipselects = <1>;
 327                                 sirf,spi-dma-rx-channel = <12>;
 328                                 sirf,spi-dma-tx-channel = <13>;
 329                                 #address-cells = <1>;
 330                                 #size-cells = <0>;
 331                                 clocks = <&clks 20>;
 332                                 status = "disabled";
 333                         };
 334
 335                         i2c0: i2c@b00e0000 {
 336                                 cell-index = <0>;
 337                                 compatible = "sirf,prima2-i2c";
 338                                 reg = <0xb00e0000 0x10000>;
 339                                 interrupts = <24>;
 340                                 clocks = <&clks 17>;
 341                                 #address-cells = <1>;
 342                                 #size-cells = <0>;
 343                         };
 344
 345                         i2c1: i2c@b00f0000 {
 346                                 cell-index = <1>;
 347                                 compatible = "sirf,prima2-i2c";
 348                                 reg = <0xb00f0000 0x10000>;
 349                                 interrupts = <25>;
 350                                 clocks = <&clks 18>;
 351                                 #address-cells = <1>;
 352                                 #size-cells = <0>;
 353                         };
 354
 355                         tsc@b0110000 {
 356                                 compatible = "sirf,prima2-tsc";
 357                                 reg = <0xb0110000 0x10000>;
 358                                 interrupts = <33>;
 359                                 clocks = <&clks 16>;
 360                         };
 361
 362                         gpio: pinctrl@b0120000 {
 363                                 #gpio-cells = <2>;
 364                                 #interrupt-cells = <2>;
 365                                 compatible = "sirf,prima2-pinctrl";
 366                                 reg = <0xb0120000 0x10000>;
 367                                 interrupts = <43 44 45 46 47>;
 368                                 gpio-controller;
 369                                 interrupt-controller;
 370
 371                                 lcd_16pins_a: lcd0@0 {
 372                                         lcd {
 373                                                 sirf,pins = "lcd_16bitsgrp";
 374                                                 sirf,function = "lcd_16bits";
 375                                         };
 376                                 };
 377                                 lcd_18pins_a: lcd0@1 {
 378                                         lcd {
 379                                                 sirf,pins = "lcd_18bitsgrp";
 380                                                 sirf,function = "lcd_18bits";
 381                                         };
 382                                 };
 383                                 lcd_24pins_a: lcd0@2 {
 384                                         lcd {
 385                                                 sirf,pins = "lcd_24bitsgrp";
 386                                                 sirf,function = "lcd_24bits";
 387                                         };
 388                                 };
 389                                 lcdrom_pins_a: lcdrom0@0 {
 390                                         lcd {
 391                                                 sirf,pins = "lcdromgrp";
 392                                                 sirf,function = "lcdrom";
 393                                         };
 394                                 };
 395                                 uart0_pins_a: uart0@0 {
 396                                         uart {
 397                                                 sirf,pins = "uart0grp";
 398                                                 sirf,function = "uart0";
 399                                         };
 400                                 };
 401                                 uart0_noflow_pins_a: uart0@1 {
 402                                         uart {
 403                                                 sirf,pins = "uart0_nostreamctrlgrp";
 404                                                 sirf,function = "uart0_nostreamctrl";
 405                                         };
 406                                 };
 407                                 uart1_pins_a: uart1@0 {
 408                                         uart {
 409                                                 sirf,pins = "uart1grp";
 410                                                 sirf,function = "uart1";
 411                                         };
 412                                 };
 413                                 uart2_pins_a: uart2@0 {
 414                                         uart {
 415                                                 sirf,pins = "uart2grp";
 416                                                 sirf,function = "uart2";
 417                                         };
 418                                 };
 419                                 uart2_noflow_pins_a: uart2@1 {
 420                                         uart {
 421                                                 sirf,pins = "uart2_nostreamctrlgrp";
 422                                                 sirf,function = "uart2_nostreamctrl";
 423                                         };
 424                                 };
 425                                 spi0_pins_a: spi0@0 {
 426                                         spi {
 427                                                 sirf,pins = "spi0grp";
 428                                                 sirf,function = "spi0";
 429                                         };
 430                                 };
 431                                 spi1_pins_a: spi1@0 {
 432                                         spi {
 433                                                 sirf,pins = "spi1grp";
 434                                                 sirf,function = "spi1";
 435                                         };
 436                                 };
 437                                 i2c0_pins_a: i2c0@0 {
 438                                         i2c {
 439                                                 sirf,pins = "i2c0grp";
 440                                                 sirf,function = "i2c0";
 441                                         };
 442                                 };
 443                                 i2c1_pins_a: i2c1@0 {
 444                                         i2c {
 445                                                 sirf,pins = "i2c1grp";
 446                                                 sirf,function = "i2c1";
 447                                         };
 448                                 };
 449                                 pwm0_pins_a: pwm0@0 {
 450                                         pwm {
 451                                                 sirf,pins = "pwm0grp";
 452                                                 sirf,function = "pwm0";
 453                                         };
 454                                 };
 455                                 pwm1_pins_a: pwm1@0 {
 456                                         pwm {
 457                                                 sirf,pins = "pwm1grp";
 458                                                 sirf,function = "pwm1";
 459                                         };
 460                                 };
 461                                 pwm2_pins_a: pwm2@0 {
 462                                         pwm {
 463                                                 sirf,pins = "pwm2grp";
 464                                                 sirf,function = "pwm2";
 465                                         };
 466                                 };
 467                                 pwm3_pins_a: pwm3@0 {
 468                                         pwm {
 469                                                 sirf,pins = "pwm3grp";
 470                                                 sirf,function = "pwm3";
 471                                         };
 472                                 };
 473                                 gps_pins_a: gps@0 {
 474                                         gps {
 475                                                 sirf,pins = "gpsgrp";
 476                                                 sirf,function = "gps";
 477                                         };
 478                                 };
 479                                 vip_pins_a: vip@0 {
 480                                         vip {
 481                                                 sirf,pins = "vipgrp";
 482                                                 sirf,function = "vip";
 483                                         };
 484                                 };
 485                                 sdmmc0_pins_a: sdmmc0@0 {
 486                                         sdmmc0 {
 487                                                 sirf,pins = "sdmmc0grp";
 488                                                 sirf,function = "sdmmc0";
 489                                         };
 490                                 };
 491                                 sdmmc1_pins_a: sdmmc1@0 {
 492                                         sdmmc1 {
 493                                                 sirf,pins = "sdmmc1grp";
 494                                                 sirf,function = "sdmmc1";
 495                                         };
 496                                 };
 497                                 sdmmc2_pins_a: sdmmc2@0 {
 498                                         sdmmc2 {
 499                                                 sirf,pins = "sdmmc2grp";
 500                                                 sirf,function = "sdmmc2";
 501                                         };
 502                                 };
 503                                 sdmmc3_pins_a: sdmmc3@0 {
 504                                         sdmmc3 {
 505                                                 sirf,pins = "sdmmc3grp";
 506                                                 sirf,function = "sdmmc3";
 507                                         };
 508                                 };
 509                                 sdmmc4_pins_a: sdmmc4@0 {
 510                                         sdmmc4 {
 511                                                 sirf,pins = "sdmmc4grp";
 512                                                 sirf,function = "sdmmc4";
 513                                         };
 514                                 };
 515                                 sdmmc5_pins_a: sdmmc5@0 {
 516                                         sdmmc5 {
 517                                                 sirf,pins = "sdmmc5grp";
 518                                                 sirf,function = "sdmmc5";
 519                                         };
 520                                 };
 521                                 i2s_pins_a: i2s@0 {
 522                                         i2s {
 523                                                 sirf,pins = "i2sgrp";
 524                                                 sirf,function = "i2s";
 525                                         };
 526                                 };
 527                                 ac97_pins_a: ac97@0 {
 528                                         ac97 {
 529                                                 sirf,pins = "ac97grp";
 530                                                 sirf,function = "ac97";
 531                                         };
 532                                 };
 533                                 nand_pins_a: nand@0 {
 534                                         nand {
 535                                                 sirf,pins = "nandgrp";
 536                                                 sirf,function = "nand";
 537                                         };
 538                                 };
 539                                 usp0_pins_a: usp0@0 {
 540                                         usp0 {
 541                                                 sirf,pins = "usp0grp";
 542                                                 sirf,function = "usp0";
 543                                         };
 544                                 };
 545                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 546                                         usp0 {
 547                                                 sirf,pins =
 548                                                         "usp0_uart_nostreamctrl_grp";
 549                                                 sirf,function =
 550                                                         "usp0_uart_nostreamctrl";
 551                                         };
 552                                 };
 553                                 usp0_only_utfs_pins_a: usp0@2 {
 554                                         usp0 {
 555                                                 sirf,pins = "usp0_only_utfs_grp";
 556                                                 sirf,function = "usp0_only_utfs";
 557                                         };
 558                                 };
 559                                 usp0_only_urfs_pins_a: usp0@3 {
 560                                         usp0 {
 561                                                 sirf,pins = "usp0_only_urfs_grp";
 562                                                 sirf,function = "usp0_only_urfs";
 563                                         };
 564                                 };
 565                                 usp1_pins_a: usp1@0 {
 566                                         usp1 {
 567                                                 sirf,pins = "usp1grp";
 568                                                 sirf,function = "usp1";
 569                                         };
 570                                 };
 571                                 usp1_uart_nostreamctrl_pins_a: usp1@1 {
 572                                         usp1 {
 573                                                 sirf,pins =
 574                                                         "usp1_uart_nostreamctrl_grp";
 575                                                 sirf,function =
 576                                                         "usp1_uart_nostreamctrl";
 577                                         };
 578                                 };
 579                                 usp2_pins_a: usp2@0 {
 580                                         usp2 {
 581                                                 sirf,pins = "usp2grp";
 582                                                 sirf,function = "usp2";
 583                                         };
 584                                 };
 585                                 usp2_uart_nostreamctrl_pins_a: usp2@1 {
 586                                         usp2 {
 587                                                 sirf,pins =
 588                                                         "usp2_uart_nostreamctrl_grp";
 589                                                 sirf,function =
 590                                                         "usp2_uart_nostreamctrl";
 591                                         };
 592                                 };
 593                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
 594                                         usb0_utmi_drvbus {
 595                                                 sirf,pins = "usb0_utmi_drvbusgrp";
 596                                                 sirf,function = "usb0_utmi_drvbus";
 597                                         };
 598                                 };
 599                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 600                                         usb1_utmi_drvbus {
 601                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 602                                                 sirf,function = "usb1_utmi_drvbus";
 603                                         };
 604                                 };
 605                                 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
 606                                         usb1_dp_dn {
 607                                                 sirf,pins = "usb1_dp_dngrp";
 608                                                 sirf,function = "usb1_dp_dn";
 609                                         };
 610                                 };
 611                                 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
 612                                         uart1_route_io_usb1 {
 613                                                 sirf,pins = "uart1_route_io_usb1grp";
 614                                                 sirf,function = "uart1_route_io_usb1";
 615                                         };
 616                                 };
 617                                 warm_rst_pins_a: warm_rst@0 {
 618                                         warm_rst {
 619                                                 sirf,pins = "warm_rstgrp";
 620                                                 sirf,function = "warm_rst";
 621                                         };
 622                                 };
 623                                 pulse_count_pins_a: pulse_count@0 {
 624                                         pulse_count {
 625                                                 sirf,pins = "pulse_countgrp";
 626                                                 sirf,function = "pulse_count";
 627                                         };
 628                                 };
 629                                 cko0_pins_a: cko0@0 {
 630                                         cko0 {
 631                                                 sirf,pins = "cko0grp";
 632                                                 sirf,function = "cko0";
 633                                         };
 634                                 };
 635                                 cko1_pins_a: cko1@0 {
 636                                         cko1 {
 637                                                 sirf,pins = "cko1grp";
 638                                                 sirf,function = "cko1";
 639                                         };
 640                                 };
 641                         };
 642
 643                         pwm@b0130000 {
 644                                 compatible = "sirf,prima2-pwm";
 645                                 reg = <0xb0130000 0x10000>;
 646                                 clocks = <&clks 21>;
 647                         };
 648
 649                         efusesys@b0140000 {
 650                                 compatible = "sirf,prima2-efuse";
 651                                 reg = <0xb0140000 0x10000>;
 652                                 clocks = <&clks 22>;
 653                         };
 654
 655                         pulsec@b0150000 {
 656                                 compatible = "sirf,prima2-pulsec";
 657                                 reg = <0xb0150000 0x10000>;
 658                                 interrupts = <48>;
 659                                 clocks = <&clks 23>;
 660                         };
 661
 662                         pci-iobg {
 663                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 664                                 #address-cells = <1>;
 665                                 #size-cells = <1>;
 666                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 667
 668                                 sd0: sdhci@56000000 {
 669                                         cell-index = <0>;
 670                                         compatible = "sirf,prima2-sdhc";
 671                                         reg = <0x56000000 0x100000>;
 672                                         interrupts = <38>;
 673                                         status = "disabled";
 674                                         bus-width = <8>;
 675                                         clocks = <&clks 36>;
 676                                 };
 677
 678                                 sd1: sdhci@56100000 {
 679                                         cell-index = <1>;
 680                                         compatible = "sirf,prima2-sdhc";
 681                                         reg = <0x56100000 0x100000>;
 682                                         interrupts = <38>;
 683                                         status = "disabled";
 684                                         bus-width = <4>;
 685                                         clocks = <&clks 36>;
 686                                 };
 687
 688                                 sd2: sdhci@56200000 {
 689                                         cell-index = <2>;
 690                                         compatible = "sirf,prima2-sdhc";
 691                                         reg = <0x56200000 0x100000>;
 692                                         interrupts = <23>;
 693                                         status = "disabled";
 694                                         clocks = <&clks 37>;
 695                                 };
 696
 697                                 sd3: sdhci@56300000 {
 698                                         cell-index = <3>;
 699                                         compatible = "sirf,prima2-sdhc";
 700                                         reg = <0x56300000 0x100000>;
 701                                         interrupts = <23>;
 702                                         status = "disabled";
 703                                         clocks = <&clks 37>;
 704                                 };
 705
 706                                 sd4: sdhci@56400000 {
 707                                         cell-index = <4>;
 708                                         compatible = "sirf,prima2-sdhc";
 709                                         reg = <0x56400000 0x100000>;
 710                                         interrupts = <39>;
 711                                         status = "disabled";
 712                                         clocks = <&clks 38>;
 713                                 };
 714
 715                                 sd5: sdhci@56500000 {
 716                                         cell-index = <5>;
 717                                         compatible = "sirf,prima2-sdhc";
 718                                         reg = <0x56500000 0x100000>;
 719                                         interrupts = <39>;
 720                                         clocks = <&clks 38>;
 721                                 };
 722
 723                                 pci-copy@57900000 {
 724                                         compatible = "sirf,prima2-pcicp";
 725                                         reg = <0x57900000 0x100000>;
 726                                         interrupts = <40>;
 727                                 };
 728
 729                                 rom-interface@57a00000 {
 730                                         compatible = "sirf,prima2-romif";
 731                                         reg = <0x57a00000 0x100000>;
 732                                 };
 733                         };
 734                 };
 735
 736                 rtc-iobg {
 737                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 738                         #address-cells = <1>;
 739                         #size-cells = <1>;
 740                         reg = <0x80030000 0x10000>;
 741
 742                         gpsrtc@1000 {
 743                                 compatible = "sirf,prima2-gpsrtc";
 744                                 reg = <0x1000 0x1000>;
 745                                 interrupts = <55 56 57>;
 746                         };
 747
 748                         sysrtc@2000 {
 749                                 compatible = "sirf,prima2-sysrtc";
 750                                 reg = <0x2000 0x1000>;
 751                                 interrupts = <52 53 54>;
 752                         };
 753
 754                         minigpsrtc@2000 {
 755                                 compatible = "sirf,prima2-minigpsrtc";
 756                                 reg = <0x2000 0x1000>;
 757                                 interrupts = <54>;
 758                         };
 759
 760                         pwrc@3000 {
 761                                 compatible = "sirf,prima2-pwrc";
 762                                 reg = <0x3000 0x1000>;
 763                                 interrupts = <32>;
 764                         };
 765                 };
 766
 767                 uus-iobg {
 768                         compatible = "simple-bus";
 769                         #address-cells = <1>;
 770                         #size-cells = <1>;
 771                         ranges = <0xb8000000 0xb8000000 0x40000>;
 772
 773                         usb0: usb@b00e0000 {
 774                                 compatible = "chipidea,ci13611a-prima2";
 775                                 reg = <0xb8000000 0x10000>;
 776                                 interrupts = <10>;
 777                                 clocks = <&clks 40>;
 778                         };
 779
 780                         usb1: usb@b00f0000 {
 781                                 compatible = "chipidea,ci13611a-prima2";
 782                                 reg = <0xb8010000 0x10000>;
 783                                 interrupts = <11>;
 784                                 clocks = <&clks 41>;
 785                         };
 786
 787                         sata@b00f0000 {
 788                                 compatible = "synopsys,dwc-ahsata";
 789                                 reg = <0xb8020000 0x10000>;
 790                                 interrupts = <37>;
 791                         };
 792
 793                         security@b00f0000 {
 794                                 compatible = "sirf,prima2-security";
 795                                 reg = <0xb8030000 0x10000>;
 796                                 interrupts = <42>;
 797                                 clocks = <&clks 7>;
 798                         };
 799                 };
 800         };
 801 };