Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Carveout for multimedia usecases
  11  * It should be the last 48MB of the first 512MB memory part
  12  * In theory, it should not even exist. That zone should be reserved
  13  * dynamically during the .reserve callback.
  14  */
  15 /memreserve/ 0x9d000000 0x03000000;
  16
  17 /include/ "skeleton.dtsi"
  18
  19 / {
  20         compatible = "ti,omap4430", "ti,omap4";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 cpu@0 {
  32                         compatible = "arm,cortex-a9";
  33                         next-level-cache = <&L2>;
  34                 };
  35                 cpu@1 {
  36                         compatible = "arm,cortex-a9";
  37                         next-level-cache = <&L2>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@48241000 {
  42                 compatible = "arm,cortex-a9-gic";
  43                 interrupt-controller;
  44                 #interrupt-cells = <3>;
  45                 reg = <0x48241000 0x1000>,
  46                       <0x48240100 0x0100>;
  47         };
  48
  49         L2: l2-cache-controller@48242000 {
  50                 compatible = "arm,pl310-cache";
  51                 reg = <0x48242000 0x1000>;
  52                 cache-unified;
  53                 cache-level = <2>;
  54         };
  55
  56         local-timer@0x48240600 {
  57                 compatible = "arm,cortex-a9-twd-timer";
  58                 reg = <0x48240600 0x20>;
  59                 interrupts = <1 13 0x304>;
  60         };
  61
  62         /*
  63          * The soc node represents the soc top level view. It is uses for IPs
  64          * that are not memory mapped in the MPU view or for the MPU itself.
  65          */
  66         soc {
  67                 compatible = "ti,omap-infra";
  68                 mpu {
  69                         compatible = "ti,omap4-mpu";
  70                         ti,hwmods = "mpu";
  71                 };
  72
  73                 dsp {
  74                         compatible = "ti,omap3-c64";
  75                         ti,hwmods = "dsp";
  76                 };
  77
  78                 iva {
  79                         compatible = "ti,ivahd";
  80                         ti,hwmods = "iva";
  81                 };
  82         };
  83
  84         /*
  85          * XXX: Use a flat representation of the OMAP4 interconnect.
  86          * The real OMAP interconnect network is quite complex.
  87          * Since that will not bring real advantage to represent that in DT for
  88          * the moment, just use a fake OCP bus entry to represent the whole bus
  89          * hierarchy.
  90          */
  91         ocp {
  92                 compatible = "ti,omap4-l3-noc", "simple-bus";
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95                 ranges;
  96                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
  97                 reg = <0x44000000 0x1000>,
  98                       <0x44800000 0x2000>,
  99                       <0x45000000 0x1000>;
 100                 interrupts = <0 9 0x4>,
 101                              <0 10 0x4>;
 102
 103                 counter32k: counter@4a304000 {
 104                         compatible = "ti,omap-counter32k";
 105                         reg = <0x4a304000 0x20>;
 106                         ti,hwmods = "counter_32k";
 107                 };
 108
 109                 omap4_pmx_core: pinmux@4a100040 {
 110                         compatible = "ti,omap4-padconf", "pinctrl-single";
 111                         reg = <0x4a100040 0x0196>;
 112                         #address-cells = <1>;
 113                         #size-cells = <0>;
 114                         pinctrl-single,register-width = <16>;
 115                         pinctrl-single,function-mask = <0x7fff>;
 116                 };
 117                 omap4_pmx_wkup: pinmux@4a31e040 {
 118                         compatible = "ti,omap4-padconf", "pinctrl-single";
 119                         reg = <0x4a31e040 0x0038>;
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         pinctrl-single,register-width = <16>;
 123                         pinctrl-single,function-mask = <0x7fff>;
 124                 };
 125
 126                 sdma: dma-controller@4a056000 {
 127                         compatible = "ti,omap4430-sdma";
 128                         reg = <0x4a056000 0x1000>;
 129                         interrupts = <0 12 0x4>,
 130                                      <0 13 0x4>,
 131                                      <0 14 0x4>,
 132                                      <0 15 0x4>;
 133                         #dma-cells = <1>;
 134                         #dma-channels = <32>;
 135                         #dma-requests = <127>;
 136                 };
 137
 138                 gpio1: gpio@4a310000 {
 139                         compatible = "ti,omap4-gpio";
 140                         reg = <0x4a310000 0x200>;
 141                         interrupts = <0 29 0x4>;
 142                         ti,hwmods = "gpio1";
 143                         ti,gpio-always-on;
 144                         gpio-controller;
 145                         #gpio-cells = <2>;
 146                         interrupt-controller;
 147                         #interrupt-cells = <2>;
 148                 };
 149
 150                 gpio2: gpio@48055000 {
 151                         compatible = "ti,omap4-gpio";
 152                         reg = <0x48055000 0x200>;
 153                         interrupts = <0 30 0x4>;
 154                         ti,hwmods = "gpio2";
 155                         gpio-controller;
 156                         #gpio-cells = <2>;
 157                         interrupt-controller;
 158                         #interrupt-cells = <2>;
 159                 };
 160
 161                 gpio3: gpio@48057000 {
 162                         compatible = "ti,omap4-gpio";
 163                         reg = <0x48057000 0x200>;
 164                         interrupts = <0 31 0x4>;
 165                         ti,hwmods = "gpio3";
 166                         gpio-controller;
 167                         #gpio-cells = <2>;
 168                         interrupt-controller;
 169                         #interrupt-cells = <2>;
 170                 };
 171
 172                 gpio4: gpio@48059000 {
 173                         compatible = "ti,omap4-gpio";
 174                         reg = <0x48059000 0x200>;
 175                         interrupts = <0 32 0x4>;
 176                         ti,hwmods = "gpio4";
 177                         gpio-controller;
 178                         #gpio-cells = <2>;
 179                         interrupt-controller;
 180                         #interrupt-cells = <2>;
 181                 };
 182
 183                 gpio5: gpio@4805b000 {
 184                         compatible = "ti,omap4-gpio";
 185                         reg = <0x4805b000 0x200>;
 186                         interrupts = <0 33 0x4>;
 187                         ti,hwmods = "gpio5";
 188                         gpio-controller;
 189                         #gpio-cells = <2>;
 190                         interrupt-controller;
 191                         #interrupt-cells = <2>;
 192                 };
 193
 194                 gpio6: gpio@4805d000 {
 195                         compatible = "ti,omap4-gpio";
 196                         reg = <0x4805d000 0x200>;
 197                         interrupts = <0 34 0x4>;
 198                         ti,hwmods = "gpio6";
 199                         gpio-controller;
 200                         #gpio-cells = <2>;
 201                         interrupt-controller;
 202                         #interrupt-cells = <2>;
 203                 };
 204
 205                 gpmc: gpmc@50000000 {
 206                         compatible = "ti,omap4430-gpmc";
 207                         reg = <0x50000000 0x1000>;
 208                         #address-cells = <2>;
 209                         #size-cells = <1>;
 210                         interrupts = <0 20 0x4>;
 211                         gpmc,num-cs = <8>;
 212                         gpmc,num-waitpins = <4>;
 213                         ti,hwmods = "gpmc";
 214                 };
 215
 216                 uart1: serial@4806a000 {
 217                         compatible = "ti,omap4-uart";
 218                         reg = <0x4806a000 0x100>;
 219                         interrupts = <0 72 0x4>;
 220                         ti,hwmods = "uart1";
 221                         clock-frequency = <48000000>;
 222                 };
 223
 224                 uart2: serial@4806c000 {
 225                         compatible = "ti,omap4-uart";
 226                         reg = <0x4806c000 0x100>;
 227                         interrupts = <0 73 0x4>;
 228                         ti,hwmods = "uart2";
 229                         clock-frequency = <48000000>;
 230                 };
 231
 232                 uart3: serial@48020000 {
 233                         compatible = "ti,omap4-uart";
 234                         reg = <0x48020000 0x100>;
 235                         interrupts = <0 74 0x4>;
 236                         ti,hwmods = "uart3";
 237                         clock-frequency = <48000000>;
 238                 };
 239
 240                 uart4: serial@4806e000 {
 241                         compatible = "ti,omap4-uart";
 242                         reg = <0x4806e000 0x100>;
 243                         interrupts = <0 70 0x4>;
 244                         ti,hwmods = "uart4";
 245                         clock-frequency = <48000000>;
 246                 };
 247
 248                 i2c1: i2c@48070000 {
 249                         compatible = "ti,omap4-i2c";
 250                         reg = <0x48070000 0x100>;
 251                         interrupts = <0 56 0x4>;
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         ti,hwmods = "i2c1";
 255                 };
 256
 257                 i2c2: i2c@48072000 {
 258                         compatible = "ti,omap4-i2c";
 259                         reg = <0x48072000 0x100>;
 260                         interrupts = <0 57 0x4>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         ti,hwmods = "i2c2";
 264                 };
 265
 266                 i2c3: i2c@48060000 {
 267                         compatible = "ti,omap4-i2c";
 268                         reg = <0x48060000 0x100>;
 269                         interrupts = <0 61 0x4>;
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                         ti,hwmods = "i2c3";
 273                 };
 274
 275                 i2c4: i2c@48350000 {
 276                         compatible = "ti,omap4-i2c";
 277                         reg = <0x48350000 0x100>;
 278                         interrupts = <0 62 0x4>;
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         ti,hwmods = "i2c4";
 282                 };
 283
 284                 mcspi1: spi@48098000 {
 285                         compatible = "ti,omap4-mcspi";
 286                         reg = <0x48098000 0x200>;
 287                         interrupts = <0 65 0x4>;
 288                         #address-cells = <1>;
 289                         #size-cells = <0>;
 290                         ti,hwmods = "mcspi1";
 291                         ti,spi-num-cs = <4>;
 292                         dmas = <&sdma 35>,
 293                                <&sdma 36>,
 294                                <&sdma 37>,
 295                                <&sdma 38>,
 296                                <&sdma 39>,
 297                                <&sdma 40>,
 298                                <&sdma 41>,
 299                                <&sdma 42>;
 300                         dma-names = "tx0", "rx0", "tx1", "rx1",
 301                                     "tx2", "rx2", "tx3", "rx3";
 302                 };
 303
 304                 mcspi2: spi@4809a000 {
 305                         compatible = "ti,omap4-mcspi";
 306                         reg = <0x4809a000 0x200>;
 307                         interrupts = <0 66 0x4>;
 308                         #address-cells = <1>;
 309                         #size-cells = <0>;
 310                         ti,hwmods = "mcspi2";
 311                         ti,spi-num-cs = <2>;
 312                         dmas = <&sdma 43>,
 313                                <&sdma 44>,
 314                                <&sdma 45>,
 315                                <&sdma 46>;
 316                         dma-names = "tx0", "rx0", "tx1", "rx1";
 317                 };
 318
 319                 mcspi3: spi@480b8000 {
 320                         compatible = "ti,omap4-mcspi";
 321                         reg = <0x480b8000 0x200>;
 322                         interrupts = <0 91 0x4>;
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         ti,hwmods = "mcspi3";
 326                         ti,spi-num-cs = <2>;
 327                         dmas = <&sdma 15>, <&sdma 16>;
 328                         dma-names = "tx0", "rx0";
 329                 };
 330
 331                 mcspi4: spi@480ba000 {
 332                         compatible = "ti,omap4-mcspi";
 333                         reg = <0x480ba000 0x200>;
 334                         interrupts = <0 48 0x4>;
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         ti,hwmods = "mcspi4";
 338                         ti,spi-num-cs = <1>;
 339                         dmas = <&sdma 70>, <&sdma 71>;
 340                         dma-names = "tx0", "rx0";
 341                 };
 342
 343                 mmc1: mmc@4809c000 {
 344                         compatible = "ti,omap4-hsmmc";
 345                         reg = <0x4809c000 0x400>;
 346                         interrupts = <0 83 0x4>;
 347                         ti,hwmods = "mmc1";
 348                         ti,dual-volt;
 349                         ti,needs-special-reset;
 350                         dmas = <&sdma 61>, <&sdma 62>;
 351                         dma-names = "tx", "rx";
 352                 };
 353
 354                 mmc2: mmc@480b4000 {
 355                         compatible = "ti,omap4-hsmmc";
 356                         reg = <0x480b4000 0x400>;
 357                         interrupts = <0 86 0x4>;
 358                         ti,hwmods = "mmc2";
 359                         ti,needs-special-reset;
 360                         dmas = <&sdma 47>, <&sdma 48>;
 361                         dma-names = "tx", "rx";
 362                 };
 363
 364                 mmc3: mmc@480ad000 {
 365                         compatible = "ti,omap4-hsmmc";
 366                         reg = <0x480ad000 0x400>;
 367                         interrupts = <0 94 0x4>;
 368                         ti,hwmods = "mmc3";
 369                         ti,needs-special-reset;
 370                         dmas = <&sdma 77>, <&sdma 78>;
 371                         dma-names = "tx", "rx";
 372                 };
 373
 374                 mmc4: mmc@480d1000 {
 375                         compatible = "ti,omap4-hsmmc";
 376                         reg = <0x480d1000 0x400>;
 377                         interrupts = <0 96 0x4>;
 378                         ti,hwmods = "mmc4";
 379                         ti,needs-special-reset;
 380                         dmas = <&sdma 57>, <&sdma 58>;
 381                         dma-names = "tx", "rx";
 382                 };
 383
 384                 mmc5: mmc@480d5000 {
 385                         compatible = "ti,omap4-hsmmc";
 386                         reg = <0x480d5000 0x400>;
 387                         interrupts = <0 59 0x4>;
 388                         ti,hwmods = "mmc5";
 389                         ti,needs-special-reset;
 390                         dmas = <&sdma 59>, <&sdma 60>;
 391                         dma-names = "tx", "rx";
 392                 };
 393
 394                 wdt2: wdt@4a314000 {
 395                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 396                         reg = <0x4a314000 0x80>;
 397                         interrupts = <0 80 0x4>;
 398                         ti,hwmods = "wd_timer2";
 399                 };
 400
 401                 mcpdm: mcpdm@40132000 {
 402                         compatible = "ti,omap4-mcpdm";
 403                         reg = <0x40132000 0x7f>, /* MPU private access */
 404                               <0x49032000 0x7f>; /* L3 Interconnect */
 405                         reg-names = "mpu", "dma";
 406                         interrupts = <0 112 0x4>;
 407                         ti,hwmods = "mcpdm";
 408                         dmas = <&sdma 65>,
 409                                <&sdma 66>;
 410                         dma-names = "up_link", "dn_link";
 411                 };
 412
 413                 dmic: dmic@4012e000 {
 414                         compatible = "ti,omap4-dmic";
 415                         reg = <0x4012e000 0x7f>, /* MPU private access */
 416                               <0x4902e000 0x7f>; /* L3 Interconnect */
 417                         reg-names = "mpu", "dma";
 418                         interrupts = <0 114 0x4>;
 419                         ti,hwmods = "dmic";
 420                         dmas = <&sdma 67>;
 421                         dma-names = "up_link";
 422                 };
 423
 424                 mcbsp1: mcbsp@40122000 {
 425                         compatible = "ti,omap4-mcbsp";
 426                         reg = <0x40122000 0xff>, /* MPU private access */
 427                               <0x49022000 0xff>; /* L3 Interconnect */
 428                         reg-names = "mpu", "dma";
 429                         interrupts = <0 17 0x4>;
 430                         interrupt-names = "common";
 431                         ti,buffer-size = <128>;
 432                         ti,hwmods = "mcbsp1";
 433                         dmas = <&sdma 33>,
 434                                <&sdma 34>;
 435                         dma-names = "tx", "rx";
 436                 };
 437
 438                 mcbsp2: mcbsp@40124000 {
 439                         compatible = "ti,omap4-mcbsp";
 440                         reg = <0x40124000 0xff>, /* MPU private access */
 441                               <0x49024000 0xff>; /* L3 Interconnect */
 442                         reg-names = "mpu", "dma";
 443                         interrupts = <0 22 0x4>;
 444                         interrupt-names = "common";
 445                         ti,buffer-size = <128>;
 446                         ti,hwmods = "mcbsp2";
 447                         dmas = <&sdma 17>,
 448                                <&sdma 18>;
 449                         dma-names = "tx", "rx";
 450                 };
 451
 452                 mcbsp3: mcbsp@40126000 {
 453                         compatible = "ti,omap4-mcbsp";
 454                         reg = <0x40126000 0xff>, /* MPU private access */
 455                               <0x49026000 0xff>; /* L3 Interconnect */
 456                         reg-names = "mpu", "dma";
 457                         interrupts = <0 23 0x4>;
 458                         interrupt-names = "common";
 459                         ti,buffer-size = <128>;
 460                         ti,hwmods = "mcbsp3";
 461                         dmas = <&sdma 19>,
 462                                <&sdma 20>;
 463                         dma-names = "tx", "rx";
 464                 };
 465
 466                 mcbsp4: mcbsp@48096000 {
 467                         compatible = "ti,omap4-mcbsp";
 468                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 469                         reg-names = "mpu";
 470                         interrupts = <0 16 0x4>;
 471                         interrupt-names = "common";
 472                         ti,buffer-size = <128>;
 473                         ti,hwmods = "mcbsp4";
 474                         dmas = <&sdma 31>,
 475                                <&sdma 32>;
 476                         dma-names = "tx", "rx";
 477                 };
 478
 479                 keypad: keypad@4a31c000 {
 480                         compatible = "ti,omap4-keypad";
 481                         reg = <0x4a31c000 0x80>;
 482                         interrupts = <0 120 0x4>;
 483                         reg-names = "mpu";
 484                         ti,hwmods = "kbd";
 485                 };
 486
 487                 emif1: emif@4c000000 {
 488                         compatible = "ti,emif-4d";
 489                         reg = <0x4c000000 0x100>;
 490                         interrupts = <0 110 0x4>;
 491                         ti,hwmods = "emif1";
 492                         phy-type = <1>;
 493                         hw-caps-read-idle-ctrl;
 494                         hw-caps-ll-interface;
 495                         hw-caps-temp-alert;
 496                 };
 497
 498                 emif2: emif@4d000000 {
 499                         compatible = "ti,emif-4d";
 500                         reg = <0x4d000000 0x100>;
 501                         interrupts = <0 111 0x4>;
 502                         ti,hwmods = "emif2";
 503                         phy-type = <1>;
 504                         hw-caps-read-idle-ctrl;
 505                         hw-caps-ll-interface;
 506                         hw-caps-temp-alert;
 507                 };
 508
 509                 ocp2scp@4a0ad000 {
 510                         compatible = "ti,omap-ocp2scp";
 511                         reg = <0x4a0ad000 0x1f>;
 512                         #address-cells = <1>;
 513                         #size-cells = <1>;
 514                         ranges;
 515                         ti,hwmods = "ocp2scp_usb_phy";
 516                         usb2_phy: usb2phy@4a0ad080 {
 517                                 compatible = "ti,omap-usb2";
 518                                 reg = <0x4a0ad080 0x58>;
 519                                 ctrl-module = <&omap_control_usb>;
 520                         };
 521                 };
 522
 523                 timer1: timer@4a318000 {
 524                         compatible = "ti,omap3430-timer";
 525                         reg = <0x4a318000 0x80>;
 526                         interrupts = <0 37 0x4>;
 527                         ti,hwmods = "timer1";
 528                         ti,timer-alwon;
 529                 };
 530
 531                 timer2: timer@48032000 {
 532                         compatible = "ti,omap3430-timer";
 533                         reg = <0x48032000 0x80>;
 534                         interrupts = <0 38 0x4>;
 535                         ti,hwmods = "timer2";
 536                 };
 537
 538                 timer3: timer@48034000 {
 539                         compatible = "ti,omap4430-timer";
 540                         reg = <0x48034000 0x80>;
 541                         interrupts = <0 39 0x4>;
 542                         ti,hwmods = "timer3";
 543                 };
 544
 545                 timer4: timer@48036000 {
 546                         compatible = "ti,omap4430-timer";
 547                         reg = <0x48036000 0x80>;
 548                         interrupts = <0 40 0x4>;
 549                         ti,hwmods = "timer4";
 550                 };
 551
 552                 timer5: timer@40138000 {
 553                         compatible = "ti,omap4430-timer";
 554                         reg = <0x40138000 0x80>,
 555                               <0x49038000 0x80>;
 556                         interrupts = <0 41 0x4>;
 557                         ti,hwmods = "timer5";
 558                         ti,timer-dsp;
 559                 };
 560
 561                 timer6: timer@4013a000 {
 562                         compatible = "ti,omap4430-timer";
 563                         reg = <0x4013a000 0x80>,
 564                               <0x4903a000 0x80>;
 565                         interrupts = <0 42 0x4>;
 566                         ti,hwmods = "timer6";
 567                         ti,timer-dsp;
 568                 };
 569
 570                 timer7: timer@4013c000 {
 571                         compatible = "ti,omap4430-timer";
 572                         reg = <0x4013c000 0x80>,
 573                               <0x4903c000 0x80>;
 574                         interrupts = <0 43 0x4>;
 575                         ti,hwmods = "timer7";
 576                         ti,timer-dsp;
 577                 };
 578
 579                 timer8: timer@4013e000 {
 580                         compatible = "ti,omap4430-timer";
 581                         reg = <0x4013e000 0x80>,
 582                               <0x4903e000 0x80>;
 583                         interrupts = <0 44 0x4>;
 584                         ti,hwmods = "timer8";
 585                         ti,timer-pwm;
 586                         ti,timer-dsp;
 587                 };
 588
 589                 timer9: timer@4803e000 {
 590                         compatible = "ti,omap4430-timer";
 591                         reg = <0x4803e000 0x80>;
 592                         interrupts = <0 45 0x4>;
 593                         ti,hwmods = "timer9";
 594                         ti,timer-pwm;
 595                 };
 596
 597                 timer10: timer@48086000 {
 598                         compatible = "ti,omap3430-timer";
 599                         reg = <0x48086000 0x80>;
 600                         interrupts = <0 46 0x4>;
 601                         ti,hwmods = "timer10";
 602                         ti,timer-pwm;
 603                 };
 604
 605                 timer11: timer@48088000 {
 606                         compatible = "ti,omap4430-timer";
 607                         reg = <0x48088000 0x80>;
 608                         interrupts = <0 47 0x4>;
 609                         ti,hwmods = "timer11";
 610                         ti,timer-pwm;
 611                 };
 612
 613                 usbhstll: usbhstll@4a062000 {
 614                         compatible = "ti,usbhs-tll";
 615                         reg = <0x4a062000 0x1000>;
 616                         interrupts = <0 78 0x4>;
 617                         ti,hwmods = "usb_tll_hs";
 618                 };
 619
 620                 usbhshost: usbhshost@4a064000 {
 621                         compatible = "ti,usbhs-host";
 622                         reg = <0x4a064000 0x800>;
 623                         ti,hwmods = "usb_host_hs";
 624                         #address-cells = <1>;
 625                         #size-cells = <1>;
 626                         ranges;
 627
 628                         usbhsohci: ohci@4a064800 {
 629                                 compatible = "ti,ohci-omap3", "usb-ohci";
 630                                 reg = <0x4a064800 0x400>;
 631                                 interrupt-parent = <&gic>;
 632                                 interrupts = <0 76 0x4>;
 633                         };
 634
 635                         usbhsehci: ehci@4a064c00 {
 636                                 compatible = "ti,ehci-omap", "usb-ehci";
 637                                 reg = <0x4a064c00 0x400>;
 638                                 interrupt-parent = <&gic>;
 639                                 interrupts = <0 77 0x4>;
 640                         };
 641                 };
 642
 643                 omap_control_usb: omap-control-usb@4a002300 {
 644                         compatible = "ti,omap-control-usb";
 645                         reg = <0x4a002300 0x4>,
 646                               <0x4a00233c 0x4>;
 647                         reg-names = "control_dev_conf", "otghs_control";
 648                         ti,type = <1>;
 649                 };
 650
 651                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 652                         compatible = "ti,omap4-musb";
 653                         reg = <0x4a0ab000 0x7ff>;
 654                         interrupts = <0 92 0x4>, <0 93 0x4>;
 655                         interrupt-names = "mc", "dma";
 656                         ti,hwmods = "usb_otg_hs";
 657                         usb-phy = <&usb2_phy>;
 658                         multipoint = <1>;
 659                         num-eps = <16>;
 660                         ram-bits = <12>;
 661                         ti,has-mailbox;
 662                 };
 663         };
 664 };