Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/armada-xp.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada XP family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  * Ben Dooks <ben.dooks@codethink.co.uk>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  *
  15  * Contains definitions specific to the Armada XP SoC that are not
  16  * common to all Armada SoCs.
  17  */
  18
  19 #include "armada-370-xp.dtsi"
  20
  21 / {
  22         model = "Marvell Armada XP family SoC";
  23         compatible = "marvell,armadaxp", "marvell,armada-370-xp";
  24
  25         aliases {
  26                 eth2 = &eth2;
  27         };
  28
  29         soc {
  30                 compatible = "marvell,armadaxp-mbus", "simple-bus";
  31
  32                 bootrom {
  33                         compatible = "marvell,bootrom";
  34                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
  35                 };
  36
  37                 internal-regs {
  38                         L2: l2-cache {
  39                                 compatible = "marvell,aurora-system-cache";
  40                                 reg = <0x08000 0x1000>;
  41                                 cache-id-part = <0x100>;
  42                                 wt-override;
  43                         };
  44
  45                         i2c0: i2c@11000 {
  46                                 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
  47                                 reg = <0x11000 0x100>;
  48                         };
  49
  50                         i2c1: i2c@11100 {
  51                                 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
  52                                 reg = <0x11100 0x100>;
  53                         };
  54
  55                         serial@12200 {
  56                                 compatible = "snps,dw-apb-uart";
  57                                 reg = <0x12200 0x100>;
  58                                 reg-shift = <2>;
  59                                 interrupts = <43>;
  60                                 reg-io-width = <1>;
  61                                 status = "disabled";
  62                         };
  63                         serial@12300 {
  64                                 compatible = "snps,dw-apb-uart";
  65                                 reg = <0x12300 0x100>;
  66                                 reg-shift = <2>;
  67                                 interrupts = <44>;
  68                                 reg-io-width = <1>;
  69                                 status = "disabled";
  70                         };
  71
  72                         system-controller@18200 {
  73                                 compatible = "marvell,armada-370-xp-system-controller";
  74                                 reg = <0x18200 0x500>;
  75                         };
  76
  77                         gateclk: clock-gating-control@18220 {
  78                                 compatible = "marvell,armada-xp-gating-clock";
  79                                 reg = <0x18220 0x4>;
  80                                 clocks = <&coreclk 0>;
  81                                 #clock-cells = <1>;
  82                         };
  83
  84                         coreclk: mvebu-sar@18230 {
  85                                 compatible = "marvell,armada-xp-core-clock";
  86                                 reg = <0x18230 0x08>;
  87                                 #clock-cells = <1>;
  88                         };
  89
  90                         thermal@182b0 {
  91                                 compatible = "marvell,armadaxp-thermal";
  92                                 reg = <0x182b0 0x4
  93                                         0x184d0 0x4>;
  94                                 status = "okay";
  95                         };
  96
  97                         cpuclk: clock-complex@18700 {
  98                                 #clock-cells = <1>;
  99                                 compatible = "marvell,armada-xp-cpu-clock";
 100                                 reg = <0x18700 0xA0>;
 101                                 clocks = <&coreclk 1>;
 102                         };
 103
 104                         interrupt-controller@20000 {
 105                               reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 106                         };
 107
 108                         timer@20300 {
 109                                 compatible = "marvell,armada-xp-timer";
 110                                 clocks = <&coreclk 2>, <&refclk>;
 111                                 clock-names = "nbclk", "fixed";
 112                         };
 113
 114                         armada-370-xp-pmsu@22000 {
 115                                 compatible = "marvell,armada-370-xp-pmsu";
 116                                 reg = <0x22100 0x400>, <0x20800 0x20>;
 117                         };
 118
 119                         eth2: ethernet@30000 {
 120                                 compatible = "marvell,armada-370-neta";
 121                                 reg = <0x30000 0x4000>;
 122                                 interrupts = <12>;
 123                                 clocks = <&gateclk 2>;
 124                                 status = "disabled";
 125                         };
 126
 127                         usb@50000 {
 128                                 clocks = <&gateclk 18>;
 129                         };
 130
 131                         usb@51000 {
 132                                 clocks = <&gateclk 19>;
 133                         };
 134
 135                         usb@52000 {
 136                                 compatible = "marvell,orion-ehci";
 137                                 reg = <0x52000 0x500>;
 138                                 interrupts = <47>;
 139                                 clocks = <&gateclk 20>;
 140                                 status = "disabled";
 141                         };
 142
 143                         xor@60900 {
 144                                 compatible = "marvell,orion-xor";
 145                                 reg = <0x60900 0x100
 146                                        0x60b00 0x100>;
 147                                 clocks = <&gateclk 22>;
 148                                 status = "okay";
 149
 150                                 xor10 {
 151                                         interrupts = <51>;
 152                                         dmacap,memcpy;
 153                                         dmacap,xor;
 154                                 };
 155                                 xor11 {
 156                                         interrupts = <52>;
 157                                         dmacap,memcpy;
 158                                         dmacap,xor;
 159                                         dmacap,memset;
 160                                 };
 161                         };
 162
 163                         xor@f0900 {
 164                                 compatible = "marvell,orion-xor";
 165                                 reg = <0xF0900 0x100
 166                                        0xF0B00 0x100>;
 167                                 clocks = <&gateclk 28>;
 168                                 status = "okay";
 169
 170                                 xor00 {
 171                                         interrupts = <94>;
 172                                         dmacap,memcpy;
 173                                         dmacap,xor;
 174                                 };
 175                                 xor01 {
 176                                         interrupts = <95>;
 177                                         dmacap,memcpy;
 178                                         dmacap,xor;
 179                                         dmacap,memset;
 180                                 };
 181                         };
 182                 };
 183         };
 184
 185         clocks {
 186                 /* 25 MHz reference crystal */
 187                 refclk: oscillator {
 188                         compatible = "fixed-clock";
 189                         #clock-cells = <0>;
 190                         clock-frequency = <25000000>;
 191                 };
 192         };
 193 };